Pub Date : 1900-01-01DOI: 10.2312/EGGH/EGGH91/175-190
L. Shen, F. A. J. Laarakker, E. Deprettere
A new space partitioning technique is elaborated. In part I of the paper [3], we proposed a shell-like structure which is to be superimposed on a uniform grid data structure and is adaptive to the local environment seen by a bundle of rays. Here we extend this segmentation by embedding it in a static partitioning which is determined by low resolution ray casting. This partitioning is useful in achieving a balanced computation while mapping it onto a pipelined parallel architecture. Moreover, a run-time control of workloads is applied during a subsequent high resolution ray casting so as to adjust low resolution partitioning. The technique has been tested on practical and randomly generated scenes. The performance evaluation of a pipelined parallel architecture has been done by queueing network simulation. Promising results have been obtained.
{"title":"Space Partitioning for Mapping Radiosity Computations onto a Pipelined Parallel Architecture (II)","authors":"L. Shen, F. A. J. Laarakker, E. Deprettere","doi":"10.2312/EGGH/EGGH91/175-190","DOIUrl":"https://doi.org/10.2312/EGGH/EGGH91/175-190","url":null,"abstract":"A new space partitioning technique is elaborated. In part I of the paper [3], we proposed a shell-like structure which is to be superimposed on a uniform grid data structure and is adaptive to the local environment seen by a bundle of rays. Here we extend this segmentation by embedding it in a static partitioning which is determined by low resolution ray casting. This partitioning is useful in achieving a balanced computation while mapping it onto a pipelined parallel architecture. Moreover, a run-time control of workloads is applied during a subsequent high resolution ray casting so as to adjust low resolution partitioning. The technique has been tested on practical and randomly generated scenes. The performance evaluation of a pipelined parallel architecture has been done by queueing network simulation. Promising results have been obtained.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"40 22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128474616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.2312/EGGH/EGGH88/067-084
J. Oldfield, Richard D. Williams, N. Wiseman, M. Brule
Quadtrees are attractive for storing and processing mages with area coherence, but performance has been limited by software overheads. A Content-Addressable Memory (CAM) with ternary storage allows single-cycle searches by pixel coordinate, quadrant or rectangle. To use thiS feature effectively the authors have reviewed a range of quadtree processing functions relevant to computer graphics and Image processing, and some new algorithms have been discovere. The proposed VLSI chip has microcoded logic on each row, as well as its CAM cells. This architecture has been simulated in fine detail with the aid of the Connection Machine as well as by much slower, conventional computers. The combination of quadtrees and CAMs offers significant improvement in performance for display systems and image processing.
{"title":"Content-Addressable Memories for Quadtree-Based Images","authors":"J. Oldfield, Richard D. Williams, N. Wiseman, M. Brule","doi":"10.2312/EGGH/EGGH88/067-084","DOIUrl":"https://doi.org/10.2312/EGGH/EGGH88/067-084","url":null,"abstract":"Quadtrees are attractive for storing and processing mages with area coherence, but performance has been limited by software overheads. A Content-Addressable Memory (CAM) with ternary storage allows single-cycle searches by pixel coordinate, quadrant or rectangle. To use thiS feature effectively the authors have reviewed a range of quadtree processing functions relevant to computer graphics and Image processing, and some new algorithms have been discovere. The proposed VLSI chip has microcoded logic on each row, as well as its CAM cells. This architecture has been simulated in fine detail with the aid of the Connection Machine as well as by much slower, conventional computers. The combination of quadtrees and CAMs offers significant improvement in performance for display systems and image processing.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"488 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113967172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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