Pub Date : 2021-08-30DOI: 10.1109/MLCAD52597.2021.9531234
Raviv Gal, E. Haber, Brian Irwin, Marwa Mouallem, Bilal Saleh, A. Ziv
In computer aided design (CAD), a core task is to optimize the parameters of noisy simulations. Derivative free optimization (DFO) methods are the most common choice for this task. In this paper, we show how four DFO methods, specifically implicit filtering (IF), simulated annealing (SA), genetic algorithms (GA), and particle swarm (PS), can be accelerated using a deep neural network (DNN) that acts as a surrogate model of the objective function. In particular, we demonstrate the applicability of the DNN accelerated DFO approach to the coverage directed generation (CDG) problem that is commonly solved by hardware verification teams.
{"title":"Using Deep Neural Networks And Derivative Free Optimization To Accelerate Coverage Closure","authors":"Raviv Gal, E. Haber, Brian Irwin, Marwa Mouallem, Bilal Saleh, A. Ziv","doi":"10.1109/MLCAD52597.2021.9531234","DOIUrl":"https://doi.org/10.1109/MLCAD52597.2021.9531234","url":null,"abstract":"In computer aided design (CAD), a core task is to optimize the parameters of noisy simulations. Derivative free optimization (DFO) methods are the most common choice for this task. In this paper, we show how four DFO methods, specifically implicit filtering (IF), simulated annealing (SA), genetic algorithms (GA), and particle swarm (PS), can be accelerated using a deep neural network (DNN) that acts as a surrogate model of the objective function. In particular, we demonstrate the applicability of the DNN accelerated DFO approach to the coverage directed generation (CDG) problem that is commonly solved by hardware verification teams.","PeriodicalId":210763,"journal":{"name":"2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126098390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-30DOI: 10.1109/MLCAD52597.2021.9531256
V. V. R. M. K. Muvva, Martin Rapp, J. Henkel, H. Amrouch, M. Wolf
A well-functioning thermal management system on the chip requires knowledge of the current temperature and the potential changes in temperature in the near future. This information is important for ensuring proactive thermal management on the chip. However, the limited number of sensors on the chip makes it difficult to accomplish this task. Hence we proposed a neural network based approach to predict the temperature map of the chip. To solve the problem, we have implemented two different neural networks, one is a feedforward network and the other uses recurrent neural networks. Our proposed method requires only performance counters measure to predict the temperature map of the chip during the runtime. Each of the two models shows promising results regarding the estimation of the temperature map on the chip. The recurrent neural network outperformed the feedforward neural network. Furthermore, both networks have been quantized, pruned, and the feedforward network has been compiled into FPGA logic. Therefore, the network could be embedded in the chip, whether it be an ASIC or an FPGA.
{"title":"On the Effectiveness of Quantization and Pruning on the Performance of FPGAs-based NN Temperature Estimation","authors":"V. V. R. M. K. Muvva, Martin Rapp, J. Henkel, H. Amrouch, M. Wolf","doi":"10.1109/MLCAD52597.2021.9531256","DOIUrl":"https://doi.org/10.1109/MLCAD52597.2021.9531256","url":null,"abstract":"A well-functioning thermal management system on the chip requires knowledge of the current temperature and the potential changes in temperature in the near future. This information is important for ensuring proactive thermal management on the chip. However, the limited number of sensors on the chip makes it difficult to accomplish this task. Hence we proposed a neural network based approach to predict the temperature map of the chip. To solve the problem, we have implemented two different neural networks, one is a feedforward network and the other uses recurrent neural networks. Our proposed method requires only performance counters measure to predict the temperature map of the chip during the runtime. Each of the two models shows promising results regarding the estimation of the temperature map on the chip. The recurrent neural network outperformed the feedforward neural network. Furthermore, both networks have been quantized, pruned, and the feedforward network has been compiled into FPGA logic. Therefore, the network could be embedded in the chip, whether it be an ASIC or an FPGA.","PeriodicalId":210763,"journal":{"name":"2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125643447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-30DOI: 10.1109/MLCAD52597.2021.9531219
Peng Huang, Xuan-Yi Lin, Yan-Jhih Wang, Tsung-Yi Ho
Along with the rapid growth in the market of the Internet of Things and electrical devices, the design flow of Printed Circuit Boards (PCBs) requires a more effective design methodology. As to design a PCB board, it is necessary to build a footprint of components first, containing manufacturing information such as outline, height, and other constraints for placing components on a PCB board. Footprint design can vary between different manufacturers, depending on their production technology, which means an electronic component can have distinctive footprints. Therefore, analyzing PCB footprint libraries can help to sort out footprint design rules, which can then be used for designing new footprints of the same type of components. In this paper, we adopt StackNet based on the ensemble learning method, using footprint images and numerical information for classification. Furthermore, we implement hierarchical clustering on the classification result to analyze the footprint design rules. Experimental results show our method can achieve higher accuracy than previous works.
{"title":"Ensemble Learning Based Electric Components Footprint Analysis","authors":"Peng Huang, Xuan-Yi Lin, Yan-Jhih Wang, Tsung-Yi Ho","doi":"10.1109/MLCAD52597.2021.9531219","DOIUrl":"https://doi.org/10.1109/MLCAD52597.2021.9531219","url":null,"abstract":"Along with the rapid growth in the market of the Internet of Things and electrical devices, the design flow of Printed Circuit Boards (PCBs) requires a more effective design methodology. As to design a PCB board, it is necessary to build a footprint of components first, containing manufacturing information such as outline, height, and other constraints for placing components on a PCB board. Footprint design can vary between different manufacturers, depending on their production technology, which means an electronic component can have distinctive footprints. Therefore, analyzing PCB footprint libraries can help to sort out footprint design rules, which can then be used for designing new footprints of the same type of components. In this paper, we adopt StackNet based on the ensemble learning method, using footprint images and numerical information for classification. Furthermore, we implement hierarchical clustering on the classification result to analyze the footprint design rules. Experimental results show our method can achieve higher accuracy than previous works.","PeriodicalId":210763,"journal":{"name":"2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130226389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-30DOI: 10.1109/MLCAD52597.2021.9531161
Erika S. Alcorta, A. Gerstlauer
Predicting coarse-grain variations in workload behavior during execution is essential for dynamic resource optimization of processor systems. Researchers have proposed various methods to first classify workloads into phases and then learn their long-term phase behavior to predict and anticipate phase changes. Early studies on phase prediction proposed table-based phase predictors. More recently, simple learning-based techniques such as decision trees have been explored. However, more recent advances in machine learning have not been applied to phase prediction so far. Furthermore, existing phase predictors have been studied only in connection with specific phase classifiers even though there is a wide range of classification methods. Early work in phase classification proposed various clustering methods that required access to source code. Some later studies used performance monitoring counters, but they only evaluated classifiers for specific contexts such as thermal modeling.In this work, we perform a comprehensive study of source-oblivious phase classification and prediction methods using hardware counters. We adapt classification techniques that were used with different inputs in the past and compare them to state-of-the-art hardware counter based classifiers. We further evaluate the accuracy of various phase predictors when coupled with different phase classifiers and evaluate a range of advanced machine learning techniques, including SVMs and LSTMs for workload phase prediction. We apply classification and prediction approaches to SPEC workloads running on an Intel Core-i9 platform. Results show that a two-level kmeans clustering combined with SVM-based phase change prediction provides the best tradeoff between accuracy and long-term stability. Additionally, the SVM predictor reduces the average prediction error by 80% when compared to a table-based predictor.
{"title":"Learning-Based Workload Phase Classification and Prediction Using Performance Monitoring Counters","authors":"Erika S. Alcorta, A. Gerstlauer","doi":"10.1109/MLCAD52597.2021.9531161","DOIUrl":"https://doi.org/10.1109/MLCAD52597.2021.9531161","url":null,"abstract":"Predicting coarse-grain variations in workload behavior during execution is essential for dynamic resource optimization of processor systems. Researchers have proposed various methods to first classify workloads into phases and then learn their long-term phase behavior to predict and anticipate phase changes. Early studies on phase prediction proposed table-based phase predictors. More recently, simple learning-based techniques such as decision trees have been explored. However, more recent advances in machine learning have not been applied to phase prediction so far. Furthermore, existing phase predictors have been studied only in connection with specific phase classifiers even though there is a wide range of classification methods. Early work in phase classification proposed various clustering methods that required access to source code. Some later studies used performance monitoring counters, but they only evaluated classifiers for specific contexts such as thermal modeling.In this work, we perform a comprehensive study of source-oblivious phase classification and prediction methods using hardware counters. We adapt classification techniques that were used with different inputs in the past and compare them to state-of-the-art hardware counter based classifiers. We further evaluate the accuracy of various phase predictors when coupled with different phase classifiers and evaluate a range of advanced machine learning techniques, including SVMs and LSTMs for workload phase prediction. We apply classification and prediction approaches to SPEC workloads running on an Intel Core-i9 platform. Results show that a two-level kmeans clustering combined with SVM-based phase change prediction provides the best tradeoff between accuracy and long-term stability. Additionally, the SVM predictor reduces the average prediction error by 80% when compared to a table-based predictor.","PeriodicalId":210763,"journal":{"name":"2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125597775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-30DOI: 10.1109/MLCAD52597.2021.9531245
Ahsan Saeed, Daniel Mueller-Gritschneder, Falk Rehm, A. Hamann, D. Ziegenbein, Ulf Schlichtmann, A. Gerstlauer
Early run-time prediction of co-running independent applications prior to application integration becomes challenging in multi-core processors. One of the most notable causes is the interference at the main memory subsystem, which results in significant degradation in application performance and response time in comparison to standalone execution. Currently available techniques for run-time prediction like traditional cycle-accurate simulations are slow, and analytical models are not accurate and time-consuming to build. By contrast, existing machine-learning-based approaches for run-time prediction simply do not account for interference. In this paper, we use a machine learning-based approach to train a model to correlate performance data (instructions and hardware performance counters) for a set of benchmark applications between the standalone and interference scenarios. After that, the trained model is used to predict the run-time of co-running applications in interference scenarios. In general, there is no straightforward one-to-one correspondence between samples obtained from the standalone and interference scenarios due to the different run-times, i.e. execution speeds. To address this, we developed a simple yet effective sample alignment algorithm, which is a key component in transforming interference prediction into a machine learning problem. In addition, we systematically identify the subset of features that have the highest positive impact on the model performance. Our approach is demonstrated to be effective and shows an average run-time prediction error, which is as low as 0.3% and 0.1% for two co-running applications.
{"title":"Learning based Memory Interference Prediction for Co-running Applications on Multi-Cores","authors":"Ahsan Saeed, Daniel Mueller-Gritschneder, Falk Rehm, A. Hamann, D. Ziegenbein, Ulf Schlichtmann, A. Gerstlauer","doi":"10.1109/MLCAD52597.2021.9531245","DOIUrl":"https://doi.org/10.1109/MLCAD52597.2021.9531245","url":null,"abstract":"Early run-time prediction of co-running independent applications prior to application integration becomes challenging in multi-core processors. One of the most notable causes is the interference at the main memory subsystem, which results in significant degradation in application performance and response time in comparison to standalone execution. Currently available techniques for run-time prediction like traditional cycle-accurate simulations are slow, and analytical models are not accurate and time-consuming to build. By contrast, existing machine-learning-based approaches for run-time prediction simply do not account for interference. In this paper, we use a machine learning-based approach to train a model to correlate performance data (instructions and hardware performance counters) for a set of benchmark applications between the standalone and interference scenarios. After that, the trained model is used to predict the run-time of co-running applications in interference scenarios. In general, there is no straightforward one-to-one correspondence between samples obtained from the standalone and interference scenarios due to the different run-times, i.e. execution speeds. To address this, we developed a simple yet effective sample alignment algorithm, which is a key component in transforming interference prediction into a machine learning problem. In addition, we systematically identify the subset of features that have the highest positive impact on the model performance. Our approach is demonstrated to be effective and shows an average run-time prediction error, which is as low as 0.3% and 0.1% for two co-running applications.","PeriodicalId":210763,"journal":{"name":"2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123087758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Before starting printed-circuit-board (PCB) design, it is usually very time-consuming for PCB and system designers to review a large amount of electronic component datasheets in order to determine the best integration of electronic components for the target electronic systems. Each datasheet may contain over hundred figures and tables, while the figures and tables usually present the most important electronic component specifications. This paper categorizes various figures, including tables, in electronic component datasheets, and proposes the ECS-YOLO model for massive figure extraction and classification in order to accelerate PCB design preparation process. The experimental results show that, compared with the state-of-the-art object detection model, the proposed ECS-YOLO can consistently achieve better accuracy for figure extraction and classification in electronic component datasheets.
{"title":"Massive Figure Extraction and Classification in Electronic Component Datasheets for Accelerating PCB Design Preparation","authors":"Kuan-Chun Chen, Chou-Chen Lee, Mark Po-Hung Lin, Yan-Jhih Wang, Yi-Ting Chen","doi":"10.1109/MLCAD52597.2021.9531275","DOIUrl":"https://doi.org/10.1109/MLCAD52597.2021.9531275","url":null,"abstract":"Before starting printed-circuit-board (PCB) design, it is usually very time-consuming for PCB and system designers to review a large amount of electronic component datasheets in order to determine the best integration of electronic components for the target electronic systems. Each datasheet may contain over hundred figures and tables, while the figures and tables usually present the most important electronic component specifications. This paper categorizes various figures, including tables, in electronic component datasheets, and proposes the ECS-YOLO model for massive figure extraction and classification in order to accelerate PCB design preparation process. The experimental results show that, compared with the state-of-the-art object detection model, the proposed ECS-YOLO can consistently achieve better accuracy for figure extraction and classification in electronic component datasheets.","PeriodicalId":210763,"journal":{"name":"2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117208365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-30DOI: 10.1109/MLCAD52597.2021.9531313
Zixuan Jiang, Ebrahim M. Songhori, Shen Wang, Anna Goldie, Azalia Mirhoseini, J. Jiang, Young-Joon Lee, David Z. Pan
In physical design, human designers typically place macros via trial and error, which is a Markov decision process. Reinforcement learning (RL) methods have demonstrated superhuman performance on the macro placement. In this paper, we propose an extension to this prior work [1]. We first describe the details of the policy and value network architecture. We replace the force-directed method with DREAMPlace for placing standard cells in the RL environment. We also compare our improved method with other academic placers on public benchmarks.
{"title":"Delving into Macro Placement with Reinforcement Learning","authors":"Zixuan Jiang, Ebrahim M. Songhori, Shen Wang, Anna Goldie, Azalia Mirhoseini, J. Jiang, Young-Joon Lee, David Z. Pan","doi":"10.1109/MLCAD52597.2021.9531313","DOIUrl":"https://doi.org/10.1109/MLCAD52597.2021.9531313","url":null,"abstract":"In physical design, human designers typically place macros via trial and error, which is a Markov decision process. Reinforcement learning (RL) methods have demonstrated superhuman performance on the macro placement. In this paper, we propose an extension to this prior work [1]. We first describe the details of the policy and value network architecture. We replace the force-directed method with DREAMPlace for placing standard cells in the RL environment. We also compare our improved method with other academic placers on public benchmarks.","PeriodicalId":210763,"journal":{"name":"2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131425715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-30DOI: 10.1109/MLCAD52597.2021.9531070
Daniela Sánchez Lopera, Lorenzo Servadei, Gamze Naz Kiprit, Souvik Hazra, R. Wille, W. Ecker
Driven by Moore’s law, the chip design complexity is steadily increasing. Electronic Design Automation (EDA) has been able to cope with the challenging very large-scale integration process, assuring scalability, reliability, and proper time-to-market. However, EDA approaches are time and resource-demanding, and they often do not guarantee optimal solutions. To alleviate these, Machine Learning (ML) has been incorporated into many stages of the design flow, such as in placement and routing. Many solutions employ Euclidean data and ML techniques without considering that many EDA objects are represented naturally as graphs. The trending Graph Neural Networks are an opportunity to solve EDA problems directly using graph structures for circuits, intermediate RTLs, and netlists. In this paper, we present a comprehensive review of the existing works linking the EDA flow for chip design and Graph Neural Networks.
{"title":"A Survey of Graph Neural Networks for Electronic Design Automation","authors":"Daniela Sánchez Lopera, Lorenzo Servadei, Gamze Naz Kiprit, Souvik Hazra, R. Wille, W. Ecker","doi":"10.1109/MLCAD52597.2021.9531070","DOIUrl":"https://doi.org/10.1109/MLCAD52597.2021.9531070","url":null,"abstract":"Driven by Moore’s law, the chip design complexity is steadily increasing. Electronic Design Automation (EDA) has been able to cope with the challenging very large-scale integration process, assuring scalability, reliability, and proper time-to-market. However, EDA approaches are time and resource-demanding, and they often do not guarantee optimal solutions. To alleviate these, Machine Learning (ML) has been incorporated into many stages of the design flow, such as in placement and routing. Many solutions employ Euclidean data and ML techniques without considering that many EDA objects are represented naturally as graphs. The trending Graph Neural Networks are an opportunity to solve EDA problems directly using graph structures for circuits, intermediate RTLs, and netlists. In this paper, we present a comprehensive review of the existing works linking the EDA flow for chip design and Graph Neural Networks.","PeriodicalId":210763,"journal":{"name":"2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126243398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-30DOI: 10.1109/MLCAD52597.2021.9531269
J. Spieck, S. Wildermann, Jürgen Teich
The mapping of soft real-time applications onto heterogeneous MPSoC architectures can have a high influence on execution properties like energy consumption or the number of deadline violations. In recent years, scenario-aware hybrid application mapping (HAM) has turned out as the state-of-the-art mapping method for input-dependent applications whose execution characteristics are in strong dependence on the input that shall be processed. In this work, we propose an extension of scenario-aware HAM that is capable of transferring its mapping strategy learned from a labeled source data domain using supervised learning into an unlabeled target domain that exhibits a shift in its data distribution. Our domain-adaptive HAM employs a run-time manager (RTM) that performs mapping selection and reconfiguration at run time based on general domain-invariant knowledge learned at design time that is valid for both the source and target domain. Evaluation based on two input-dependent applications and two MPSoC architectures demonstrates that our domain-adaptive HAM consistently outperforms state-of-the-art mapping procedures with regard to the number of deadline misses and energy consumption in presence of a domain shift. Furthermore, our HAM approach obtains results close to an explicit optimization for the target domain in a fraction of the necessary optimization time and without necessitating target labels.
{"title":"Domain-Adaptive Soft Real-Time Hybrid Application Mapping for MPSoCs","authors":"J. Spieck, S. Wildermann, Jürgen Teich","doi":"10.1109/MLCAD52597.2021.9531269","DOIUrl":"https://doi.org/10.1109/MLCAD52597.2021.9531269","url":null,"abstract":"The mapping of soft real-time applications onto heterogeneous MPSoC architectures can have a high influence on execution properties like energy consumption or the number of deadline violations. In recent years, scenario-aware hybrid application mapping (HAM) has turned out as the state-of-the-art mapping method for input-dependent applications whose execution characteristics are in strong dependence on the input that shall be processed. In this work, we propose an extension of scenario-aware HAM that is capable of transferring its mapping strategy learned from a labeled source data domain using supervised learning into an unlabeled target domain that exhibits a shift in its data distribution. Our domain-adaptive HAM employs a run-time manager (RTM) that performs mapping selection and reconfiguration at run time based on general domain-invariant knowledge learned at design time that is valid for both the source and target domain. Evaluation based on two input-dependent applications and two MPSoC architectures demonstrates that our domain-adaptive HAM consistently outperforms state-of-the-art mapping procedures with regard to the number of deadline misses and energy consumption in presence of a domain shift. Furthermore, our HAM approach obtains results close to an explicit optimization for the target domain in a fraction of the necessary optimization time and without necessitating target labels.","PeriodicalId":210763,"journal":{"name":"2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124568856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-30DOI: 10.1109/MLCAD52597.2021.9531299
F. Last, Ulf Schlichtmann
Supervised machine learning requires large amounts of labeled data for training. In power, performance and area (PPA) estimation of embedded memories, every new memory compiler version is considered independently of previous versions. Since the data of different memory compilers originate from similar domains, transfer learning may reduce the amount of supervised data required by pre-training PPA estimation neural networks on related domains. We show that provisioning times of PPA models for new compiler versions can be reduced significantly by exploiting similarities across versions and technology nodes. Through transfer learning, we shorten the time to provision PPA models for new compiler versions by 50% to 90%, which speeds up time-critical periods of the design cycle. This is achieved by requiring less than 6,500 ground truth samples for the target compiler to achieve average estimation errors of 0.35% instead of 13,000 samples. Using only 1,300 samples is sufficient to achieve an almost worst-case (98th percentile) error of approximately 3% and allows us to shorten model provisioning times from over 40 days to less than one week.
{"title":"Feeding Hungry Models Less: Deep Transfer Learning for Embedded Memory PPA Models : Special Session","authors":"F. Last, Ulf Schlichtmann","doi":"10.1109/MLCAD52597.2021.9531299","DOIUrl":"https://doi.org/10.1109/MLCAD52597.2021.9531299","url":null,"abstract":"Supervised machine learning requires large amounts of labeled data for training. In power, performance and area (PPA) estimation of embedded memories, every new memory compiler version is considered independently of previous versions. Since the data of different memory compilers originate from similar domains, transfer learning may reduce the amount of supervised data required by pre-training PPA estimation neural networks on related domains. We show that provisioning times of PPA models for new compiler versions can be reduced significantly by exploiting similarities across versions and technology nodes. Through transfer learning, we shorten the time to provision PPA models for new compiler versions by 50% to 90%, which speeds up time-critical periods of the design cycle. This is achieved by requiring less than 6,500 ground truth samples for the target compiler to achieve average estimation errors of 0.35% instead of 13,000 samples. Using only 1,300 samples is sufficient to achieve an almost worst-case (98th percentile) error of approximately 3% and allows us to shorten model provisioning times from over 40 days to less than one week.","PeriodicalId":210763,"journal":{"name":"2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127555042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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