Pub Date : 2012-06-20DOI: 10.1109/SIES.2012.6356564
Jonas Diemer, Daniel Thiele, R. Ernst
Ethernet is increasingly recognized as the future communication standard for distributed embedded systems in multiple domains such as industrial automation, automotive and avionics. A main motivation for this is cost and available data rate. A critical issue in the adoption of Ethernet in these domains is the timing of frame transfers, as many relevant applications require a guaranteed low-latency communication in order to meet real-time constraints. Ethernet AVB is an upcoming standard which addresses the timing issues by extending the existing strict-priority arbitration. Still, it needs to be evaluated whether these mechanism suffice for the targeted applications. For safety-critical applications, this can not only be done using intuition or simulation but requires a formal approach to assure the coverage of all worst-case corner cases. Hence, we present in this paper a formal worst-case analysis of the timing properties of Ethernet AVB and strict-priority Ethernet. This analysis mathematically determines safe upper bounds on the latency of frame transfers. Using this approach, we evaluate different topologies for a typical use-case in industrial automation.
{"title":"Formal worst-case timing analysis of Ethernet topologies with strict-priority and AVB switching","authors":"Jonas Diemer, Daniel Thiele, R. Ernst","doi":"10.1109/SIES.2012.6356564","DOIUrl":"https://doi.org/10.1109/SIES.2012.6356564","url":null,"abstract":"Ethernet is increasingly recognized as the future communication standard for distributed embedded systems in multiple domains such as industrial automation, automotive and avionics. A main motivation for this is cost and available data rate. A critical issue in the adoption of Ethernet in these domains is the timing of frame transfers, as many relevant applications require a guaranteed low-latency communication in order to meet real-time constraints. Ethernet AVB is an upcoming standard which addresses the timing issues by extending the existing strict-priority arbitration. Still, it needs to be evaluated whether these mechanism suffice for the targeted applications. For safety-critical applications, this can not only be done using intuition or simulation but requires a formal approach to assure the coverage of all worst-case corner cases. Hence, we present in this paper a formal worst-case analysis of the timing properties of Ethernet AVB and strict-priority Ethernet. This analysis mathematically determines safe upper bounds on the latency of frame transfers. Using this approach, we evaluate different topologies for a typical use-case in industrial automation.","PeriodicalId":219258,"journal":{"name":"7th IEEE International Symposium on Industrial Embedded Systems (SIES'12)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117061547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-20DOI: 10.1109/SIES.2012.6356592
Julian Wolf, Bernhard Fechner, S. Uhrig, T. Ungerer
Robustness and reliability are essential requirements of today's embedded systems. Especially errors in the control flow of a program, e.g. caused by transient errors, may lead to a faulty system behavior potentially with catastrophic consequences. Several methods for control flow checking have been proposed during the last decades. However, these techniques mostly focus on a correct sequence of application parts but not on the correct timing behavior of the control flow, which is essential for hard real-time systems. In this paper, we present a new approach which introduces fine-grained on-line timing checks for hard real-time systems combined with a lightweight control flow monitoring technique. The proposed approach is a hybrid hardware-software technique: We instrument the application code at compile-time by adding checkpoints, which contain temporal and logical information of the control flow. During run-time, a small hardware check unit connected to the core reads the instrumented data in order to verify the correctness of the application's control flow and timing behavior. The finegrained functionality of our mechanism allows a detection of many transient errors, associated with very low detection latency. It is no longer necessary to redundantly execute code in order to monitor anomalies. The hardware overhead is limited to a small check unit (only 0.5 % of chip space compared to the processor core); according to experimental results, the execution time overhead is only 10.6 % in the average case while the memory overhead is 12.3 %.
{"title":"Fine-grained timing and control flow error checking for hard real-time task execution","authors":"Julian Wolf, Bernhard Fechner, S. Uhrig, T. Ungerer","doi":"10.1109/SIES.2012.6356592","DOIUrl":"https://doi.org/10.1109/SIES.2012.6356592","url":null,"abstract":"Robustness and reliability are essential requirements of today's embedded systems. Especially errors in the control flow of a program, e.g. caused by transient errors, may lead to a faulty system behavior potentially with catastrophic consequences. Several methods for control flow checking have been proposed during the last decades. However, these techniques mostly focus on a correct sequence of application parts but not on the correct timing behavior of the control flow, which is essential for hard real-time systems. In this paper, we present a new approach which introduces fine-grained on-line timing checks for hard real-time systems combined with a lightweight control flow monitoring technique. The proposed approach is a hybrid hardware-software technique: We instrument the application code at compile-time by adding checkpoints, which contain temporal and logical information of the control flow. During run-time, a small hardware check unit connected to the core reads the instrumented data in order to verify the correctness of the application's control flow and timing behavior. The finegrained functionality of our mechanism allows a detection of many transient errors, associated with very low detection latency. It is no longer necessary to redundantly execute code in order to monitor anomalies. The hardware overhead is limited to a small check unit (only 0.5 % of chip space compared to the processor core); according to experimental results, the execution time overhead is only 10.6 % in the average case while the memory overhead is 12.3 %.","PeriodicalId":219258,"journal":{"name":"7th IEEE International Symposium on Industrial Embedded Systems (SIES'12)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122374871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-20DOI: 10.1109/SIES.2012.6356605
Sara Afshar, Farhang Nemati, Thomas Nolte
Semi-partitioned scheduling has been the subject of recent interest, compared with conventional global and partitioned scheduling algorithms for multiprocessors, due to better utilization results. In semi-partitioned scheduling most tasks are assigned to fixed processors while a low number of tasks are split up and allocated to different processors. Various techniques have recently been proposed to assign tasks in a semi-partitioned environment. However, an appropriate resource sharing mechanism for handling the resource requests between tasks in semi-partitioned scheduling has not yet been investigated. In this paper we propose two methods for handling resource sharing under semi-partitioned scheduling in multiprocessor platforms. The main challenge is to handle the resource requests of tasks that are split over multiple processors.
{"title":"Towards resource sharing under multiprocessor semi-partitioned scheduling","authors":"Sara Afshar, Farhang Nemati, Thomas Nolte","doi":"10.1109/SIES.2012.6356605","DOIUrl":"https://doi.org/10.1109/SIES.2012.6356605","url":null,"abstract":"Semi-partitioned scheduling has been the subject of recent interest, compared with conventional global and partitioned scheduling algorithms for multiprocessors, due to better utilization results. In semi-partitioned scheduling most tasks are assigned to fixed processors while a low number of tasks are split up and allocated to different processors. Various techniques have recently been proposed to assign tasks in a semi-partitioned environment. However, an appropriate resource sharing mechanism for handling the resource requests between tasks in semi-partitioned scheduling has not yet been investigated. In this paper we propose two methods for handling resource sharing under semi-partitioned scheduling in multiprocessor platforms. The main challenge is to handle the resource requests of tasks that are split over multiple processors.","PeriodicalId":219258,"journal":{"name":"7th IEEE International Symposium on Industrial Embedded Systems (SIES'12)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121321697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-20DOI: 10.1109/SIES.2012.6356596
Carsten Tradowsky, F. Thoma, M. Hübner, J. Becker
In today's mobile computers, such as tablets and smart phones, power, performance and chip area are the major constraints to the development of cost efficient high tech products. One solution is the usage of application-specific instruction-set processors (ASIP), which are optimized for the execution of special tasks and thus enable a more efficient implementation. As an extension to this approach the LISPARC processor is developed. For more flexibility, the LISPARC model enables dynamic reconfiguration at run-time in order to adapt to different ASIPs. The processor model of LISPARC is described using an architecture description language called Language for Instruction-Set Architectures (LISA).
{"title":"LISPARC: Using an architecture description language approach for modelling an adaptive processor microarchitecture","authors":"Carsten Tradowsky, F. Thoma, M. Hübner, J. Becker","doi":"10.1109/SIES.2012.6356596","DOIUrl":"https://doi.org/10.1109/SIES.2012.6356596","url":null,"abstract":"In today's mobile computers, such as tablets and smart phones, power, performance and chip area are the major constraints to the development of cost efficient high tech products. One solution is the usage of application-specific instruction-set processors (ASIP), which are optimized for the execution of special tasks and thus enable a more efficient implementation. As an extension to this approach the LISPARC processor is developed. For more flexibility, the LISPARC model enables dynamic reconfiguration at run-time in order to adapt to different ASIPs. The processor model of LISPARC is described using an architecture description language called Language for Instruction-Set Architectures (LISA).","PeriodicalId":219258,"journal":{"name":"7th IEEE International Symposium on Industrial Embedded Systems (SIES'12)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116474471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-20DOI: 10.1109/SIES.2012.6356593
A. Ferrari, Marco Carloni, Alessandro Mignogna, F. Menichelli, D. Ginsberg, E. Scholte, D. Nguyen
In this paper we present the use of a SystemC-based design environment called DESYRE to the simulation of a modern elevator system designed by Otis Elevator Company for large scale buildings. We describe the construction of the virtual prototype of a scalable elevator system based on the CAN communication protocol. We show the tuning and validation of the simulated model against a test system composed of 24 physical nodes, linked to bus and logic analyzers. We finally introduce the work in progress on design space exploration in order to predict the scalability performances of the shared communication resources.
{"title":"Scalable virtual prototyping of distributed embedded control in a modern elevator system","authors":"A. Ferrari, Marco Carloni, Alessandro Mignogna, F. Menichelli, D. Ginsberg, E. Scholte, D. Nguyen","doi":"10.1109/SIES.2012.6356593","DOIUrl":"https://doi.org/10.1109/SIES.2012.6356593","url":null,"abstract":"In this paper we present the use of a SystemC-based design environment called DESYRE to the simulation of a modern elevator system designed by Otis Elevator Company for large scale buildings. We describe the construction of the virtual prototype of a scalable elevator system based on the CAN communication protocol. We show the tuning and validation of the simulated model against a test system composed of 24 physical nodes, linked to bus and logic analyzers. We finally introduce the work in progress on design space exploration in order to predict the scalability performances of the shared communication resources.","PeriodicalId":219258,"journal":{"name":"7th IEEE International Symposium on Industrial Embedded Systems (SIES'12)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133228719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-20DOI: 10.1109/SIES.2012.6356566
M. Neukirchner, Mircea Negrean, R. Ernst, Torsten T. Bone
Driven by the increasing demand for high speed communication of the in-vehicle automotive systems, car manufacturers and suppliers have developed the FlexRay communication protocol. Being dedicated to safety and time-critical applications, the availability of appropriate timing analysis methods for the prediction of the FlexRay timing behaviour is essential. Consequently, several analysis solutions have been proposed. Due to the limitation in the number of frame identifiers in the FlexRay dynamic segment, the slot-multiplexing (or cycle-multiplexing) mechanism is gaining importance for realistic systems. This mechanism allows to share frame identifiers between messages. Moreover, cycle multiplexing in the dynamic segment is often used for signals with deadlines beyond the signal period. Despite its practical relevance, none of the existing response-time analysis approaches is able to consider slot-multiplexing in the dynamic segment for realistic configurations. In this paper we overcome limitations of previous work and present a more general approach for the response-time analysis of the FlexRay dynamic segment, which accurately takes slot-multiplexing into account. We illustrate the applicability of the proposed approach with an industrial case-study and synthetic testcases.
{"title":"Response-time analysis of the flexray dynamic segment under consideration of slot-multiplexing","authors":"M. Neukirchner, Mircea Negrean, R. Ernst, Torsten T. Bone","doi":"10.1109/SIES.2012.6356566","DOIUrl":"https://doi.org/10.1109/SIES.2012.6356566","url":null,"abstract":"Driven by the increasing demand for high speed communication of the in-vehicle automotive systems, car manufacturers and suppliers have developed the FlexRay communication protocol. Being dedicated to safety and time-critical applications, the availability of appropriate timing analysis methods for the prediction of the FlexRay timing behaviour is essential. Consequently, several analysis solutions have been proposed. Due to the limitation in the number of frame identifiers in the FlexRay dynamic segment, the slot-multiplexing (or cycle-multiplexing) mechanism is gaining importance for realistic systems. This mechanism allows to share frame identifiers between messages. Moreover, cycle multiplexing in the dynamic segment is often used for signals with deadlines beyond the signal period. Despite its practical relevance, none of the existing response-time analysis approaches is able to consider slot-multiplexing in the dynamic segment for realistic configurations. In this paper we overcome limitations of previous work and present a more general approach for the response-time analysis of the FlexRay dynamic segment, which accurately takes slot-multiplexing into account. We illustrate the applicability of the proposed approach with an industrial case-study and synthetic testcases.","PeriodicalId":219258,"journal":{"name":"7th IEEE International Symposium on Industrial Embedded Systems (SIES'12)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129415853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-20DOI: 10.1109/SIES.2012.6356595
Peter Ulbrich, Florian Franzmann, F. Scheler, Wolfgang Schröder-Preikschat
Real-time systems usually incorporate a wide variety of challenges: A control engineer, for example, aims for the highest possible control quality achievable. Here, one key element is to minimise the uncertainty of the measurements. This, to put it simple, is the noise of sensor data, which has a negative effect on control. Although measurement uncertainty is well treated in control theory, it is usually ignored in common real-time architectures where temporal properties are the prevalent criteria. Consequently, the communication between control engineers and real-time specialists is rather one way, revolving around deadlines and sampling periods. However, on closer examination, many real-time properties are derived from the measurement uncertainty aspired by the control engineer. Conversely, temporal variations, virtually inevitable in practice, can be represented as measurement uncertainty as well. Tackling the measurement uncertainty should therefore be an interdisciplinary task: The control system respects the actual run-time conditions instead of estimating them. Likewise, the real-time system considers measurement uncertainty rather than blindly sticking to deadlines. In this paper we present an uncertainty-centric approach to leverage measurement uncertainty in real-time architectures, not only at design time but also at run-time. Using measurement uncertainty as an explicit interface minimises the gap between real-time specialists and control engineers and facilitates a modular and flexible system design. Our preliminary results are promising and show the ease of use and the applicability to existing systems.
{"title":"Design by uncertainty: Towards the use of measurement uncertainty in real-time systems","authors":"Peter Ulbrich, Florian Franzmann, F. Scheler, Wolfgang Schröder-Preikschat","doi":"10.1109/SIES.2012.6356595","DOIUrl":"https://doi.org/10.1109/SIES.2012.6356595","url":null,"abstract":"Real-time systems usually incorporate a wide variety of challenges: A control engineer, for example, aims for the highest possible control quality achievable. Here, one key element is to minimise the uncertainty of the measurements. This, to put it simple, is the noise of sensor data, which has a negative effect on control. Although measurement uncertainty is well treated in control theory, it is usually ignored in common real-time architectures where temporal properties are the prevalent criteria. Consequently, the communication between control engineers and real-time specialists is rather one way, revolving around deadlines and sampling periods. However, on closer examination, many real-time properties are derived from the measurement uncertainty aspired by the control engineer. Conversely, temporal variations, virtually inevitable in practice, can be represented as measurement uncertainty as well. Tackling the measurement uncertainty should therefore be an interdisciplinary task: The control system respects the actual run-time conditions instead of estimating them. Likewise, the real-time system considers measurement uncertainty rather than blindly sticking to deadlines. In this paper we present an uncertainty-centric approach to leverage measurement uncertainty in real-time architectures, not only at design time but also at run-time. Using measurement uncertainty as an explicit interface minimises the gap between real-time specialists and control engineers and facilitates a modular and flexible system design. Our preliminary results are promising and show the ease of use and the applicability to existing systems.","PeriodicalId":219258,"journal":{"name":"7th IEEE International Symposium on Industrial Embedded Systems (SIES'12)","volume":"15 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130765019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-20DOI: 10.1109/SIES.2012.6356608
K. Wang, Z. Salcic, J. Yeh, J. Akagi, D. Wlodkowic
This paper presents a high level systematic design approach for a distinctive type of application, automated Bio Cybernetic Systems (BCS), which enable experiments to be performed autonomously on live organisms in a Lab-on-Chip platform. The system integrates micro-electro-mechanical, microfluidics and embedded computing technologies into a fully Automated Biochemical Laboratory (ABL) with real-time sensing and actuating capabilities and control of multiple parallel experiments on large number of live organisms to achieve high throughput screening process. The system comprises of multiple concurrent control subsystems, imaging subsystem, higher-level data acquisition and storage system. A system level design language SystemJ is used to model the ABL as a Globally Asynchronous, Locally Synchronous (GALS) system in software and a hardware prototype is successfully built based on the software model.
{"title":"Automated Bio Cybernetic System: A Lab-on-Chip case study","authors":"K. Wang, Z. Salcic, J. Yeh, J. Akagi, D. Wlodkowic","doi":"10.1109/SIES.2012.6356608","DOIUrl":"https://doi.org/10.1109/SIES.2012.6356608","url":null,"abstract":"This paper presents a high level systematic design approach for a distinctive type of application, automated Bio Cybernetic Systems (BCS), which enable experiments to be performed autonomously on live organisms in a Lab-on-Chip platform. The system integrates micro-electro-mechanical, microfluidics and embedded computing technologies into a fully Automated Biochemical Laboratory (ABL) with real-time sensing and actuating capabilities and control of multiple parallel experiments on large number of live organisms to achieve high throughput screening process. The system comprises of multiple concurrent control subsystems, imaging subsystem, higher-level data acquisition and storage system. A system level design language SystemJ is used to model the ABL as a Globally Asynchronous, Locally Synchronous (GALS) system in software and a hardware prototype is successfully built based on the software model.","PeriodicalId":219258,"journal":{"name":"7th IEEE International Symposium on Industrial Embedded Systems (SIES'12)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126695499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-20DOI: 10.1109/SIES.2012.6356572
Z. Iqbal, L. Almeida, R. Marau, M. Behnam, Thomas Nolte
Hierarchical scheduling is instrumental to efficiently deploy component-based designs and achieve composability. It allows partitioning resources into multiple levels, hiding the complexity within each partition behind its respective interface. In this paper we focus on the network resource, particularly on Ethernet using ordinary COTS switches, and we show how hierarchical scheduling can be efficiently deployed using a master/slave approach that enforces the temporal properties of the partitions. We use the FTT-SE protocol for being open source and a bandwidth efficient master/slave alternative currently available for real-time communication over Ethernet. We present a response-time analysis for the traffic submitted within each partition and we validate it using experimental results obtained from a prototype implementation. In particular, the results highlight the strong partitioning capabilities of our approach, with full temporal isolation across partitions in different branches of the hierarchy.
{"title":"Implementing hierarchical scheduling on COTS Ethernet switches using a master/slave approach","authors":"Z. Iqbal, L. Almeida, R. Marau, M. Behnam, Thomas Nolte","doi":"10.1109/SIES.2012.6356572","DOIUrl":"https://doi.org/10.1109/SIES.2012.6356572","url":null,"abstract":"Hierarchical scheduling is instrumental to efficiently deploy component-based designs and achieve composability. It allows partitioning resources into multiple levels, hiding the complexity within each partition behind its respective interface. In this paper we focus on the network resource, particularly on Ethernet using ordinary COTS switches, and we show how hierarchical scheduling can be efficiently deployed using a master/slave approach that enforces the temporal properties of the partitions. We use the FTT-SE protocol for being open source and a bandwidth efficient master/slave alternative currently available for real-time communication over Ethernet. We present a response-time analysis for the traffic submitted within each partition and we validate it using experimental results obtained from a prototype implementation. In particular, the results highlight the strong partitioning capabilities of our approach, with full temporal isolation across partitions in different branches of the hierarchy.","PeriodicalId":219258,"journal":{"name":"7th IEEE International Symposium on Industrial Embedded Systems (SIES'12)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123123305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-20DOI: 10.1109/SIES.2012.6356594
C. Prehofer, M. Zeller
In this work, we consider reliable runtime adaptation in networked, embedded systems with tight real-time constraints by adapting the placement of software components on a multitude of hardware components. We show the need for a hierarchical transaction concept in this context. In particular, we consider multiple adaptation steps under hard system constraints and also introduce a model with undesired configurations, which cannot be maintained for an extended time period. Furthermore, we discuss implementation issues for such an adaptation process, including the actual task migration implementation, for real-time, embedded systems.
{"title":"Towards runtime adaptation in real-time, networked embedded systems","authors":"C. Prehofer, M. Zeller","doi":"10.1109/SIES.2012.6356594","DOIUrl":"https://doi.org/10.1109/SIES.2012.6356594","url":null,"abstract":"In this work, we consider reliable runtime adaptation in networked, embedded systems with tight real-time constraints by adapting the placement of software components on a multitude of hardware components. We show the need for a hierarchical transaction concept in this context. In particular, we consider multiple adaptation steps under hard system constraints and also introduce a model with undesired configurations, which cannot be maintained for an extended time period. Furthermore, we discuss implementation issues for such an adaptation process, including the actual task migration implementation, for real-time, embedded systems.","PeriodicalId":219258,"journal":{"name":"7th IEEE International Symposium on Industrial Embedded Systems (SIES'12)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133319980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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