Pub Date : 2012-06-20DOI: 10.1109/SIES.2012.6356602
R. D. Medeiros, Miguel Góis, D. Rossi, Vanderlei Bonato
With the significant increase in complexity of system-on-chip arise the necessity of embedded systems designers to work with more flexible and detailed modelling rules. The MARTE (Modelling and Analysis of Real Time and Embedded Systems) modelling language developed by OMG (Object Management Group) to design embedded systems, supporting realtime constraints, allows specification and integration of models designed on System (Hw/Sw), Hardware(HW) and Software(Sw) levels. This language enables the MDA methodology (Model-Driven Architecture) to be employed for the development of embedded systems in a standard way independently of implementation technology. In this context, this paper presents a work in progress converter, called I2S, in which platform-independent models (PIM) are automatically converted to specific models (PSM) for the Altera and Xilinx platforms, being the latter one still under development. It also describes how the models are specified and interpreted in MARTE and how the PIM to PSM transformations occur. The PSM models generated by the converter are synthesizable to FPGA (Field-Programmable Gate Array) devices, allowing its application to real-world problems.
{"title":"Designing embedded systems with MARTE: A PIM to PSM converter","authors":"R. D. Medeiros, Miguel Góis, D. Rossi, Vanderlei Bonato","doi":"10.1109/SIES.2012.6356602","DOIUrl":"https://doi.org/10.1109/SIES.2012.6356602","url":null,"abstract":"With the significant increase in complexity of system-on-chip arise the necessity of embedded systems designers to work with more flexible and detailed modelling rules. The MARTE (Modelling and Analysis of Real Time and Embedded Systems) modelling language developed by OMG (Object Management Group) to design embedded systems, supporting realtime constraints, allows specification and integration of models designed on System (Hw/Sw), Hardware(HW) and Software(Sw) levels. This language enables the MDA methodology (Model-Driven Architecture) to be employed for the development of embedded systems in a standard way independently of implementation technology. In this context, this paper presents a work in progress converter, called I2S, in which platform-independent models (PIM) are automatically converted to specific models (PSM) for the Altera and Xilinx platforms, being the latter one still under development. It also describes how the models are specified and interpreted in MARTE and how the PIM to PSM transformations occur. The PSM models generated by the converter are synthesizable to FPGA (Field-Programmable Gate Array) devices, allowing its application to real-world problems.","PeriodicalId":219258,"journal":{"name":"7th IEEE International Symposium on Industrial Embedded Systems (SIES'12)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133575796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-20DOI: 10.1109/SIES.2012.6356573
H. Nguyen, G. Juanole
The goal of this paper is to consider a co-design approach between the controller of a process control application and the frame scheduling of a Local Area Network (LAN). More precisely we present a bi-directional relation between the Quality of Control (QoC) provided by the controller and the Quality of Service (QoS) provided by the LAN (relation noted QoS⇋QoC). We present, first, the implementation of the relation QoS→QoC on the basis of a compensation method for time delays called dominant pole method, and second, the implementation of the relation QoC→QoS on the basis of the hybrid priorities for the frame scheduling. The final objective is the implementation of the bidirectional relation QoS⇋QoC which is the combination of the both relations QoS→QoC and QoC→QoS in order to have a more efficient NCSs design.
{"title":"Design of Networked Control Systems (NCSs) on the basis of interplays between Quality of Control and Quality of Service","authors":"H. Nguyen, G. Juanole","doi":"10.1109/SIES.2012.6356573","DOIUrl":"https://doi.org/10.1109/SIES.2012.6356573","url":null,"abstract":"The goal of this paper is to consider a co-design approach between the controller of a process control application and the frame scheduling of a Local Area Network (LAN). More precisely we present a bi-directional relation between the Quality of Control (QoC) provided by the controller and the Quality of Service (QoS) provided by the LAN (relation noted QoS⇋QoC). We present, first, the implementation of the relation QoS→QoC on the basis of a compensation method for time delays called dominant pole method, and second, the implementation of the relation QoC→QoS on the basis of the hybrid priorities for the frame scheduling. The final objective is the implementation of the bidirectional relation QoS⇋QoC which is the combination of the both relations QoS→QoC and QoC→QoS in order to have a more efficient NCSs design.","PeriodicalId":219258,"journal":{"name":"7th IEEE International Symposium on Industrial Embedded Systems (SIES'12)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134330062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-20DOI: 10.1109/SIES.2012.6356606
R. Inam, Mikael Sjödin, Reinder J. Brfi
Multi-mode embedded real-time systems exhibit a specific behavior for each mode and upon a mode-change request, the task-set and timing interfaces of the system need to be changed. Hierarchical Scheduling Framework (HSF) is a known technique to partition the CPU time into a number of hierarchically divided subsystems each consists of its own task set. We propose to implement a multi-mode system using a two-level HSF and provide a skeleton (framework) for an adaptive HSFs supporting multi-modes. Upon a mode-change request, the timing interface of each subsystem is changed, thus making the hierarchical scheduling adaptive in nature. We address the main goals for the implementation and describe the initial design details of the Multi-Mode Adaptive Hierarchical Scheduling Framework (MMAHSF) with the emphasis of doing minimal changes to the underlying kernel.
{"title":"Implementing hierarchical scheduling to support multi-mode system","authors":"R. Inam, Mikael Sjödin, Reinder J. Brfi","doi":"10.1109/SIES.2012.6356606","DOIUrl":"https://doi.org/10.1109/SIES.2012.6356606","url":null,"abstract":"Multi-mode embedded real-time systems exhibit a specific behavior for each mode and upon a mode-change request, the task-set and timing interfaces of the system need to be changed. Hierarchical Scheduling Framework (HSF) is a known technique to partition the CPU time into a number of hierarchically divided subsystems each consists of its own task set. We propose to implement a multi-mode system using a two-level HSF and provide a skeleton (framework) for an adaptive HSFs supporting multi-modes. Upon a mode-change request, the timing interface of each subsystem is changed, thus making the hierarchical scheduling adaptive in nature. We address the main goals for the implementation and describe the initial design details of the Multi-Mode Adaptive Hierarchical Scheduling Framework (MMAHSF) with the emphasis of doing minimal changes to the underlying kernel.","PeriodicalId":219258,"journal":{"name":"7th IEEE International Symposium on Industrial Embedded Systems (SIES'12)","volume":"819 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116419570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-20DOI: 10.1109/SIES.2012.6356565
Xiaoting Li, Jean-Luc Scharbarg, C. Fraboul
A heterogeneous network, where a switched Ethernet backbone interconnects several existing CAN buses via bridges, is a promising candidate to build a large scale network. For real-time applications, deterministic communication is a key issue. A worst-case delay analysis on such a network has to deal with heterogeneity properties, such as different bandwidths, scheduling policies and bridging strategies. In this paper, two approaches are proposed. The first one is based on a hierarchical component-based approach. The second one is an adapted Trajectory approach which integrates heterogeneity properties. Moreover, pessimism introduced by the adapted Trajectory approach is analyzed and an optimization of this approach is proposed.
{"title":"Worst-case delay analysis on a real-time heterogeneous network","authors":"Xiaoting Li, Jean-Luc Scharbarg, C. Fraboul","doi":"10.1109/SIES.2012.6356565","DOIUrl":"https://doi.org/10.1109/SIES.2012.6356565","url":null,"abstract":"A heterogeneous network, where a switched Ethernet backbone interconnects several existing CAN buses via bridges, is a promising candidate to build a large scale network. For real-time applications, deterministic communication is a key issue. A worst-case delay analysis on such a network has to deal with heterogeneity properties, such as different bandwidths, scheduling policies and bridging strategies. In this paper, two approaches are proposed. The first one is based on a hierarchical component-based approach. The second one is an adapted Trajectory approach which integrates heterogeneity properties. Moreover, pessimism introduced by the adapted Trajectory approach is analyzed and an optimization of this approach is proposed.","PeriodicalId":219258,"journal":{"name":"7th IEEE International Symposium on Industrial Embedded Systems (SIES'12)","volume":"356 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121695885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-20DOI: 10.1109/SIES.2012.6356584
Timo Schönwald, A. Viehl, O. Bringmann, W. Rosenstiel
In this paper, we present a novel approach for automated latency-optimized mapping of processes onto cores of NoC-based MPSoCs. During the mapping determination, the routing algorithm for packet-based communication is taken into account. The basic idea of the presented approach is the reduction of communication conflicts on the communication network links for reducing the overall communication latency and hence for increasing the total system performance. The presented approach is based on the idea of force-directed scheduling (FDS) from high-level synthesis. It maps the problem of conflict avoidance to forces for deriving an optimized process mapping. We present results obtained from two advanced driver assistance systems (ADAS), a traffic sign recognition and a depth map computation for a stereo camera system used for object recognition. As hardware platform we used a Tilera TILEPro64 processor system.
{"title":"Optimized software mapping for advanced driver assistance systems","authors":"Timo Schönwald, A. Viehl, O. Bringmann, W. Rosenstiel","doi":"10.1109/SIES.2012.6356584","DOIUrl":"https://doi.org/10.1109/SIES.2012.6356584","url":null,"abstract":"In this paper, we present a novel approach for automated latency-optimized mapping of processes onto cores of NoC-based MPSoCs. During the mapping determination, the routing algorithm for packet-based communication is taken into account. The basic idea of the presented approach is the reduction of communication conflicts on the communication network links for reducing the overall communication latency and hence for increasing the total system performance. The presented approach is based on the idea of force-directed scheduling (FDS) from high-level synthesis. It maps the problem of conflict avoidance to forces for deriving an optimized process mapping. We present results obtained from two advanced driver assistance systems (ADAS), a traffic sign recognition and a depth map computation for a stereo camera system used for object recognition. As hardware platform we used a Tilera TILEPro64 processor system.","PeriodicalId":219258,"journal":{"name":"7th IEEE International Symposium on Industrial Embedded Systems (SIES'12)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127811446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-20DOI: 10.1109/SIES.2012.6356575
Francesco Fraternali, Mahsan Rofouei, N. Alshurafa, Hassan Ghasemzadeh, L. Benini, M. Sarrafzadeh
Patient monitoring systems are becoming increasingly important in accurately diagnosing and treating growing worldwide chronic conditions especially the obesity epidemic. The ubiquitous nature of wearable sensors, such as the readily available embedded accelerometers in smart phones, provides physicians with an opportunity to remotely monitor their patient's daily activity. There have been several developments in the area of activity recognition using wearable sensors. However, due to power constraints, resource efficient algorithms are necessary in order to perform accurate realtime activity recognition while consuming minimal energy. In this paper, we present a two-tier architecture for optimizing power consumption in such systems. While the first tier relies on a hierarchical classification approach, the second one manages the activation and deactivation of the classification system. We demonstrate this using a series of binary Support Vector Machine classifiers. The proposed approach, however, is classifier independent. Experimenting with subjects performing different daily activities such as walking, going upstairs and down-stairs, standing and sitting, our approach achieves a power savings of 87%, while maintaining 92% classification accuracy.
{"title":"Opportunistic hierarchical classification for power optimization in wearable movement monitoring systems","authors":"Francesco Fraternali, Mahsan Rofouei, N. Alshurafa, Hassan Ghasemzadeh, L. Benini, M. Sarrafzadeh","doi":"10.1109/SIES.2012.6356575","DOIUrl":"https://doi.org/10.1109/SIES.2012.6356575","url":null,"abstract":"Patient monitoring systems are becoming increasingly important in accurately diagnosing and treating growing worldwide chronic conditions especially the obesity epidemic. The ubiquitous nature of wearable sensors, such as the readily available embedded accelerometers in smart phones, provides physicians with an opportunity to remotely monitor their patient's daily activity. There have been several developments in the area of activity recognition using wearable sensors. However, due to power constraints, resource efficient algorithms are necessary in order to perform accurate realtime activity recognition while consuming minimal energy. In this paper, we present a two-tier architecture for optimizing power consumption in such systems. While the first tier relies on a hierarchical classification approach, the second one manages the activation and deactivation of the classification system. We demonstrate this using a series of binary Support Vector Machine classifiers. The proposed approach, however, is classifier independent. Experimenting with subjects performing different daily activities such as walking, going upstairs and down-stairs, standing and sitting, our approach achieves a power savings of 87%, while maintaining 92% classification accuracy.","PeriodicalId":219258,"journal":{"name":"7th IEEE International Symposium on Industrial Embedded Systems (SIES'12)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129208182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-20DOI: 10.1109/SIES.2012.6356591
M. Cheminod, L. Durante, A. Valenzano
Awareness that networked embedded systems are vulnerable to cyber-threats has been constantly raising since some years ago. In the industrial arena recent severe attacks, such as the popular case of the Stuxnet worm, have completely debunked the myth of security of embedded devices based on their isolation. Indeed, the ever increasing dependence of many industrial systems on digital communication networks is causing the cyber-security requirements to become a priority in their planning, design, deployment and management. This paper deals with our experience in checking the conformance of a distributed industrial automation system, which includes several types of embedded devices, with respect to a set of security policies defined at the global system level. In particular, the focus of the paper is on the use of modeling techniques and semi-automated s/w tools to verify the configuration of devices and services with attention to the correct use of their security capabilities to support the desired set of policies.
{"title":"System configuration check against security policies in industrial networks","authors":"M. Cheminod, L. Durante, A. Valenzano","doi":"10.1109/SIES.2012.6356591","DOIUrl":"https://doi.org/10.1109/SIES.2012.6356591","url":null,"abstract":"Awareness that networked embedded systems are vulnerable to cyber-threats has been constantly raising since some years ago. In the industrial arena recent severe attacks, such as the popular case of the Stuxnet worm, have completely debunked the myth of security of embedded devices based on their isolation. Indeed, the ever increasing dependence of many industrial systems on digital communication networks is causing the cyber-security requirements to become a priority in their planning, design, deployment and management. This paper deals with our experience in checking the conformance of a distributed industrial automation system, which includes several types of embedded devices, with respect to a set of security policies defined at the global system level. In particular, the focus of the paper is on the use of modeling techniques and semi-automated s/w tools to verify the configuration of devices and services with attention to the correct use of their security capabilities to support the desired set of policies.","PeriodicalId":219258,"journal":{"name":"7th IEEE International Symposium on Industrial Embedded Systems (SIES'12)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123497260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-20DOI: 10.1109/SIES.2012.6356586
J. Zimmermann, Stefan Hauck-Stattelmann, A. Viehl, O. Bringmann, W. Rosenstiel
In this paper, we present an approach to generate a virtual execution platform in SystemC to advance the development of software-intensive real-time embedded systems including early validation and verification. These virtual execution platforms allow the execution of embedded software with strict consideration of the underlying hardware platform configuration in order to reduce subsequent development costs and to allow a short time-to-market by tailoring and exploring distributed embedded hardware and software architectures. Starting from abstract UML-based descriptions of the software and hardware architecture as well as integrated abstractions of legacy code, model transformation techniques are used during the model-driven generation process. The combination of source code level timing and power annotations obtained from binary legacy code analysis with a layered approach for TLM-based simulation of non-functional properties in a common virtual prototyping methodology allows a fast and accurate simulation of the embedded system model. We further show the synchronization and co-simulation of the embedded hardware/software with vehicle dynamics including human-in-the-loop. To substantiate our allegation we present experimental results expressing the high performance and accuracy of the elaborated virtual prototyping framework as well as its applicability within different application areas and use cases.
{"title":"Model-driven virtual prototyping for real-time simulation of distributed embedded systems","authors":"J. Zimmermann, Stefan Hauck-Stattelmann, A. Viehl, O. Bringmann, W. Rosenstiel","doi":"10.1109/SIES.2012.6356586","DOIUrl":"https://doi.org/10.1109/SIES.2012.6356586","url":null,"abstract":"In this paper, we present an approach to generate a virtual execution platform in SystemC to advance the development of software-intensive real-time embedded systems including early validation and verification. These virtual execution platforms allow the execution of embedded software with strict consideration of the underlying hardware platform configuration in order to reduce subsequent development costs and to allow a short time-to-market by tailoring and exploring distributed embedded hardware and software architectures. Starting from abstract UML-based descriptions of the software and hardware architecture as well as integrated abstractions of legacy code, model transformation techniques are used during the model-driven generation process. The combination of source code level timing and power annotations obtained from binary legacy code analysis with a layered approach for TLM-based simulation of non-functional properties in a common virtual prototyping methodology allows a fast and accurate simulation of the embedded system model. We further show the synchronization and co-simulation of the embedded hardware/software with vehicle dynamics including human-in-the-loop. To substantiate our allegation we present experimental results expressing the high performance and accuracy of the elaborated virtual prototyping framework as well as its applicability within different application areas and use cases.","PeriodicalId":219258,"journal":{"name":"7th IEEE International Symposium on Industrial Embedded Systems (SIES'12)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116749708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-20DOI: 10.1109/SIES.2012.6356604
J. Jiang, Kuen-Cheng Chiang, J. Shann
A coarse-grain reconfigurable architecture is an important technology for exploiting the parallelism of a program without compromise of the flexibility and has been adopted for high-performance embedded systems. However, the utilization of hardware resources may be limited by a large number of conditional executed operations. This paper represents a predicate-aware modulo scheduling which may map disjoint operations into the same processing element to reduce the requirements of hardware resources. Moreover, a weighted mapping decision algorithm has also been proposed to improve the execution performance for reconfigurable architecture. Our experimental results indicate that the initiation interval of a loop of the selected benchmarks may be reduced by 12% to 25.2% compared with a related work.
{"title":"A predicate-aware modulo scheduling for improving resource efficiency of coarse grained reconfigurable architectures","authors":"J. Jiang, Kuen-Cheng Chiang, J. Shann","doi":"10.1109/SIES.2012.6356604","DOIUrl":"https://doi.org/10.1109/SIES.2012.6356604","url":null,"abstract":"A coarse-grain reconfigurable architecture is an important technology for exploiting the parallelism of a program without compromise of the flexibility and has been adopted for high-performance embedded systems. However, the utilization of hardware resources may be limited by a large number of conditional executed operations. This paper represents a predicate-aware modulo scheduling which may map disjoint operations into the same processing element to reduce the requirements of hardware resources. Moreover, a weighted mapping decision algorithm has also been proposed to improve the execution performance for reconfigurable architecture. Our experimental results indicate that the initiation interval of a loop of the selected benchmarks may be reduced by 12% to 25.2% compared with a related work.","PeriodicalId":219258,"journal":{"name":"7th IEEE International Symposium on Industrial Embedded Systems (SIES'12)","volume":"215 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126016817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-20DOI: 10.1109/SIES.2012.6356571
Emanuel Heidinger, Fabien Geyer, S. Schneele, M. Paulitsch
Audio-Video-Bridging (AVB) is a promising new commercially available Ethernet-based standard providing mechanism for audio and video transmission over Ethernet supporting demanding audio and video transmission delay requirements. This paper addresses the applicability of using AVB in a fully-switched Ethernet network that covers safety-related functions in the aeronautics. Avionic systems leveraging such digital networks have stringent requirements in terms of audio quality, latency, and jitter; e.g., latency can be at most a few milliseconds. The result of this work is a performance study of audio transmission approaches in aeronautics where we address AVB without synchronization and AVB synchronization with 802.1AS. We pay special attention to the failure mode of losing synchronization during operation. Two real-world scenarios are addressed in the experimental results - a demonstration of a switched Ethernet aircraft cabin and a demonstration for a highly safety-related audio system. For these two scenarios hard performance bounds are required in terms of synchronous playback that cannot easily be fulfilled, especially when time synchronization is lost.
{"title":"A performance study of Audio Video Bridging in aeronautic Ethernet networks","authors":"Emanuel Heidinger, Fabien Geyer, S. Schneele, M. Paulitsch","doi":"10.1109/SIES.2012.6356571","DOIUrl":"https://doi.org/10.1109/SIES.2012.6356571","url":null,"abstract":"Audio-Video-Bridging (AVB) is a promising new commercially available Ethernet-based standard providing mechanism for audio and video transmission over Ethernet supporting demanding audio and video transmission delay requirements. This paper addresses the applicability of using AVB in a fully-switched Ethernet network that covers safety-related functions in the aeronautics. Avionic systems leveraging such digital networks have stringent requirements in terms of audio quality, latency, and jitter; e.g., latency can be at most a few milliseconds. The result of this work is a performance study of audio transmission approaches in aeronautics where we address AVB without synchronization and AVB synchronization with 802.1AS. We pay special attention to the failure mode of losing synchronization during operation. Two real-world scenarios are addressed in the experimental results - a demonstration of a switched Ethernet aircraft cabin and a demonstration for a highly safety-related audio system. For these two scenarios hard performance bounds are required in terms of synchronous playback that cannot easily be fulfilled, especially when time synchronization is lost.","PeriodicalId":219258,"journal":{"name":"7th IEEE International Symposium on Industrial Embedded Systems (SIES'12)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127932190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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