Pub Date : 2017-09-13DOI: 10.1109/TASE.2017.8285634
Zeineb Zhioua, Y. Roudier, R. Ameur-Boulifa
Secure software can be obtained out of two distinct processes: security by design, and security by certification. The former approach has been quite extensively formalized as it builds upon models, which are verified to ensure security properties are attained and from which software is then derived manually or automatically. In contrast, the latter approach has always been quite informal in both specifying security best practices and verifying that the code produced conforms to them. In this paper, we focus on the latter approach and describe how security guidelines might be captured by security experts and verified formally by developers. Our technique relies on abstracting actions in a program based on modularity, and on combining model checking together with information flow analysis. Our goal is to formalize the existing body of knowledge in security best practices using formulas in the MCL language and to conduct formal verifications of the conformance of programs with such security guidelines. We also discuss our first results in creating a methodology for the formalization of security guidelines.
{"title":"Formal specification of security guidelines for program certification","authors":"Zeineb Zhioua, Y. Roudier, R. Ameur-Boulifa","doi":"10.1109/TASE.2017.8285634","DOIUrl":"https://doi.org/10.1109/TASE.2017.8285634","url":null,"abstract":"Secure software can be obtained out of two distinct processes: security by design, and security by certification. The former approach has been quite extensively formalized as it builds upon models, which are verified to ensure security properties are attained and from which software is then derived manually or automatically. In contrast, the latter approach has always been quite informal in both specifying security best practices and verifying that the code produced conforms to them. In this paper, we focus on the latter approach and describe how security guidelines might be captured by security experts and verified formally by developers. Our technique relies on abstracting actions in a program based on modularity, and on combining model checking together with information flow analysis. Our goal is to formalize the existing body of knowledge in security best practices using formulas in the MCL language and to conduct formal verifications of the conformance of programs with such security guidelines. We also discuss our first results in creating a methodology for the formalization of security guidelines.","PeriodicalId":221968,"journal":{"name":"2017 International Symposium on Theoretical Aspects of Software Engineering (TASE)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132046921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-13DOI: 10.1109/TASE.2017.8285630
Ning Ge, M. Pantel, Silvano Dal-Zilio
To ease the expression of real-time requirements, Dwyer, and then Konrad, studied a large collection of existing systems in order to identify a set of real-time property patterns covering most of the useful use cases. The goal was to provide a set of reusable patterns that system designers can instantiate to express requirements instead of using complex temporal logic formulas. A limitation of this approach is that the choice of patterns is more oriented towards expressiveness than efficiency; meaning that it does not take into account the computational complexity of checking patterns. For this purpose, we define a set of verification-dedicated, atomic property patterns for qualitative and quantitative real-time requirements. End-user requirements can then be expressed as a composition of these patterns using a predefined meta-model and a mapping library. These properties can be checked efficiently using a set of elementary observers and a model checking approach.
{"title":"Formal verification of user-level real-time property patterns","authors":"Ning Ge, M. Pantel, Silvano Dal-Zilio","doi":"10.1109/TASE.2017.8285630","DOIUrl":"https://doi.org/10.1109/TASE.2017.8285630","url":null,"abstract":"To ease the expression of real-time requirements, Dwyer, and then Konrad, studied a large collection of existing systems in order to identify a set of real-time property patterns covering most of the useful use cases. The goal was to provide a set of reusable patterns that system designers can instantiate to express requirements instead of using complex temporal logic formulas. A limitation of this approach is that the choice of patterns is more oriented towards expressiveness than efficiency; meaning that it does not take into account the computational complexity of checking patterns. For this purpose, we define a set of verification-dedicated, atomic property patterns for qualitative and quantitative real-time requirements. End-user requirements can then be expressed as a composition of these patterns using a predefined meta-model and a mapping library. These properties can be checked efficiently using a set of elementary observers and a model checking approach.","PeriodicalId":221968,"journal":{"name":"2017 International Symposium on Theoretical Aspects of Software Engineering (TASE)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121483694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-13DOI: 10.1109/TASE.2017.8285631
C. Mu, S. Qin
Protecting confidential data in today's computing environments is an important problem. Information flow control can help to avoid information leakage and violations introduced by executing the software applications. In software development cycle, it is important to handle security related issues from the beginning specifications at the level of abstract. Mu [1] investigated the problem of preserving information flow security in the Event-B specification models. A typed Event-B model was presented to enforce information flow security and to prevent direct flows introduced by the system. However, in practice, timing behaviours of programs can also introduce a covert flow. The problem of run-time flow monitoring and controlling must also be addressed. This paper investigates information flow control in the Event-B specification language with timing constructs. We present a timed Event-B system by introducing timers and relevant time constraints into the system events. We suggest a time-sensitive flow security condition for the timed Event-B systems, and present a type system to close the covert channels of timing flows for the system by ensuring the security condition. We then investigate how to refine timed events during the stepwise refinement modelling to satisfy the security condition.
{"title":"Time-sensitive information flow control in timed event-B","authors":"C. Mu, S. Qin","doi":"10.1109/TASE.2017.8285631","DOIUrl":"https://doi.org/10.1109/TASE.2017.8285631","url":null,"abstract":"Protecting confidential data in today's computing environments is an important problem. Information flow control can help to avoid information leakage and violations introduced by executing the software applications. In software development cycle, it is important to handle security related issues from the beginning specifications at the level of abstract. Mu [1] investigated the problem of preserving information flow security in the Event-B specification models. A typed Event-B model was presented to enforce information flow security and to prevent direct flows introduced by the system. However, in practice, timing behaviours of programs can also introduce a covert flow. The problem of run-time flow monitoring and controlling must also be addressed. This paper investigates information flow control in the Event-B specification language with timing constructs. We present a timed Event-B system by introducing timers and relevant time constraints into the system events. We suggest a time-sensitive flow security condition for the timed Event-B systems, and present a type system to close the covert channels of timing flows for the system by ensuring the security condition. We then investigate how to refine timed events during the stepwise refinement modelling to satisfy the security condition.","PeriodicalId":221968,"journal":{"name":"2017 International Symposium on Theoretical Aspects of Software Engineering (TASE)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130773278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-13DOI: 10.1109/TASE.2017.8285636
Ning Ge, Arnaud Dieumegard, E. Jenn, Bruno d'Ausbourg, Y. A. Ameur
This paper presents a formal development process for safety-critical embedded Human-Machine Interface (HMI) systems. This formal approach is centered on the LIDL formal language and the S3 verification toolset. It is aimed at blurring the boundaries between modeling, design, verification and implementation for the development of HMI. From textual requirements to software, the development process integrates the following formal activities: modeling the behavioral aspect of user interfaces (UIs) using LIDL; translating LIDL to Lustre, with which we combine the functional library in Lustre; translating the Lustre design models into the HLL verification models; verifying formal properties expressed in HLL against the HLL model using the S3 toolset, and diagnosing design errors with the help of counterexample scenarios and debug tools. This formal development process is illustrated on a simple use case — part of the display component of an alert management system used in a three-wheeled robot.
{"title":"Formal development process of safety-critical embedded human machine interface systems","authors":"Ning Ge, Arnaud Dieumegard, E. Jenn, Bruno d'Ausbourg, Y. A. Ameur","doi":"10.1109/TASE.2017.8285636","DOIUrl":"https://doi.org/10.1109/TASE.2017.8285636","url":null,"abstract":"This paper presents a formal development process for safety-critical embedded Human-Machine Interface (HMI) systems. This formal approach is centered on the LIDL formal language and the S3 verification toolset. It is aimed at blurring the boundaries between modeling, design, verification and implementation for the development of HMI. From textual requirements to software, the development process integrates the following formal activities: modeling the behavioral aspect of user interfaces (UIs) using LIDL; translating LIDL to Lustre, with which we combine the functional library in Lustre; translating the Lustre design models into the HLL verification models; verifying formal properties expressed in HLL against the HLL model using the S3 toolset, and diagnosing design errors with the help of counterexample scenarios and debug tools. This formal development process is illustrated on a simple use case — part of the display component of an alert management system used in a three-wheeled robot.","PeriodicalId":221968,"journal":{"name":"2017 International Symposium on Theoretical Aspects of Software Engineering (TASE)","volume":"601 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132789237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/TASE.2017.8285629
Pattaravut Maleehuan, Yuki Chiba, Toshiaki Aoki
A relaxed memory model allows reordering of memory accesses, which can violate program correctness in multiprocessors. This paper presents an approach to verifying a list of assembly programs under a relaxed memory model. Assembly programs are considered for abstractions, which capture essential information that affects the correctness. For program verification, SMT solvers are adopted for finding an execution that violates program property, which is defined by assertions. The solver takes constraints that represent the violation of assertion conditions to find a valuation which can construct an execution. An encoding method is presented for constructing the constraints of program behavior, which classifies the essential behaviors in multiprocessors and can be used by the solvers. An automated tool was developed to abstract the list of assembly programs and find an execution that violates the program assertions. Experiment results show the tool can verify assembly programs for SPARC architecture under SC, TSO, and PSO memory models.
{"title":"Assembly program verification for multiprocessors with relaxed memory model using SMT solver","authors":"Pattaravut Maleehuan, Yuki Chiba, Toshiaki Aoki","doi":"10.1109/TASE.2017.8285629","DOIUrl":"https://doi.org/10.1109/TASE.2017.8285629","url":null,"abstract":"A relaxed memory model allows reordering of memory accesses, which can violate program correctness in multiprocessors. This paper presents an approach to verifying a list of assembly programs under a relaxed memory model. Assembly programs are considered for abstractions, which capture essential information that affects the correctness. For program verification, SMT solvers are adopted for finding an execution that violates program property, which is defined by assertions. The solver takes constraints that represent the violation of assertion conditions to find a valuation which can construct an execution. An encoding method is presented for constructing the constraints of program behavior, which classifies the essential behaviors in multiprocessors and can be used by the solvers. An automated tool was developed to abstract the list of assembly programs and find an execution that violates the program assertions. Experiment results show the tool can verify assembly programs for SPARC architecture under SC, TSO, and PSO memory models.","PeriodicalId":221968,"journal":{"name":"2017 International Symposium on Theoretical Aspects of Software Engineering (TASE)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124044511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/TASE.2017.8285627
Yueling Zhang, Jianwen Li, Min Zhang, G. Pu, Fu Song
Backbone is the common part of each solution in a given propositional formula, which is a key to improving the performance of SAT solving and SAT-based applications, such as model checking and program analysis. In this paper, we propose an optimized approach that combines implication-driven (IDF), conflict-driven (CDF), and unique-driven (UDF) heuristics to improve backbone computing. IDF uses the particular binary structure of the form a ↔ b ∧ c to find more backbone literals. CDF comes from the observation that for a clause ¬a ∨ b, if a is a backbone literal, then b is also a backbone literal. Besides CDF, we are also able to detect new non-backbone literals by UDF. A literal l is not a backbone literal, if there is no clause Φ ∊ Φ that is only satisfied by l. We implemented our approach in a tool named DUCIBone with the above optimizations (IDF+CDF+UDF), and conducted experiments on formulas used in previous work and SAT competitions (2015, 2016). Results demonstrate that DUCIBone solved 4% (507 formulas) more formulas than minibones (minibones-RLD, 490 formulas) does under its best configuration. Among 486 formulas solved by all tools (DUCIBone, minibones-RLD, minibonescb100), DUCIBone reduced 7% (35131 seconds) than minibones (37454 seconds). Experiments indicate that the advantage of DUCIBone is more obvious when the formulas are harder.
{"title":"Optimizing backbone filtering","authors":"Yueling Zhang, Jianwen Li, Min Zhang, G. Pu, Fu Song","doi":"10.1109/TASE.2017.8285627","DOIUrl":"https://doi.org/10.1109/TASE.2017.8285627","url":null,"abstract":"Backbone is the common part of each solution in a given propositional formula, which is a key to improving the performance of SAT solving and SAT-based applications, such as model checking and program analysis. In this paper, we propose an optimized approach that combines implication-driven (IDF), conflict-driven (CDF), and unique-driven (UDF) heuristics to improve backbone computing. IDF uses the particular binary structure of the form a ↔ b ∧ c to find more backbone literals. CDF comes from the observation that for a clause ¬a ∨ b, if a is a backbone literal, then b is also a backbone literal. Besides CDF, we are also able to detect new non-backbone literals by UDF. A literal l is not a backbone literal, if there is no clause Φ ∊ Φ that is only satisfied by l. We implemented our approach in a tool named DUCIBone with the above optimizations (IDF+CDF+UDF), and conducted experiments on formulas used in previous work and SAT competitions (2015, 2016). Results demonstrate that DUCIBone solved 4% (507 formulas) more formulas than minibones (minibones-RLD, 490 formulas) does under its best configuration. Among 486 formulas solved by all tools (DUCIBone, minibones-RLD, minibonescb100), DUCIBone reduced 7% (35131 seconds) than minibones (37454 seconds). Experiments indicate that the advantage of DUCIBone is more obvious when the formulas are harder.","PeriodicalId":221968,"journal":{"name":"2017 International Symposium on Theoretical Aspects of Software Engineering (TASE)","volume":"2012 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128189564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/TASE.2017.8285638
Diego Marmsoler
In component-based design, temporal logic is a means to specify the temporal behavior of components. If these components are deployed to a dynamic architecture, they can be activated and deactivated over time. Thus, the traditional semantics of temporal specifications of component-behavior does no longer reflect the actual behavior of the components within such dynamic architectures. To address this problem, we provide an alternative semantics of temporal specifications of component-behavior for dynamic architectures, taking into account component activation and deactivation. We show soundness and relative completeness of our semantics w.r.t. the traditional one. The new semantics can then be used to support in the formal specification of dynamic architectures by separating the specification of component-behavior from other aspects such as component activation and architecture reconfiguration.
{"title":"On the semantics of temporal specifications of component-behavior for dynamic architectures","authors":"Diego Marmsoler","doi":"10.1109/TASE.2017.8285638","DOIUrl":"https://doi.org/10.1109/TASE.2017.8285638","url":null,"abstract":"In component-based design, temporal logic is a means to specify the temporal behavior of components. If these components are deployed to a dynamic architecture, they can be activated and deactivated over time. Thus, the traditional semantics of temporal specifications of component-behavior does no longer reflect the actual behavior of the components within such dynamic architectures. To address this problem, we provide an alternative semantics of temporal specifications of component-behavior for dynamic architectures, taking into account component activation and deactivation. We show soundness and relative completeness of our semantics w.r.t. the traditional one. The new semantics can then be used to support in the formal specification of dynamic architectures by separating the specification of component-behavior from other aspects such as component activation and architecture reconfiguration.","PeriodicalId":221968,"journal":{"name":"2017 International Symposium on Theoretical Aspects of Software Engineering (TASE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129670343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/TASE.2017.8285637
Bingqing Xu, Qin Li
The decision-making module on an autonomous car is usually a periodic program. In every cycle, the program makes a decision such as acceleration, brake, initiating a lane change process or a turn process based on the current traffic information gathered from car sensors. In urban traffic with mixed type of vehicles, the real-time performance requirement is critical for the decision-making program while acquiring global knowledge of the traffic is less practical. In such an environment, communications between vehicles are unreliable and time-consuming, so it is often difficult to know the exact driving decisions of other cars in the next cycle. In order to guarantee safety, a feasible solution requires the reasonable estimation on the driving decisions of other cars in the near future. In this paper, we propose a BMML (Bounded Multi-dimensional Modal Logic) to specify the traffic situations with spatio-temproral properties taking account of the estimated evolvement on them in the near future. The logic contains a primitive spatial logic with navigation operators and estimation operators as modal operators. The satisfaction of a BMML formula depends on a snapshot of the current traffic condition and an estimation structure capturing the believed information on the driving decisions of other cars. Given a snapshot and an estimation structure, the satisfaction of a BMML formula can be determined with simple and deterministic reasoning, so it is feasible for taking a BMML formula as the guard condition of the decision-making program of an autonomous car. The usage of BMML is illustrated with a series of small examples.
{"title":"A bounded multi-dimensional modal logic for autonomous cars based on local traffic and estimation","authors":"Bingqing Xu, Qin Li","doi":"10.1109/TASE.2017.8285637","DOIUrl":"https://doi.org/10.1109/TASE.2017.8285637","url":null,"abstract":"The decision-making module on an autonomous car is usually a periodic program. In every cycle, the program makes a decision such as acceleration, brake, initiating a lane change process or a turn process based on the current traffic information gathered from car sensors. In urban traffic with mixed type of vehicles, the real-time performance requirement is critical for the decision-making program while acquiring global knowledge of the traffic is less practical. In such an environment, communications between vehicles are unreliable and time-consuming, so it is often difficult to know the exact driving decisions of other cars in the next cycle. In order to guarantee safety, a feasible solution requires the reasonable estimation on the driving decisions of other cars in the near future. In this paper, we propose a BMML (Bounded Multi-dimensional Modal Logic) to specify the traffic situations with spatio-temproral properties taking account of the estimated evolvement on them in the near future. The logic contains a primitive spatial logic with navigation operators and estimation operators as modal operators. The satisfaction of a BMML formula depends on a snapshot of the current traffic condition and an estimation structure capturing the believed information on the driving decisions of other cars. Given a snapshot and an estimation structure, the satisfaction of a BMML formula can be determined with simple and deterministic reasoning, so it is feasible for taking a BMML formula as the guard condition of the decision-making program of an autonomous car. The usage of BMML is illustrated with a series of small examples.","PeriodicalId":221968,"journal":{"name":"2017 International Symposium on Theoretical Aspects of Software Engineering (TASE)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125572297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/TASE.2017.8285632
J. Julliand, O. Kouchnarenko, P. Masson, G. Voiron
Model-based testing of event systems can take advantage of considering abstractions rather than explicit models, for controlling their size. A test is then a connected and reachable event sequence. This paper reports on experiments made when adapting for event systems two known under-approximation techniques of predicate tri-modal (may, must+, must-) abstractions. We first instantiate all the abstract may transitions, preferably as reachable instances. Second, we complete this underapproximation with instantiations of Ball chains, i.e. sequences in the shape of must-∗may.must+∗ transitions, as such sequences are guaranteed to have connected instantiations. We present a backward symbolic instantiation algorithm for connecting these two under-approximations. We experimentally address the question of their complementarity. Surprisingly, our results show that Ball chains have not enhanced the coverage already achieved by the first step of may-transitions instantiation. However, it has enhanced the number of test steps by prolonging the already existing tests.
{"title":"Two under-approximation techniques for 3-modal abstraction coverage of event systems: Joint effort?","authors":"J. Julliand, O. Kouchnarenko, P. Masson, G. Voiron","doi":"10.1109/TASE.2017.8285632","DOIUrl":"https://doi.org/10.1109/TASE.2017.8285632","url":null,"abstract":"Model-based testing of event systems can take advantage of considering abstractions rather than explicit models, for controlling their size. A test is then a connected and reachable event sequence. This paper reports on experiments made when adapting for event systems two known under-approximation techniques of predicate tri-modal (may, must+, must-) abstractions. We first instantiate all the abstract may transitions, preferably as reachable instances. Second, we complete this underapproximation with instantiations of Ball chains, i.e. sequences in the shape of must-∗may.must+∗ transitions, as such sequences are guaranteed to have connected instantiations. We present a backward symbolic instantiation algorithm for connecting these two under-approximations. We experimentally address the question of their complementarity. Surprisingly, our results show that Ball chains have not enhanced the coverage already achieved by the first step of may-transitions instantiation. However, it has enhanced the number of test steps by prolonging the already existing tests.","PeriodicalId":221968,"journal":{"name":"2017 International Symposium on Theoretical Aspects of Software Engineering (TASE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129378124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/TASE.2017.8285633
Haiyang Liu, Tingting Hu, Z. Qiu
Correct mutual-exclusion is one of the key challenges in concurrent programming. Although the fine-grained locking schema can be more efficient compared with the coarse-grained techniques, it is tough to use, as well as error-prone. Here we present a static approach, based on program analysis, to automatically add fine-grained locking primitives to data structures implemented as classes. For tree-like structures, the modified class definitions are guaranteed to be thread-safe. Experiments show that the approach can successfully deal with programs which are challenging to be handled manually, and it works efficiently.
{"title":"Automatic fine-grained locking generation for shared data structures","authors":"Haiyang Liu, Tingting Hu, Z. Qiu","doi":"10.1109/TASE.2017.8285633","DOIUrl":"https://doi.org/10.1109/TASE.2017.8285633","url":null,"abstract":"Correct mutual-exclusion is one of the key challenges in concurrent programming. Although the fine-grained locking schema can be more efficient compared with the coarse-grained techniques, it is tough to use, as well as error-prone. Here we present a static approach, based on program analysis, to automatically add fine-grained locking primitives to data structures implemented as classes. For tree-like structures, the modified class definitions are guaranteed to be thread-safe. Experiments show that the approach can successfully deal with programs which are challenging to be handled manually, and it works efficiently.","PeriodicalId":221968,"journal":{"name":"2017 International Symposium on Theoretical Aspects of Software Engineering (TASE)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122658069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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