Pub Date : 2013-12-02DOI: 10.1109/ISSoC.2013.6675278
Alexandre M. Amory, Matheus T. Moreira, Ney Laert Vilar Calazans, F. Moraes, C. Lazzari, M. Lubaszewski
Intra-chip communication architectures evolved from buses to networks-on-chip, in order to provide design scalability and increased bandwidth. However, the predominant test architecture for SoCs is still based on buses. While this approach presents advantages, such as simple design and a mature set of automation tools, its scalability is questionable. This paper evaluates such aspect by synthesizing SoCs of different sizes (with more than 100 cores) to layout level and extracting accurate results in terms of wire length, capacitance, and delay. The results compare the wiring for test buses and for NoC links, indicating that these test buses have limited scalability (highly irregular wire lengths and long wires) and may not be suitable for testing future SoCs with hundreds of cores. Finally, we discuss advantages and drawbacks of some approaches proposed in the literature. This discussion might give directions towards new scalable SoC test architectural models.
{"title":"Evaluating the scalability of test buses","authors":"Alexandre M. Amory, Matheus T. Moreira, Ney Laert Vilar Calazans, F. Moraes, C. Lazzari, M. Lubaszewski","doi":"10.1109/ISSoC.2013.6675278","DOIUrl":"https://doi.org/10.1109/ISSoC.2013.6675278","url":null,"abstract":"Intra-chip communication architectures evolved from buses to networks-on-chip, in order to provide design scalability and increased bandwidth. However, the predominant test architecture for SoCs is still based on buses. While this approach presents advantages, such as simple design and a mature set of automation tools, its scalability is questionable. This paper evaluates such aspect by synthesizing SoCs of different sizes (with more than 100 cores) to layout level and extracting accurate results in terms of wire length, capacitance, and delay. The results compare the wiring for test buses and for NoC links, indicating that these test buses have limited scalability (highly irregular wire lengths and long wires) and may not be suitable for testing future SoCs with hundreds of cores. Finally, we discuss advantages and drawbacks of some approaches proposed in the literature. This discussion might give directions towards new scalable SoC test architectural models.","PeriodicalId":228272,"journal":{"name":"2013 International Symposium on System on Chip (SoC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133769408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-02DOI: 10.1109/ISSoC.2013.6675269
Purnachand Nalluri, L. N. Alves, A. Navarro
Motion estimation (ME) is one of the critical and most time consuming tasks in video coding. The increase of block size to 64x64 and introduction of asymmetric motion partitioning (AMP) in HEVC makes variable block size motion estimation more complex and therefore requires specific hardware architecture for real time implementation. The ME process includes the calculation of SAD (Sum of Absolute Difference) of two blocks, the current and the reference blocks. The present paper proposes low complexity SAD (Sum of Absolute Difference) architecture for ME of HEVC video encoder, which is able to exploit and optimize parallelism at various levels. The proposed architecture was implemented in FPGA, and compared with other non-parallel SAD architectures. Synthesis results show that the proposed architecture takes fewer resources in FPGA when compared with results from non-parallel architectures and other contributions.
运动估计是视频编码中最关键、最耗时的任务之一。在HEVC中，将块大小增加到64x64以及引入非对称运动分区(AMP)使得可变块大小运动估计变得更加复杂，因此需要特定的硬件架构来实时实现。ME过程包括计算两个块，电流块和参考块的绝对差和(SAD)。本文针对HEVC视频编码器的ME提出了一种低复杂度的绝对差和(Sum of Absolute Difference, SAD)架构，该架构能够充分利用和优化不同层次的并行性。在FPGA上实现了该架构，并与其他非并行SAD架构进行了比较。综合结果表明，与非并行架构和其他贡献的结果相比，该架构在FPGA中占用的资源更少。
{"title":"A novel SAD architecture for variable block size motion estimation in HEVC video coding","authors":"Purnachand Nalluri, L. N. Alves, A. Navarro","doi":"10.1109/ISSoC.2013.6675269","DOIUrl":"https://doi.org/10.1109/ISSoC.2013.6675269","url":null,"abstract":"Motion estimation (ME) is one of the critical and most time consuming tasks in video coding. The increase of block size to 64x64 and introduction of asymmetric motion partitioning (AMP) in HEVC makes variable block size motion estimation more complex and therefore requires specific hardware architecture for real time implementation. The ME process includes the calculation of SAD (Sum of Absolute Difference) of two blocks, the current and the reference blocks. The present paper proposes low complexity SAD (Sum of Absolute Difference) architecture for ME of HEVC video encoder, which is able to exploit and optimize parallelism at various levels. The proposed architecture was implemented in FPGA, and compared with other non-parallel SAD architectures. Synthesis results show that the proposed architecture takes fewer resources in FPGA when compared with results from non-parallel architectures and other contributions.","PeriodicalId":228272,"journal":{"name":"2013 International Symposium on System on Chip (SoC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125505031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-02DOI: 10.1109/ISSoC.2013.6675266
Z. Shirmohammadi, S. Miremadi
Inter-wire coupling capacitance may lead to crosstalk faults that significantly limits the reliability of NoCs. In this paper, we propose a numerical-based crosstalk avoidance code that can omit the Triplet Opposite Direction (TOD) transitions produced by crosstalk faults. The proposed coding does not have ambiguity and uses all of the codeword space. Simulations using VHDL for different channel widths show that the proposed method can reduce crosstalk fault in the NoC links with negligible power and area overheads.
{"title":"Crosstalk avoidance coding for reliable data transmission of network on chips","authors":"Z. Shirmohammadi, S. Miremadi","doi":"10.1109/ISSoC.2013.6675266","DOIUrl":"https://doi.org/10.1109/ISSoC.2013.6675266","url":null,"abstract":"Inter-wire coupling capacitance may lead to crosstalk faults that significantly limits the reliability of NoCs. In this paper, we propose a numerical-based crosstalk avoidance code that can omit the Triplet Opposite Direction (TOD) transitions produced by crosstalk faults. The proposed coding does not have ambiguity and uses all of the codeword space. Simulations using VHDL for different channel widths show that the proposed method can reduce crosstalk fault in the NoC links with negligible power and area overheads.","PeriodicalId":228272,"journal":{"name":"2013 International Symposium on System on Chip (SoC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127702679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-02DOI: 10.1109/ISSoC.2013.6675267
Benedikt Noethen, Oliver Arnold, G. Fettweis
With the increasing number of integrated functional units in Multi-Processor System-on-Chip (MPSoC) the communication among modules is becoming a major challenge. The overall system performance is not only characterized by the computing power but more often limited by the slow interconnections and memory accesses. Furthermore, the available on-chip memory is not efficiently utilized according to the application requirements. This paper describes the concept, implementation and analysis of a data management unit, which improves the utilization of on-chip distributed local memories. Hence data locality and system performance is improved. This strategy leads to a dramatic reduction in the number of accesses to the external memory for data-intensive applications. The impact of this approach on system performance is investigated in this work, which shows a reduction of 53% in the number of accesses to the external memory. In data-limited environments this leads to an improvement of up to 30% in the overall system performance.
{"title":"On the impact of dynamic data management for distributed local memories in heterogeneous MPSoCs","authors":"Benedikt Noethen, Oliver Arnold, G. Fettweis","doi":"10.1109/ISSoC.2013.6675267","DOIUrl":"https://doi.org/10.1109/ISSoC.2013.6675267","url":null,"abstract":"With the increasing number of integrated functional units in Multi-Processor System-on-Chip (MPSoC) the communication among modules is becoming a major challenge. The overall system performance is not only characterized by the computing power but more often limited by the slow interconnections and memory accesses. Furthermore, the available on-chip memory is not efficiently utilized according to the application requirements. This paper describes the concept, implementation and analysis of a data management unit, which improves the utilization of on-chip distributed local memories. Hence data locality and system performance is improved. This strategy leads to a dramatic reduction in the number of accesses to the external memory for data-intensive applications. The impact of this approach on system performance is investigated in this work, which shows a reduction of 53% in the number of accesses to the external memory. In data-limited environments this leads to an improvement of up to 30% in the overall system performance.","PeriodicalId":228272,"journal":{"name":"2013 International Symposium on System on Chip (SoC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124240834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Memory management is a challenging issue of multi-core architecture. With growing core numbers, Distributed Shared Memory (DSM) is becoming a general trend. In this paper, a DSM based multi-core architecture is explored and evaluated via an H.264 decoder application. The memory access and communication over Network-on-Chips is managed by the Data Management Engine (DME). Experimental results realized on an Altera Stratix VI show that 9-node distributed memory system increases performance by 1.5x compared to centralized memory. Moreover, the performance of proposed DSM architecture grows linearly with the number of cores deployed.
{"title":"Efficient distributed memory management in a multi-core H.264 decoder on FPGA","authors":"Jiajie Zhang, Zheng Yu, Zhiyi Yu, Kexin Zhang, Zhonghai Lu, A. Jantsch","doi":"10.1109/ISSoC.2013.6675256","DOIUrl":"https://doi.org/10.1109/ISSoC.2013.6675256","url":null,"abstract":"Memory management is a challenging issue of multi-core architecture. With growing core numbers, Distributed Shared Memory (DSM) is becoming a general trend. In this paper, a DSM based multi-core architecture is explored and evaluated via an H.264 decoder application. The memory access and communication over Network-on-Chips is managed by the Data Management Engine (DME). Experimental results realized on an Altera Stratix VI show that 9-node distributed memory system increases performance by 1.5x compared to centralized memory. Moreover, the performance of proposed DSM architecture grows linearly with the number of cores deployed.","PeriodicalId":228272,"journal":{"name":"2013 International Symposium on System on Chip (SoC)","volume":"26 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115673407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-02DOI: 10.1109/ISSoC.2013.6675268
Jamie Garside, N. Audsley
Within Network-on-Chip architectures the sharing of external memory by many CPUs provides a key challenge within the design in order that memory latencies do not dominate overall performance. Within this paper, we propose and evaluate a stream based prefetch unit within a NoC architecture that utilises a separate shared memory tree to provide access to external memory from each CPU tile. The paper shows that prefetching is an appropriate architectural technique within NoCs, enabling better system performance.
{"title":"Prefetching across a shared memory tree within a Network-on-Chip architecture","authors":"Jamie Garside, N. Audsley","doi":"10.1109/ISSoC.2013.6675268","DOIUrl":"https://doi.org/10.1109/ISSoC.2013.6675268","url":null,"abstract":"Within Network-on-Chip architectures the sharing of external memory by many CPUs provides a key challenge within the design in order that memory latencies do not dominate overall performance. Within this paper, we propose and evaluate a stream based prefetch unit within a NoC architecture that utilises a separate shared memory tree to provide access to external memory from each CPU tile. The paper shows that prefetching is an appropriate architectural technique within NoCs, enabling better system performance.","PeriodicalId":228272,"journal":{"name":"2013 International Symposium on System on Chip (SoC)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134013492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-02DOI: 10.1109/ISSoC.2013.6675282
Alexander W. Rath, Volkan Esen, W. Ecker
The Universal Verification Methodology (UVM) has become a de facto standard in today's functional verification of digital designs. However, it is rarely used for the verification of Designs Under Test containing Real Number Models. This paper presents a new technique using UVM that can be used in order to compare models of analog circuitry on different levels of abstraction. It makes use of statistic metrics. The presented technique enables us to ensure that Real Number Models used in chip projects match the transistor level circuitry during the whole life cycle of the project.
{"title":"Comparison of analog transactions using statistics","authors":"Alexander W. Rath, Volkan Esen, W. Ecker","doi":"10.1109/ISSoC.2013.6675282","DOIUrl":"https://doi.org/10.1109/ISSoC.2013.6675282","url":null,"abstract":"The Universal Verification Methodology (UVM) has become a de facto standard in today's functional verification of digital designs. However, it is rarely used for the verification of Designs Under Test containing Real Number Models. This paper presents a new technique using UVM that can be used in order to compare models of analog circuitry on different levels of abstraction. It makes use of statistic metrics. The presented technique enables us to ensure that Real Number Models used in chip projects match the transistor level circuitry during the whole life cycle of the project.","PeriodicalId":228272,"journal":{"name":"2013 International Symposium on System on Chip (SoC)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115007752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-02DOI: 10.1109/ISSoC.2013.6675271
Zheng Zhou, K. Desnos, M. Pelcat, J. Nezan, W. Plishker, S. Bhattacharyya
Parallelization of Digital Signal Processing (DSP) software is an important trend for MultiProcessor System-on-Chip (MPSoC) implementation. The performance of DSP systems composed of parallelized computations depends on the scheduling technique, which must in general allocate computation and communication resources for competing tasks, and ensure that data dependencies are satisfied. In this paper, we formulate a new type of parallel task scheduling problem called Parallel Actor Scheduling (PAS) for MPSoC mapping of DSP systems that are represented as Synchronous DataFlow (SDF) graphs. In contrast to traditional SDF-based scheduling techniques, which focus on exploiting graph level (inter-actor) parallelism, the PAS problem targets the integrated exploitation of both intra- and inter-actor parallelism for platforms in which individual actors can be parallelized across multiple processing units. We address a special case of the PAS problem in which all of the actors in the DSP application or subsystem being optimized can be parallelized. For this special case, we develop and experimentally evaluate a two-phase scheduling framework with two work flows - particle swarm optimization with a mixed integer programming formulation, and particle swarm optimization with a fast heuristic based on list scheduling. We demonstrate that our PAS-targeted scheduling framework provides a useful range of trade-offs between synthesis time requirements and the quality of the derived solutions.
{"title":"Scheduling of parallelized synchronous dataflow actors","authors":"Zheng Zhou, K. Desnos, M. Pelcat, J. Nezan, W. Plishker, S. Bhattacharyya","doi":"10.1109/ISSoC.2013.6675271","DOIUrl":"https://doi.org/10.1109/ISSoC.2013.6675271","url":null,"abstract":"Parallelization of Digital Signal Processing (DSP) software is an important trend for MultiProcessor System-on-Chip (MPSoC) implementation. The performance of DSP systems composed of parallelized computations depends on the scheduling technique, which must in general allocate computation and communication resources for competing tasks, and ensure that data dependencies are satisfied. In this paper, we formulate a new type of parallel task scheduling problem called Parallel Actor Scheduling (PAS) for MPSoC mapping of DSP systems that are represented as Synchronous DataFlow (SDF) graphs. In contrast to traditional SDF-based scheduling techniques, which focus on exploiting graph level (inter-actor) parallelism, the PAS problem targets the integrated exploitation of both intra- and inter-actor parallelism for platforms in which individual actors can be parallelized across multiple processing units. We address a special case of the PAS problem in which all of the actors in the DSP application or subsystem being optimized can be parallelized. For this special case, we develop and experimentally evaluate a two-phase scheduling framework with two work flows - particle swarm optimization with a mixed integer programming formulation, and particle swarm optimization with a fast heuristic based on list scheduling. We demonstrate that our PAS-targeted scheduling framework provides a useful range of trade-offs between synthesis time requirements and the quality of the derived solutions.","PeriodicalId":228272,"journal":{"name":"2013 International Symposium on System on Chip (SoC)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126217715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-02DOI: 10.1109/ISSoC.2013.6675272
Florian Stock, A. Koch, D. Hildenbrand
Geometric Algebra (GA) is a branch of mathematics that generalizes complex numbers and quaternions. One of the advantages of the framework is, that it allows intuitive description and manipulation of geometric objects. While even complex operations can be described concisely, the actual evaluation of these GA expressions is extremely compute intensive. However, it has significant fine-grained parallelism, which makes it a profitable target for hardware implementation. In this paper, we present the automatic acceleration of a color edge-detection algorithm from a GA description. Using our Gaalop GA compiler with its Verilog back-end, we can show speed-ups of over 1000x even compared to a recent GA processor ASIC.
{"title":"FPGA-accelerated color edge detection using a Geometric-Algebra-to-Verilog compiler","authors":"Florian Stock, A. Koch, D. Hildenbrand","doi":"10.1109/ISSoC.2013.6675272","DOIUrl":"https://doi.org/10.1109/ISSoC.2013.6675272","url":null,"abstract":"Geometric Algebra (GA) is a branch of mathematics that generalizes complex numbers and quaternions. One of the advantages of the framework is, that it allows intuitive description and manipulation of geometric objects. While even complex operations can be described concisely, the actual evaluation of these GA expressions is extremely compute intensive. However, it has significant fine-grained parallelism, which makes it a profitable target for hardware implementation. In this paper, we present the automatic acceleration of a color edge-detection algorithm from a GA description. Using our Gaalop GA compiler with its Verilog back-end, we can show speed-ups of over 1000x even compared to a recent GA processor ASIC.","PeriodicalId":228272,"journal":{"name":"2013 International Symposium on System on Chip (SoC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131776121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-02DOI: 10.1109/ISSoC.2013.6675257
Lorenzo Zuolo, Gabriele Miorandi, C. Zambelli, P. Olivo, D. Bertozzi
MMU-less embedded systems are the state of the art solution for deeply embedded computing environments. Thanks to the rapid evolution of such devices, nowadays applications that run on top of them are evolving from simple control tasks to more complex applications that involve an Operating System (OS). At the same time, cost budget remains unchanged in spite of the growing performance requirements. For this reason, traditional code loading and execution techniques like full code shadowing or execute-in-place may lead to a performance bottleneck. Even demand paging strategies lack consensus due to the customization and the complexity of the software infrastructure dealing with the memory management. The objective of this work is to implement a transparent hardware-based demand paging strategy for code loading and execution, targeting MMU-less embedded systems. This approach consists of making the system interconnect aware of the memory map, without burdening on the legacy OS code, application code and on the compilation framework. This approach materializes lower boot-up latency and shorter application execution time with respect to traditional loading and executing schemes.
{"title":"System interconnect extensions for fully transparent demand paging in low-cost MMU-less embedded systems","authors":"Lorenzo Zuolo, Gabriele Miorandi, C. Zambelli, P. Olivo, D. Bertozzi","doi":"10.1109/ISSoC.2013.6675257","DOIUrl":"https://doi.org/10.1109/ISSoC.2013.6675257","url":null,"abstract":"MMU-less embedded systems are the state of the art solution for deeply embedded computing environments. Thanks to the rapid evolution of such devices, nowadays applications that run on top of them are evolving from simple control tasks to more complex applications that involve an Operating System (OS). At the same time, cost budget remains unchanged in spite of the growing performance requirements. For this reason, traditional code loading and execution techniques like full code shadowing or execute-in-place may lead to a performance bottleneck. Even demand paging strategies lack consensus due to the customization and the complexity of the software infrastructure dealing with the memory management. The objective of this work is to implement a transparent hardware-based demand paging strategy for code loading and execution, targeting MMU-less embedded systems. This approach consists of making the system interconnect aware of the memory map, without burdening on the legacy OS code, application code and on the compilation framework. This approach materializes lower boot-up latency and shorter application execution time with respect to traditional loading and executing schemes.","PeriodicalId":228272,"journal":{"name":"2013 International Symposium on System on Chip (SoC)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121940807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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