Pub Date : 2014-05-26DOI: 10.1109/LASCAS.2014.6820315
Claudia Patricia Renteria-Mejia, A. López-Parrado, Jaime Velasco-Medina
This paper presents the design of two FFT polynomial multipliers using parallel and sequential architectures. Parallel and sequential polynomial multipliers were optimized for throughput and area resources, respectively. The designs are described in generic structural VHDL, synthesized on the Stratix EP4SGX230KF40C2 using Quartus II V. 13, and verified using SignalTap. The hardware synthesis and performance results show that the designed multipliers present a good area-throughput trade-off and they are suitable for high-performance scientific computing applications.
本文介绍了两个FFT多项式乘法器的并行和顺序结构设计。并行多项式乘法器和顺序多项式乘法器分别针对吞吐量和面积资源进行了优化。设计用通用结构VHDL描述，在Stratix EP4SGX230KF40C2上使用Quartus II V. 13进行合成，并使用SignalTap进行验证。硬件综合和性能结果表明，所设计的乘法器具有良好的面积-吞吐量权衡，适用于高性能科学计算应用。
{"title":"Hardware design of FFT polynomial multipliers","authors":"Claudia Patricia Renteria-Mejia, A. López-Parrado, Jaime Velasco-Medina","doi":"10.1109/LASCAS.2014.6820315","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820315","url":null,"abstract":"This paper presents the design of two FFT polynomial multipliers using parallel and sequential architectures. Parallel and sequential polynomial multipliers were optimized for throughput and area resources, respectively. The designs are described in generic structural VHDL, synthesized on the Stratix EP4SGX230KF40C2 using Quartus II V. 13, and verified using SignalTap. The hardware synthesis and performance results show that the designed multipliers present a good area-throughput trade-off and they are suitable for high-performance scientific computing applications.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124747938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-26DOI: 10.1109/LASCAS.2014.6820311
Manuel Carrasco-Robles, M. Delgado-Restituto
This paper proposes a SAR-based circuit suitable to obtain the amount of signal energy contained in EEG frequency bands. It uses a reconfigurable topology which, in a first stage, acts as a conventional data converter for the incoming neural signal and, in a second stage, performs the squaring operation needed for energy extraction. A simple digital circuit keeps track of the most recent outputs from the squarer and provides the accumulated value of the input signal energy. The system has been simulated in an XFAB 0.18μm technology showing correct measurement of the energy.
{"title":"Mixed-signal energy feature extractor of EEG frequency bands","authors":"Manuel Carrasco-Robles, M. Delgado-Restituto","doi":"10.1109/LASCAS.2014.6820311","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820311","url":null,"abstract":"This paper proposes a SAR-based circuit suitable to obtain the amount of signal energy contained in EEG frequency bands. It uses a reconfigurable topology which, in a first stage, acts as a conventional data converter for the incoming neural signal and, in a second stage, performs the squaring operation needed for energy extraction. A simple digital circuit keeps track of the most recent outputs from the squarer and provides the accumulated value of the input signal energy. The system has been simulated in an XFAB 0.18μm technology showing correct measurement of the energy.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132325386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-26DOI: 10.1109/LASCAS.2014.6820267
Benjamín T. Reyes, L. Tealdi, German Paulina, Emanuel Labat, R. Sanchez, P. Mandolesi, M. Hueda
A 6-bit 2-GS/s time interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) is designed and fabricated in a 0.13 μm CMOS process. The architecture uses 8 time-interleaved track-and-hold amplifiers (THA), and 16 SAR ADC's. The chip includes (i) a programmable delay cell array to adjust the interleaved sampling phase, and (ii) a 12 Gbps low voltage differential signaling (LVDS) interface. These blocks make the fabricated ADC an excellent platform to evaluate mixed-signal calibration techniques, which are of great interest for application in high-speed optical systems. Measurements of the fabricated ADC show 33.9 dB of peak signal-to-noise-and-distortion ratio (SNDR) and 192 mW of power consumption at 1.2 V.
{"title":"A 6-bit 2GS/s CMOS time-interleaved ADC for analysis of mixed-signal calibration techniques","authors":"Benjamín T. Reyes, L. Tealdi, German Paulina, Emanuel Labat, R. Sanchez, P. Mandolesi, M. Hueda","doi":"10.1109/LASCAS.2014.6820267","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820267","url":null,"abstract":"A 6-bit 2-GS/s time interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) is designed and fabricated in a 0.13 μm CMOS process. The architecture uses 8 time-interleaved track-and-hold amplifiers (THA), and 16 SAR ADC's. The chip includes (i) a programmable delay cell array to adjust the interleaved sampling phase, and (ii) a 12 Gbps low voltage differential signaling (LVDS) interface. These blocks make the fabricated ADC an excellent platform to evaluate mixed-signal calibration techniques, which are of great interest for application in high-speed optical systems. Measurements of the fabricated ADC show 33.9 dB of peak signal-to-noise-and-distortion ratio (SNDR) and 192 mW of power consumption at 1.2 V.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123352186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-26DOI: 10.1109/LASCAS.2014.6820326
K. Grzesiak-Kopeć, M. Ogorzałek
Computer-aided 3D ICs layout design requires effective search of discontinuous and large spaces of possible solutions. There are no deterministic algorithms able to perform the task. This paper presents a new approach to block-level 3D IC layout design. A simple shape grammar generates possible design solutions. Design specific knowledge is represented as goals and constraints that are both given in the form of predicates. The solution space exploration is driven by an intelligent derivation controller. The proposed concept undergoes practical verification and is illustrated with an example generated by a dedicated application PerfectShape.
{"title":"New approach to block-level 3D IC layout design","authors":"K. Grzesiak-Kopeć, M. Ogorzałek","doi":"10.1109/LASCAS.2014.6820326","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820326","url":null,"abstract":"Computer-aided 3D ICs layout design requires effective search of discontinuous and large spaces of possible solutions. There are no deterministic algorithms able to perform the task. This paper presents a new approach to block-level 3D IC layout design. A simple shape grammar generates possible design solutions. Design specific knowledge is represented as goals and constraints that are both given in the form of predicates. The solution space exploration is driven by an intelligent derivation controller. The proposed concept undergoes practical verification and is illustrated with an example generated by a dedicated application PerfectShape.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123789863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-26DOI: 10.1109/LASCAS.2014.6820290
Bruno Policarpo Toledo Freitas, A. Susin, A. Bonatto
This paper presents the porting of the Ginga MiddleWare onto a Digital Television System-on-Chip. Ginga is an open-source software layer compliant to the Brazilian Digital Television Standard. The porting of Ginga is being carried out on a home made FPGA platform containing a Leon-3 processor running Linux, and the implemented audio and video decoders and graphics processing engine. The SoC has an external memory to store reference frames, OS and Ginga, user interface and applications with local and remote interactivity. Furthermore, accelerators are being designed to boost the SoC performance by implementing in hardware the most processor demanding Ginga primitives, with the profiling being made on a Ginga Virtual machine, therefore creating a “Ginga-Ready” platform.
{"title":"Ginga MiddleWare on a SoC for Digital Television Set-Top Box","authors":"Bruno Policarpo Toledo Freitas, A. Susin, A. Bonatto","doi":"10.1109/LASCAS.2014.6820290","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820290","url":null,"abstract":"This paper presents the porting of the Ginga MiddleWare onto a Digital Television System-on-Chip. Ginga is an open-source software layer compliant to the Brazilian Digital Television Standard. The porting of Ginga is being carried out on a home made FPGA platform containing a Leon-3 processor running Linux, and the implemented audio and video decoders and graphics processing engine. The SoC has an external memory to store reference frames, OS and Ginga, user interface and applications with local and remote interactivity. Furthermore, accelerators are being designed to boost the SoC performance by implementing in hardware the most processor demanding Ginga primitives, with the profiling being made on a Ginga Virtual machine, therefore creating a “Ginga-Ready” platform.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131473638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-26DOI: 10.1109/LASCAS.2014.6820295
Ruchir Saraswat, E. Rodríguez-Villegas
The current work proposes a low emission frequency shift keying (FSK) non-PLL based modulator for transmitting neural signals. FSK has been shown to be viable alternative to widely used ASK (Amplitude Shift Keying). Designers need to start developing low Electromagnetic Interference (EMI) algorithms for implanted devices so as to minimize interference. The proposed algorithm utilizes a ramp to modulate the bit stream from the neural amplifier. The encoded signal is further non-linearly modulated ensuring a lower peak in the power spectrum, a measure of electromagnetic interference. The propose circuit has been fabricated in 0.18μm AMS technology.
{"title":"Chaotic inductively coupled non-PLL low emission transmitter for implanted devices","authors":"Ruchir Saraswat, E. Rodríguez-Villegas","doi":"10.1109/LASCAS.2014.6820295","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820295","url":null,"abstract":"The current work proposes a low emission frequency shift keying (FSK) non-PLL based modulator for transmitting neural signals. FSK has been shown to be viable alternative to widely used ASK (Amplitude Shift Keying). Designers need to start developing low Electromagnetic Interference (EMI) algorithms for implanted devices so as to minimize interference. The proposed algorithm utilizes a ramp to modulate the bit stream from the neural amplifier. The encoded signal is further non-linearly modulated ensuring a lower peak in the power spectrum, a measure of electromagnetic interference. The propose circuit has been fabricated in 0.18μm AMS technology.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128114735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-26DOI: 10.1109/LASCAS.2014.6820265
J. Rengifo, J. Aller, A. Berzoy, J. Restrepo
This paper presents a predictive direct torque control PDTC algorithm for induction machine drives including a Sliding Horizon Prediction (SH-PDTC). The selected strategy for the SH-PDTC algorithm was to keep the motor torque and stator flux-linkage within predefined hysteresis bounds while reducing inverter switching losses. The proposed SH-PDTC algorithm shows better performance in torque and stator flux-linkage control in comparison with classical PDTC, without increasing power losses in the inverter. A sensitivity analysis allows to evaluate algorithm performance under parameter uncertainty, and the results show that SH-PDTC keeps torque ripple performance. The paper includes a simulation to verify the PDTC and SH-PDTC algorithms controlling an induction machine, with a standard two level inverter.
{"title":"Predictive DTC algorithm for induction machines using Sliding Horizon Prediction","authors":"J. Rengifo, J. Aller, A. Berzoy, J. Restrepo","doi":"10.1109/LASCAS.2014.6820265","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820265","url":null,"abstract":"This paper presents a predictive direct torque control PDTC algorithm for induction machine drives including a Sliding Horizon Prediction (SH-PDTC). The selected strategy for the SH-PDTC algorithm was to keep the motor torque and stator flux-linkage within predefined hysteresis bounds while reducing inverter switching losses. The proposed SH-PDTC algorithm shows better performance in torque and stator flux-linkage control in comparison with classical PDTC, without increasing power losses in the inverter. A sensitivity analysis allows to evaluate algorithm performance under parameter uncertainty, and the results show that SH-PDTC keeps torque ripple performance. The paper includes a simulation to verify the PDTC and SH-PDTC algorithms controlling an induction machine, with a standard two level inverter.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132709955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-26DOI: 10.1109/LASCAS.2014.6820270
T. Curtinhas, D. L. Oliveira, D. Bompean, L. Faria, L. Romano
Controllers based on Synchronous Finite State Machines (SFSM) are widely used in the control unit design of complex digital systems. These systems can present critical requirements, such as power consumption, robustness, speed, etc. In this context, the asynchronous paradigm shows interesting features that fit as an alternative for the design, but the lack of appropriate tools and the high difficulty of the design are already drawbacks. This paper proposes a new tool called SICARELO to automatic synthesis of asynchronous FSMs with local clock. The existence of a local clock reduces the requirements of asynchronous logic, enabling the synthesis in any PLD, such as CPLDs and FPGAs, without the need of satisfying any type of macro-cells mapping. The proposed tool starts from a popular specification known as Extended Burst Mode (XBM). The tool SICARELO was tested on a set of benchmarks, compared with 3D and Minimalist tools that are state of the art. SICARELO tool obtained a reduction media in the combinatorial logic of 32% of products and 25% of literals in the XBM_AFSM synthesis with local clock.
{"title":"SICARELO: A tool for synthesis of locally-clocked extended burst-mode asynchronous Controllers","authors":"T. Curtinhas, D. L. Oliveira, D. Bompean, L. Faria, L. Romano","doi":"10.1109/LASCAS.2014.6820270","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820270","url":null,"abstract":"Controllers based on Synchronous Finite State Machines (SFSM) are widely used in the control unit design of complex digital systems. These systems can present critical requirements, such as power consumption, robustness, speed, etc. In this context, the asynchronous paradigm shows interesting features that fit as an alternative for the design, but the lack of appropriate tools and the high difficulty of the design are already drawbacks. This paper proposes a new tool called SICARELO to automatic synthesis of asynchronous FSMs with local clock. The existence of a local clock reduces the requirements of asynchronous logic, enabling the synthesis in any PLD, such as CPLDs and FPGAs, without the need of satisfying any type of macro-cells mapping. The proposed tool starts from a popular specification known as Extended Burst Mode (XBM). The tool SICARELO was tested on a set of benchmarks, compared with 3D and Minimalist tools that are state of the art. SICARELO tool obtained a reduction media in the combinatorial logic of 32% of products and 25% of literals in the XBM_AFSM synthesis with local clock.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133317006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-26DOI: 10.1109/LASCAS.2014.6820319
Bahareh Gholamzadeh, E. Ghafar-Zadeh, F. Awwad, M. Sawan
MEMS sensors can be used for label-free detection in many different biological studies. Usually in this procedure the presence of special substance in a sample can be monitored based on its interaction and binding with specific probe molecules which are immobilized on a sensor. These interactions will result into variations which can be detected by biosensors. Developing a low cost, high throughput system for performing label-free detection can be beneficial for different studies. This type of platform can be used for real-time detection of multiple molecules with high sensitivity. As a first step towards developing such platform, in this paper we present a label-free detection system using an array of 30 cantilevers implemented through standard MEMS foundry process (MetalMUMPs). Herein, we discuss the design, fabrication, and characterization results of the proposed platform using electrical and interferometry techniques. The results from simulations have shown that sensors can be used for measuring small forces in range of nN and pN and the characterization tests have proven that sensors are functional and they are ready to be used in biological experiments.
{"title":"Piezoresistive cantilever platform for label-free detection of molecules","authors":"Bahareh Gholamzadeh, E. Ghafar-Zadeh, F. Awwad, M. Sawan","doi":"10.1109/LASCAS.2014.6820319","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820319","url":null,"abstract":"MEMS sensors can be used for label-free detection in many different biological studies. Usually in this procedure the presence of special substance in a sample can be monitored based on its interaction and binding with specific probe molecules which are immobilized on a sensor. These interactions will result into variations which can be detected by biosensors. Developing a low cost, high throughput system for performing label-free detection can be beneficial for different studies. This type of platform can be used for real-time detection of multiple molecules with high sensitivity. As a first step towards developing such platform, in this paper we present a label-free detection system using an array of 30 cantilevers implemented through standard MEMS foundry process (MetalMUMPs). Herein, we discuss the design, fabrication, and characterization results of the proposed platform using electrical and interferometry techniques. The results from simulations have shown that sensors can be used for measuring small forces in range of nN and pN and the characterization tests have proven that sensors are functional and they are ready to be used in biological experiments.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134376069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-26DOI: 10.1109/LASCAS.2014.6820316
Ismael Seidel, André Beims Bräscher, M. Monteiro, Jose Luis Giintzel
This work investigates the trade-offs between energy and quality in video coding when pel decimation is applied. Realistic estimates for area and energy per block were obtained by simulating five different architectures specially designed to compute the Sum of Absolute Differences (SAD) for 4×4 pixel blocks. Among these architectures, one can be configured to operate with 1:1, 4:3, 2:1 or 4:1 sample ratios, whereas the rest are tailored to operate exclusively with each one of those ratios. The five VLSI architectures were logically synthesized for a 45 nm industrial standard cell library for a target frequency and also for the maximum achievable frequency. They were also simulated with 100 k input vectors obtained by using an H.264/AVC encoder running on one full HD (1080p) video sample. The obtained results show that by using the configurable architecture with full sampling, the best energy/block result was 3.54 pJ/block (60% better than the non-configurable with 7.08 pJ/block). The energy/block value can be further reduced until 1.34 pJ/block at the cost of 2.8% in PSNR, on average, and 14.1% in SSIM, on average.
{"title":"Exploring pel decimation to trade off between energy and quality in video coding","authors":"Ismael Seidel, André Beims Bräscher, M. Monteiro, Jose Luis Giintzel","doi":"10.1109/LASCAS.2014.6820316","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820316","url":null,"abstract":"This work investigates the trade-offs between energy and quality in video coding when pel decimation is applied. Realistic estimates for area and energy per block were obtained by simulating five different architectures specially designed to compute the Sum of Absolute Differences (SAD) for 4×4 pixel blocks. Among these architectures, one can be configured to operate with 1:1, 4:3, 2:1 or 4:1 sample ratios, whereas the rest are tailored to operate exclusively with each one of those ratios. The five VLSI architectures were logically synthesized for a 45 nm industrial standard cell library for a target frequency and also for the maximum achievable frequency. They were also simulated with 100 k input vectors obtained by using an H.264/AVC encoder running on one full HD (1080p) video sample. The obtained results show that by using the configurable architecture with full sampling, the best energy/block result was 3.54 pJ/block (60% better than the non-configurable with 7.08 pJ/block). The energy/block value can be further reduced until 1.34 pJ/block at the cost of 2.8% in PSNR, on average, and 14.1% in SSIM, on average.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123738933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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