Pub Date : 2014-05-26DOI: 10.1109/LASCAS.2014.6820308
R. Conceição, Fabiane Rediess, B. Zatt, M. Porto, L. Agostini
This paper is focused on the Adaptive Loop Filter (ALF) which is responsible to reduce the distortion between an original image and the encoded image during the video coding process by fixing artifacts from previous stages. It was proposed a novel hardware design for the ALF core which is capable to process all ALF sizes (5×5, 7×7 and 9×9), saving hardware resources consumption through reuse. The design was planned to process QFHD (3840 × 2160 pixels) video sequences in real time at 30 frames per second. The synthesis process was targeted to Altera Cyclone II and Stratix V FPGA devices. The synthesis results show that the designed architecture is capable to process 33 QFHD frames per second, considering the Stratix V implementation.
本文重点研究了自适应环路滤波器(ALF)，它通过固定前一阶段的伪影来减少视频编码过程中原始图像与编码图像之间的失真。提出了一种新颖的ALF核硬件设计，能够处理所有大小的ALF (5×5、7×7和9×9)，通过重用节省硬件资源消耗。该设计计划以每秒30帧的速度实时处理QFHD (3840 × 2160像素)视频序列。合成过程针对Altera Cyclone II和Stratix V FPGA器件。综合结果表明，考虑到Stratix V的实现，所设计的体系结构能够每秒处理33个QFHD帧。
{"title":"Configurable hardware design for the HEVC-based Adaptive Loop Filter","authors":"R. Conceição, Fabiane Rediess, B. Zatt, M. Porto, L. Agostini","doi":"10.1109/LASCAS.2014.6820308","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820308","url":null,"abstract":"This paper is focused on the Adaptive Loop Filter (ALF) which is responsible to reduce the distortion between an original image and the encoded image during the video coding process by fixing artifacts from previous stages. It was proposed a novel hardware design for the ALF core which is capable to process all ALF sizes (5×5, 7×7 and 9×9), saving hardware resources consumption through reuse. The design was planned to process QFHD (3840 × 2160 pixels) video sequences in real time at 30 frames per second. The synthesis process was targeted to Altera Cyclone II and Stratix V FPGA devices. The synthesis results show that the designed architecture is capable to process 33 QFHD frames per second, considering the Stratix V implementation.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115293745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-26DOI: 10.1109/LASCAS.2014.6820313
M. Terres, C. Meinhardt, G. Bontorin, R. Reis
Multiple Dynamic Supply Voltage (MDSV) is a technique that focuses on reducing the dynamic power. This technique is an evolution of the Multiple Supply Voltage (MSV). MSV and MDSV introduce some difference on traditional physical synthesis due to the different voltage operations of each region in the design. To convert the voltage among regions supplied by different voltages, these techniques insert a Level Shifter (LS) circuit. As a penalty consequence, traditional LS circuits insert a delay and extra power consumption in the design. The dynamical behavior of MDSV designs has brought a new condition, where LS inserted in the circuit can be in an idle state temporally. This work presents a new architecture to reduce the power consumption and delay, bypassing the LS. The architecture explores an alternative path to current flow in the cases that LS is idle. With this new approach we reduce up to 15% of power consumption and up to 75% and 15% of delay.
{"title":"Exploring more efficient architectures for Multiple Dynamic Supply Voltage designs","authors":"M. Terres, C. Meinhardt, G. Bontorin, R. Reis","doi":"10.1109/LASCAS.2014.6820313","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820313","url":null,"abstract":"Multiple Dynamic Supply Voltage (MDSV) is a technique that focuses on reducing the dynamic power. This technique is an evolution of the Multiple Supply Voltage (MSV). MSV and MDSV introduce some difference on traditional physical synthesis due to the different voltage operations of each region in the design. To convert the voltage among regions supplied by different voltages, these techniques insert a Level Shifter (LS) circuit. As a penalty consequence, traditional LS circuits insert a delay and extra power consumption in the design. The dynamical behavior of MDSV designs has brought a new condition, where LS inserted in the circuit can be in an idle state temporally. This work presents a new architecture to reduce the power consumption and delay, bypassing the LS. The architecture explores an alternative path to current flow in the cases that LS is idle. With this new approach we reduce up to 15% of power consumption and up to 75% and 15% of delay.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116527935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-26DOI: 10.1109/LASCAS.2014.6820291
A. S. Nery, N. Nedjah, F. França, L. Józwiak, H. Corporaal
Instruction Set Customization is a well-known technique to enhance the performance and efficiency of Application-Specific Processors (ASIPs). An extensive application profiling can indicate which parts of a given application, or class of applications, are most frequently executed, enabling the implementation of such frequently executed parts in hardware as custom instructions. However, a naive ad hoc instruction set customization process may identify and select poor instruction extension candidates, which may not result in a significantly improved performance with low circuit-area and energy footprints. In this paper we propose and discuss an efficient instruction set customization method and automatic tool, which exploit the maximal common subgraphs (common operation patterns) of the most frequently executed basic blocks of a given application. The speed results from our tool for a VLIW ASIP are provided for a set of benchmark applications. The average execution time reduction ranges from 30% to 40%, with only a few custom instructions.
{"title":"Automatic complex instruction identification for efficient application mapping onto ASIPs","authors":"A. S. Nery, N. Nedjah, F. França, L. Józwiak, H. Corporaal","doi":"10.1109/LASCAS.2014.6820291","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820291","url":null,"abstract":"Instruction Set Customization is a well-known technique to enhance the performance and efficiency of Application-Specific Processors (ASIPs). An extensive application profiling can indicate which parts of a given application, or class of applications, are most frequently executed, enabling the implementation of such frequently executed parts in hardware as custom instructions. However, a naive ad hoc instruction set customization process may identify and select poor instruction extension candidates, which may not result in a significantly improved performance with low circuit-area and energy footprints. In this paper we propose and discuss an efficient instruction set customization method and automatic tool, which exploit the maximal common subgraphs (common operation patterns) of the most frequently executed basic blocks of a given application. The speed results from our tool for a VLIW ASIP are provided for a set of benchmark applications. The average execution time reduction ranges from 30% to 40%, with only a few custom instructions.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126452092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-26DOI: 10.1109/LASCAS.2014.6820276
R. Neli, I. Doi, J. A. Diniz
This work has as a main goal the characterization of thermal sensors, described as bolometer, which are dedicated to far infrared radiation detection. These sensors are fabricated using microfabrication techniques and the thin films are selective to wet etching. These mechanical microstructures are formed on silicon wafers using surface wet etching. As these structures are obtained using conventional techniques for integrated circuits manufacturing, it becomes possible perform monolithic integration of electronics and mechanical devices, allowing the integrated microsystems development. The porous gold or “gold black” used as a radiation absorber, showed absorption index greater than 80%.
{"title":"Characterization of fast-response and low-noise poly si uncooled far infrared sensor","authors":"R. Neli, I. Doi, J. A. Diniz","doi":"10.1109/LASCAS.2014.6820276","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820276","url":null,"abstract":"This work has as a main goal the characterization of thermal sensors, described as bolometer, which are dedicated to far infrared radiation detection. These sensors are fabricated using microfabrication techniques and the thin films are selective to wet etching. These mechanical microstructures are formed on silicon wafers using surface wet etching. As these structures are obtained using conventional techniques for integrated circuits manufacturing, it becomes possible perform monolithic integration of electronics and mechanical devices, allowing the integrated microsystems development. The porous gold or “gold black” used as a radiation absorber, showed absorption index greater than 80%.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121702733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-26DOI: 10.1109/LASCAS.2014.6820299
Lívia Amaral, D. Silveira, Guilherme Povala, M. Porto, L. Agostini, B. Zatt
A very important component in video coding systems is the Motion Estimation (ME), that excels not only in computational cost, but off-chip memory bandwidth consumption as well. These two issues are considered critical constraints for video coding systems, especially for High Definition (HD) videos, since a large volume of data must be processed. This work presents an energy and memory bandwidth reduction approach by using two techniques for external bandwidth reduction from the literature: data reuse and reference frames compression. The proposed solution achieves high rates of memory bandwidth reduction for both writing and reading operations, reaching 31.69% and 86.32% respectively. Therewith, this scheme is able to reduce 80.67% of the ME energy consumption when compared to the traditional method, which presents no bandwidth reduction scheme. The ME search algorithm Full Search (FS) was considered for all evaluations. The solution presented is considered lossless, with no quality degradation for the coded video, and fully complied with current video coding standards.
{"title":"Memory energy consumption reduction in video coding systems","authors":"Lívia Amaral, D. Silveira, Guilherme Povala, M. Porto, L. Agostini, B. Zatt","doi":"10.1109/LASCAS.2014.6820299","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820299","url":null,"abstract":"A very important component in video coding systems is the Motion Estimation (ME), that excels not only in computational cost, but off-chip memory bandwidth consumption as well. These two issues are considered critical constraints for video coding systems, especially for High Definition (HD) videos, since a large volume of data must be processed. This work presents an energy and memory bandwidth reduction approach by using two techniques for external bandwidth reduction from the literature: data reuse and reference frames compression. The proposed solution achieves high rates of memory bandwidth reduction for both writing and reading operations, reaching 31.69% and 86.32% respectively. Therewith, this scheme is able to reduce 80.67% of the ME energy consumption when compared to the traditional method, which presents no bandwidth reduction scheme. The ME search algorithm Full Search (FS) was considered for all evaluations. The solution presented is considered lossless, with no quality degradation for the coded video, and fully complied with current video coding standards.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114245539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-26DOI: 10.1109/LASCAS.2014.6820277
Pedro Cisneros, P. Rodríguez
Hand tracking is the automatic detection and displaying of the user hands captured by a camera throughout a video. This paper proposes a practical solution to two main hand tracking problems: the mutual occlusion between hands and the recovery from a lost tracking. This is done by alternating the use of a priori information about past hand locations according to the presence of a problematic situation. We propose a deterministic solution capable of working at different video resolutions without the need of any early learning stage or hard-coded initial calibration. Thus, it is practical in the sense of its implementation and use. Our experimental results, which are compared to the state of the art, shows that our solution is computationally efficient and has a good performance in different lighting and motion situations, both in terms of speed and precision error.
{"title":"Practical hand tracking solution by alternating the use of a priori information","authors":"Pedro Cisneros, P. Rodríguez","doi":"10.1109/LASCAS.2014.6820277","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820277","url":null,"abstract":"Hand tracking is the automatic detection and displaying of the user hands captured by a camera throughout a video. This paper proposes a practical solution to two main hand tracking problems: the mutual occlusion between hands and the recovery from a lost tracking. This is done by alternating the use of a priori information about past hand locations according to the presence of a problematic situation. We propose a deterministic solution capable of working at different video resolutions without the need of any early learning stage or hard-coded initial calibration. Thus, it is practical in the sense of its implementation and use. Our experimental results, which are compared to the state of the art, shows that our solution is computationally efficient and has a good performance in different lighting and motion situations, both in terms of speed and precision error.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126956957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-26DOI: 10.1109/LASCAS.2014.6820324
K. Weide-Zaage, A. Moujbani, J. Kludt
The development of 3D-silicon integrated circuits is an increasing demand especially regarding to advanced 3D-packages and high performance applications, with the intend to miniaturize and to reduce costs. Through-silicon-vias (TSV), interconnects and landing pads have a strong mismatch in proportions. Due to high temperature as well as high applied currents, the reliability of the systems and components is affected by thermal and thermal-electrical loads. The induced stress leads to degradation effects like electro- and thermomigration (EM, TM). Mismatch in coefficient of thermal expansion (CTE) are causing mechanical induced stress during the manufacturing process. This can lead to failure mechanisms like delamination and cracking around the TSV or in the ICs.
{"title":"Simulation in 3D integration and TSV","authors":"K. Weide-Zaage, A. Moujbani, J. Kludt","doi":"10.1109/LASCAS.2014.6820324","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820324","url":null,"abstract":"The development of 3D-silicon integrated circuits is an increasing demand especially regarding to advanced 3D-packages and high performance applications, with the intend to miniaturize and to reduce costs. Through-silicon-vias (TSV), interconnects and landing pads have a strong mismatch in proportions. Due to high temperature as well as high applied currents, the reliability of the systems and components is affected by thermal and thermal-electrical loads. The induced stress leads to degradation effects like electro- and thermomigration (EM, TM). Mismatch in coefficient of thermal expansion (CTE) are causing mechanical induced stress during the manufacturing process. This can lead to failure mechanisms like delamination and cracking around the TSV or in the ICs.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128909424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-26DOI: 10.1109/LASCAS.2014.6820259
S. Lahmiri, M. Boukadoum
An adjusted empirical mode decomposition method, built on Student's probability density function is presented. Compared to the original EMD, the new version provides a lower number of intrinsic mode functions and is more accurate in signal modeling and prediction. Using a backpropagation neural network for learning and in-sample prediction, our experimental results on a synthetic signal, an electrocardiogram (ECG), and a financial time series show that the presented tEMD is more efficient and leads to higher prediction accuracy than conventional EMD, regardless of the input time signal.
{"title":"Adjusted empirical mode decomposition with improved performance for signal modeling and prediction","authors":"S. Lahmiri, M. Boukadoum","doi":"10.1109/LASCAS.2014.6820259","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820259","url":null,"abstract":"An adjusted empirical mode decomposition method, built on Student's probability density function is presented. Compared to the original EMD, the new version provides a lower number of intrinsic mode functions and is more accurate in signal modeling and prediction. Using a backpropagation neural network for learning and in-sample prediction, our experimental results on a synthetic signal, an electrocardiogram (ECG), and a financial time series show that the presented tEMD is more efficient and leads to higher prediction accuracy than conventional EMD, regardless of the input time signal.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128931683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-26DOI: 10.1109/LASCAS.2014.6820285
P. Massolino, C. Margi, Paulo L. Barreto, W. Ruggiero
Error correcting codes are useful tools not only for increasing channel reliability in telecommunications systems, but also for the asymmetric encryption cryptographic schemes. Their operation consists basically in encoding messages into codewords for transmission; once received, these messages are decoded and the original message is recovered after the removal of all bit errors introduced either due to interferences in the medium or intentionally during the encryption process. Both encoding and decoding operations can be implemented as software libraries and/or hardware circuits, although the latter is sometimes preferable due to the higher throughput they provide. One particular type of error correcting code has particular interest in the field of cryptography: binary Quasi-Dyadic Goppa (QD-Goppa) codes, a subset of binary Goppa codes. Indeed, these codes were proposed as a replacement for generic binary Goppa codes in cryptographic applications, since their internal structure allows the optimization of execution time and storage requirements for public and private keys. Despite the interest of such codes, to the best of our knowledge the literature does not include hardware implementation and evaluation of such codes. Aiming to close this gap, in this paper we discuss our results when designing and simulating a scalable hardware architecture for the encoding operation of binary QD-Goppa codes. This architecture was described using VHDL and simulated in Synopsys tools for security levels of 80 to 256 bits, using a 90nm cell library. With this architecture, we obtained processing times from 95 ms to 12 μs and an area occupation from 850 GE to 42 kGE, which allow its utilization even in restricted-resource applications.
{"title":"Scalable hardware implementation for Quasi-Dyadic Goppa encoder","authors":"P. Massolino, C. Margi, Paulo L. Barreto, W. Ruggiero","doi":"10.1109/LASCAS.2014.6820285","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820285","url":null,"abstract":"Error correcting codes are useful tools not only for increasing channel reliability in telecommunications systems, but also for the asymmetric encryption cryptographic schemes. Their operation consists basically in encoding messages into codewords for transmission; once received, these messages are decoded and the original message is recovered after the removal of all bit errors introduced either due to interferences in the medium or intentionally during the encryption process. Both encoding and decoding operations can be implemented as software libraries and/or hardware circuits, although the latter is sometimes preferable due to the higher throughput they provide. One particular type of error correcting code has particular interest in the field of cryptography: binary Quasi-Dyadic Goppa (QD-Goppa) codes, a subset of binary Goppa codes. Indeed, these codes were proposed as a replacement for generic binary Goppa codes in cryptographic applications, since their internal structure allows the optimization of execution time and storage requirements for public and private keys. Despite the interest of such codes, to the best of our knowledge the literature does not include hardware implementation and evaluation of such codes. Aiming to close this gap, in this paper we discuss our results when designing and simulating a scalable hardware architecture for the encoding operation of binary QD-Goppa codes. This architecture was described using VHDL and simulated in Synopsys tools for security levels of 80 to 256 bits, using a 90nm cell library. With this architecture, we obtained processing times from 95 ms to 12 μs and an area occupation from 850 GE to 42 kGE, which allow its utilization even in restricted-resource applications.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123653920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-26DOI: 10.1109/LASCAS.2014.6820293
J. Tarrillo, Fernando A. Escobar, F. Kastensmidt, C. Valderrama
Dynamic partial reconfiguration (DPR) is a technique that optimizes resource utilization of SRAM-based FPGAs, since it allows changing, on the fly, the functionality of a portion of its logic. A common DPR development flow requires the use of, at least, a microprocessor and several development tools (EDK, XSDK, PlanAhead); moreover, proposals are mainly based on MicroBlaze, ARM or PowerPC embedded processors, which also require extra memory control blocks. This article presents a generic DPR manager IP core (Intellectual Property), whose versatility allows the use of either any embedded processor or simple control logic. Results in terms of reconfiguration time and resources for Virtex 5 and Virtex 6 SRAM-FPGAs show its advantages and interest over traditional solutions.
{"title":"Dynamic partial reconfiguration manager","authors":"J. Tarrillo, Fernando A. Escobar, F. Kastensmidt, C. Valderrama","doi":"10.1109/LASCAS.2014.6820293","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820293","url":null,"abstract":"Dynamic partial reconfiguration (DPR) is a technique that optimizes resource utilization of SRAM-based FPGAs, since it allows changing, on the fly, the functionality of a portion of its logic. A common DPR development flow requires the use of, at least, a microprocessor and several development tools (EDK, XSDK, PlanAhead); moreover, proposals are mainly based on MicroBlaze, ARM or PowerPC embedded processors, which also require extra memory control blocks. This article presents a generic DPR manager IP core (Intellectual Property), whose versatility allows the use of either any embedded processor or simple control logic. Results in terms of reconfiguration time and resources for Virtex 5 and Virtex 6 SRAM-FPGAs show its advantages and interest over traditional solutions.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127763594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：