Summary form only given. Discrete structures are foundational materials for computer science and mathematics, which are related to set theory, symbolic logic, inductive proof, graph theory, combinatorics, probability theory, etc. Many problems are decomposed into discrete structures using simple primitive algebraic operations. A Binary Decision Diagram (BDD) is a representation of a Boolean function, one of the most basic models of discrete structures. After the epoch-making paper [1] by Bryant in 1986, BDD-based methods have attracted a great deal of attention. The BDD was originally developed for the efficient Boolean function manipulation required in VLSI logic design, however, later they are also used for sets of combinations which represent many kinds of combinatorial patterns. A Zero-suppressed BDD (ZDD) [2] is a variant of the BDD, customized for representing a set of combinations. ZDDs have been successfully applied not only to VLSI design, but also for solving various combinatorial problems, such as constraint satisfaction, frequent pattern mining, and graph enumeration. Recently, ZDDs have become more widely known, since D. E. Knuth intensively discussed ZDD-based algorithms in the latest volume of his famous series of books [3]. Although a quarter of a century has passed since Bryant first put forth his idea, there are still many interesting and exciting research topics related to BDDs and ZDDs [4]. One of the most important topics would be that, Knuth presented an extremely fast algorithm "Simpath" [3] to construct a ZDD which enumerates all the paths connecting two points in a given graph structure. This work is important because many kinds of practical problems are efficiently solved by some variations of this algorithm. We generically call such ZDD construction methods "frontier-based methods." The above techniques of data structures and algorithms have been implemented and published as an open software library, named "Graphillion"[5], [6]. Graphillion is a library for manipulating very large sets of graphs, based on ZDDs and frontier-based method. Graphillion is implemented as a Python extension in C++, to encourage easy development of its applications without introducing significant performance overhead. In order to organize an integrated method of algebraic operations for manipulating various types of discrete structures, and to construct standard techniques for efficiently solving large-scale and practical problems in various fields, A governmental agency in Japan started a nation-wide project: ERATO MINATO Discrete Structure Manipulation System Project in 2009. The project was successfully finished in this year, and a successor project, JSPS KAKENHI(S), is now running until 2020. Many interesting research results were produced in the last ERATO project, and some of topics are still attractive to be explored more. In this talk, we first show an overview of our research project, and then explain the basic techniques of BDDs and
{"title":"Power of Enumeration -- BDD/ZDD-Based Techniques for Discrete Structure Manipulation","authors":"S. Minato","doi":"10.1109/ISMVL.2016.49","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.49","url":null,"abstract":"Summary form only given. Discrete structures are foundational materials for computer science and mathematics, which are related to set theory, symbolic logic, inductive proof, graph theory, combinatorics, probability theory, etc. Many problems are decomposed into discrete structures using simple primitive algebraic operations. A Binary Decision Diagram (BDD) is a representation of a Boolean function, one of the most basic models of discrete structures. After the epoch-making paper [1] by Bryant in 1986, BDD-based methods have attracted a great deal of attention. The BDD was originally developed for the efficient Boolean function manipulation required in VLSI logic design, however, later they are also used for sets of combinations which represent many kinds of combinatorial patterns. A Zero-suppressed BDD (ZDD) [2] is a variant of the BDD, customized for representing a set of combinations. ZDDs have been successfully applied not only to VLSI design, but also for solving various combinatorial problems, such as constraint satisfaction, frequent pattern mining, and graph enumeration. Recently, ZDDs have become more widely known, since D. E. Knuth intensively discussed ZDD-based algorithms in the latest volume of his famous series of books [3]. Although a quarter of a century has passed since Bryant first put forth his idea, there are still many interesting and exciting research topics related to BDDs and ZDDs [4]. One of the most important topics would be that, Knuth presented an extremely fast algorithm \"Simpath\" [3] to construct a ZDD which enumerates all the paths connecting two points in a given graph structure. This work is important because many kinds of practical problems are efficiently solved by some variations of this algorithm. We generically call such ZDD construction methods \"frontier-based methods.\" The above techniques of data structures and algorithms have been implemented and published as an open software library, named \"Graphillion\"[5], [6]. Graphillion is a library for manipulating very large sets of graphs, based on ZDDs and frontier-based method. Graphillion is implemented as a Python extension in C++, to encourage easy development of its applications without introducing significant performance overhead. In order to organize an integrated method of algebraic operations for manipulating various types of discrete structures, and to construct standard techniques for efficiently solving large-scale and practical problems in various fields, A governmental agency in Japan started a nation-wide project: ERATO MINATO Discrete Structure Manipulation System Project in 2009. The project was successfully finished in this year, and a successor project, JSPS KAKENHI(S), is now running until 2020. Many interesting research results were produced in the last ERATO project, and some of topics are still attractive to be explored more. In this talk, we first show an overview of our research project, and then explain the basic techniques of BDDs and ","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121132859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Index generation functions are a particular class of switching (Boolean or multiple-valued) functions that have some important applications in communication, data retrieval and processing, and related areas. For these applications, determining compact representations of index generation functions is an important task. An approach towards this is to perform a linear transformation to reduce the number of required variables, but finding an optimal transformation can be difficult. In this paper, we propose non-linear transformations to reduce the number of variables, and formulate the problem of finding a good linear transformation using linear subspaces. Extending the set of initial variables by products of variables makes it easier to find a compact representation as the number of suitable transformations becomes larger.
{"title":"Index Generation Functions Based on Linear and Polynomial Transformations","authors":"Helena Astola, R. Stankovic, J. Astola","doi":"10.1109/ISMVL.2016.20","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.20","url":null,"abstract":"Index generation functions are a particular class of switching (Boolean or multiple-valued) functions that have some important applications in communication, data retrieval and processing, and related areas. For these applications, determining compact representations of index generation functions is an important task. An approach towards this is to perform a linear transformation to reduce the number of required variables, but finding an optimal transformation can be difficult. In this paper, we propose non-linear transformations to reduce the number of variables, and formulate the problem of finding a good linear transformation using linear subspaces. Extending the set of initial variables by products of variables makes it easier to find a compact representation as the number of suitable transformations becomes larger.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131359435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a solution for fault-tolerance in logic circuits comprised of Carbon Nanotube FETs (CNTFETs). This work builds on a recently proposed method for error-correction called Restorative Feedback (RFB). The RFB method is a variant of Triple-Modular Redundancy (TMR) that utilizes the fault masking capabilities of the Muller C element to provide added protection against transient faults caused by electronic noise. A novel design is proposed for implementing a ternary C element. We also show the ability of RFB method to suppress internal transient noise in CNTFET multi-valued logic (MVL) circuits.
{"title":"CNTFET-RFB: An Error Correction Implementation for Multi-valued CNTFET Logic","authors":"Gopalakrishnan Sundararajan, C. Winstead","doi":"10.1109/ISMVL.2016.41","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.41","url":null,"abstract":"This paper presents a solution for fault-tolerance in logic circuits comprised of Carbon Nanotube FETs (CNTFETs). This work builds on a recently proposed method for error-correction called Restorative Feedback (RFB). The RFB method is a variant of Triple-Modular Redundancy (TMR) that utilizes the fault masking capabilities of the Muller C element to provide added protection against transient faults caused by electronic noise. A novel design is proposed for implementing a ternary C element. We also show the ability of RFB method to suppress internal transient noise in CNTFET multi-valued logic (MVL) circuits.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122168761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
By a De Morgan algebra is meant a bounded poset equipped with an antitone involution considered as negation. Such an algebra can be considered as an algebraic axiomatization of a propositional logic satisfying the double negation law. Our aim is to introduce the so-called tense operators in every De Morgan algebra for to get an algebraic counterpart of a tense logic with negation satisfying the double negation law which need not be Boolean. Following the standard construction of tense operators G and H by a frame we solve the following question: if a dynamic De Morgan algebra is given, how to find a frame such that its tense operators G and H can be reached by this construction.
{"title":"Set Representation of Partial Dynamic De Morgan Algebras","authors":"I. Chajda, Jan Paseka","doi":"10.1109/ISMVL.2013.56.","DOIUrl":"https://doi.org/10.1109/ISMVL.2013.56.","url":null,"abstract":"By a De Morgan algebra is meant a bounded poset equipped with an antitone involution considered as negation. Such an algebra can be considered as an algebraic axiomatization of a propositional logic satisfying the double negation law. Our aim is to introduce the so-called tense operators in every De Morgan algebra for to get an algebraic counterpart of a tense logic with negation satisfying the double negation law which need not be Boolean. Following the standard construction of tense operators G and H by a frame we solve the following question: if a dynamic De Morgan algebra is given, how to find a frame such that its tense operators G and H can be reached by this construction.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125143323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We define a generalized state operator σ on a residuated lattice X and a g-state residuated lattice (X,σ), and consider properties of g-state residuated lattices. We show that a characterization theorem of σ-filters and that the class Fσ (X) of all σ-filters of a g-state residuated lattice (X, σ) is a Heyting algebra. Moreover we prove that every g-state residuated lattice (X, σ) is isomprphic to a subdirect product of g-state residuated lattices {(X/P, σ/P)}P∈Specσ(X), where Specσ(X) is the set of all prime σ-filters of (X, σ).
{"title":"Some Properties of Generalized State Operators on Residuated Lattices","authors":"M. Kondo, M. Kawaguchi","doi":"10.1109/ISMVL.2016.29","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.29","url":null,"abstract":"We define a generalized state operator σ on a residuated lattice X and a g-state residuated lattice (X,σ), and consider properties of g-state residuated lattices. We show that a characterization theorem of σ-filters and that the class F<sub>σ</sub> (X) of all σ-filters of a g-state residuated lattice (X, σ) is a Heyting algebra. Moreover we prove that every g-state residuated lattice (X, σ) is isomprphic to a subdirect product of g-state residuated lattices {(X/P, σ/P)}<sub>P∈Specσ</sub>(X), where Spec<sub>σ</sub>(X) is the set of all prime σ-filters of (X, σ).","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117348499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Md Belayet Ali, T. Hirayama, Katsuhisa Yamanaka, Y. Nishitani
The NCV (NOT, CNOT and Controlled-V/V) gate set is most commonly used for the realization of classical reversible functions and implementation of quantum circuits. Logic operations in quantum circuits are performed by individual gates or can be expressed as matrix-vector multiplication. Thispaper presents a two-qubit quantum gate library which consists most commonly used elementary quantum gates NOT, CNOT, Controlled-V and Controlled-V. The new library contains all possible two-qubit quantum gates which do not produce entangled states in the final output state. Two approaches have been appliedto generate the new two-qubit quantum gate library because it hasbeen observed that some entangled gates act like non-entangledif those entangled gates are merged with other valid gates in thelibrary. The experimental result shows the difference betweenthe libraries with and without considering entangled gates in theprocess of generating new gates.
{"title":"New Two-Qubit Gate Library with Entanglement","authors":"Md Belayet Ali, T. Hirayama, Katsuhisa Yamanaka, Y. Nishitani","doi":"10.1109/ISMVL.2016.26","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.26","url":null,"abstract":"The NCV (NOT, CNOT and Controlled-V/V) gate set is most commonly used for the realization of classical reversible functions and implementation of quantum circuits. Logic operations in quantum circuits are performed by individual gates or can be expressed as matrix-vector multiplication. Thispaper presents a two-qubit quantum gate library which consists most commonly used elementary quantum gates NOT, CNOT, Controlled-V and Controlled-V. The new library contains all possible two-qubit quantum gates which do not produce entangled states in the final output state. Two approaches have been appliedto generate the new two-qubit quantum gate library because it hasbeen observed that some entangled gates act like non-entangledif those entangled gates are merged with other valid gates in thelibrary. The experimental result shows the difference betweenthe libraries with and without considering entangled gates in theprocess of generating new gates.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116939970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a method to realize index generation functions using multiple Index Generation Units (IGUs). The architecture implements index generation functions more efficiently than a single IGU when the number of registered vectors is very large. This paper also proves that independent linear transformations are necessary in IGUs for efficient realization. Experimental results confirm this statement.
{"title":"A Realization of Index Generation Functions Using Multiple IGUs","authors":"Tsutomu Sasao","doi":"10.1109/ISMVL.2016.17","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.17","url":null,"abstract":"This paper presents a method to realize index generation functions using multiple Index Generation Units (IGUs). The architecture implements index generation functions more efficiently than a single IGU when the number of registered vectors is very large. This paper also proves that independent linear transformations are necessary in IGUs for efficient realization. Experimental results confirm this statement.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121789277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, an embedded stack machine for high voltage Intelligent Power Modules (IPMs) is presented. The proposed architecture is fabricated in TSMCs 0.18μm BCD process alongside a 10-bit SAR ADC, a 10-bit counter based Digital Pulse Width Modulator (DPWM) and an Insulated Gate Bipolar Transistor (IGBT) gate driver. The fabricated IC is incorporated into a IGBT based IPM and used to implement a Duty Cycle Correction (DCC) Algorithm to improve output current regulation.
{"title":"SPRUCE, an Embedded Compact Stack Machine for IGBT Power Modules","authors":"A. Shorten, W. Ng","doi":"10.1109/ISMVL.2016.59","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.59","url":null,"abstract":"In this paper, an embedded stack machine for high voltage Intelligent Power Modules (IPMs) is presented. The proposed architecture is fabricated in TSMCs 0.18μm BCD process alongside a 10-bit SAR ADC, a 10-bit counter based Digital Pulse Width Modulator (DPWM) and an Insulated Gate Bipolar Transistor (IGBT) gate driver. The fabricated IC is incorporated into a IGBT based IPM and used to implement a Duty Cycle Correction (DCC) Algorithm to improve output current regulation.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"219 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126109985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Jeavons, Andrius Vaicenavicius, Stanislav Živný
We study algebraic structures called weighted clones. These structures characterise the computational complexity of discrete optimisation problems of special form, known as valued constraint satisfaction problems. We identify all minimal weighted clones for every Boolean support clone.
{"title":"Minimal Weighted Clones with Boolean Support","authors":"P. Jeavons, Andrius Vaicenavicius, Stanislav Živný","doi":"10.1109/ISMVL.2016.10","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.10","url":null,"abstract":"We study algebraic structures called weighted clones. These structures characterise the computational complexity of discrete optimisation problems of special form, known as valued constraint satisfaction problems. We identify all minimal weighted clones for every Boolean support clone.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127175066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A centralizing monoid M is a set of unary functions which commute with all members of some set F of multi-variable functions. The set F is called a witness of M. In this paper, we study centralizing monoids on a three-element set which have sets of binary idempotent functions as their witnesses. It is shown that the number of such centralizing monoids is 67.
{"title":"Centralizing Monoids on a Three-Element Set Related to Binary Idempotent Functions","authors":"Hajime Machida, I. Rosenberg","doi":"10.1109/ISMVL.2016.32","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.32","url":null,"abstract":"A centralizing monoid M is a set of unary functions which commute with all members of some set F of multi-variable functions. The set F is called a witness of M. In this paper, we study centralizing monoids on a three-element set which have sets of binary idempotent functions as their witnesses. It is shown that the number of such centralizing monoids is 67.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129223412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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