This paper makes a theoretical comparative analysis of the Reed-Muller-Fourier Transform, Pascal matrices based on the Pascal triangle, and the Discrete Pascal Transform. The Reed-Muller-Fourier Transform was not originated by a Pascal matrix, however it happens to show a strong family resemblance with it, sharing several basic properties. Its area of application is the multiple-valued switching theory, mainly to obtain polynomial expressions from the value vector of multiple-valued functions. The Discrete Pascal Transform was introduced over a decade later, based on an ad hoc modification of a Pascal matrix, for applications on picture processing. It is however shown that a Discrete Pascal Transform of size p, taken modulo p equals the special Reed-Muller-Fourier Transform for the same p and n = 1. The Sierpinski fractal is close related to the Pascal matrix. Data structures based on the Sierpinski triangle have been successfully used to solve special problems in switching theory. Some of them will be addressed in the paper.
{"title":"The Pascal Triangle (1654), the Reed-Muller-Fourier Transform (1992), and the Discrete Pascal Transform (2005)","authors":"C. Moraga, R. Stankovic, M. Stankovic","doi":"10.1109/ISMVL.2016.24","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.24","url":null,"abstract":"This paper makes a theoretical comparative analysis of the Reed-Muller-Fourier Transform, Pascal matrices based on the Pascal triangle, and the Discrete Pascal Transform. The Reed-Muller-Fourier Transform was not originated by a Pascal matrix, however it happens to show a strong family resemblance with it, sharing several basic properties. Its area of application is the multiple-valued switching theory, mainly to obtain polynomial expressions from the value vector of multiple-valued functions. The Discrete Pascal Transform was introduced over a decade later, based on an ad hoc modification of a Pascal matrix, for applications on picture processing. It is however shown that a Discrete Pascal Transform of size p, taken modulo p equals the special Reed-Muller-Fourier Transform for the same p and n = 1. The Sierpinski fractal is close related to the Pascal matrix. Data structures based on the Sierpinski triangle have been successfully used to solve special problems in switching theory. Some of them will be addressed in the paper.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128914984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Motivated by its variety of applications in several (emerging) technologies, the design of reversible circuits received significant attention in the recent past. With the emergence of physical realizations, also the consideration of faults and fault-tolerance became important. It has been suggested that parity preserving circuits would be ideal for fault detection, since here the parity of the inputs is the same as the parity of the outputs. Hence, if there is a fault on any single output, the parity should be flipped which would make the fault easy to detect. This paper however shows that this is not always the case. In fact, we provide and discuss examples showing that it is not sufficient to have parity preserving circuits when considering established fault models for reversible logic. As a result of our investigations, we can conclude that, even if a reversible circuit is parity preserving, it has to be checked against a particular fault model.
{"title":"Fault Detection in Parity Preserving Reversible Circuits","authors":"Nils Przigoda, G. Dueck, R. Wille, R. Drechsler","doi":"10.1109/ISMVL.2016.44","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.44","url":null,"abstract":"Motivated by its variety of applications in several (emerging) technologies, the design of reversible circuits received significant attention in the recent past. With the emergence of physical realizations, also the consideration of faults and fault-tolerance became important. It has been suggested that parity preserving circuits would be ideal for fault detection, since here the parity of the inputs is the same as the parity of the outputs. Hence, if there is a fault on any single output, the parity should be flipped which would make the fault easy to detect. This paper however shows that this is not always the case. In fact, we provide and discuss examples showing that it is not sufficient to have parity preserving circuits when considering established fault models for reversible logic. As a result of our investigations, we can conclude that, even if a reversible circuit is parity preserving, it has to be checked against a particular fault model.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130845605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Debabani Chowdhury, D. K. Das, B. Bhattacharya, Tsutomu Sasao
There exists a class of Boolean functions, called root-functions, which can never appear as faulty response in irredundant two-level-AND-OR combinational circuits even when any arbitrary multiple stuck-at faults are injected. However, for multi-valued logic circuits, root-functions are not yet well understood. In this work, we characterize some of the multiple-valued root-functions in the context of irredundant two-level AND-OR multiple-valued circuit realizations. As in the case of binary logic, such a function can never appear as a faulty-function in the presence of any stuck-at fault. We present here a preliminary study on multiple-valued root-functions for ternary (3-valued) logic circuits, and identify a class of n-variable ternary root-functions using a recursive method called concatenation. Such an approach provides a generalized mechanism for identifying a class of root-functions for other p-valued(p > 3), n-variable, two-level AND-OR logic circuits. Furthermore, we establish an important connection between root-functions and the classical latin-square functions.
{"title":"On the Inadmissible Class of Multiple-Valued Faulty-Functions under Stuck-at Faults","authors":"Debabani Chowdhury, D. K. Das, B. Bhattacharya, Tsutomu Sasao","doi":"10.1109/ISMVL.2016.55","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.55","url":null,"abstract":"There exists a class of Boolean functions, called root-functions, which can never appear as faulty response in irredundant two-level-AND-OR combinational circuits even when any arbitrary multiple stuck-at faults are injected. However, for multi-valued logic circuits, root-functions are not yet well understood. In this work, we characterize some of the multiple-valued root-functions in the context of irredundant two-level AND-OR multiple-valued circuit realizations. As in the case of binary logic, such a function can never appear as a faulty-function in the presence of any stuck-at fault. We present here a preliminary study on multiple-valued root-functions for ternary (3-valued) logic circuits, and identify a class of n-variable ternary root-functions using a recursive method called concatenation. Such an approach provides a generalized mechanism for identifying a class of root-functions for other p-valued(p > 3), n-variable, two-level AND-OR logic circuits. Furthermore, we establish an important connection between root-functions and the classical latin-square functions.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124330726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An error correction scheme utilizing a brain-inspired learning algorithm, called Recurrent Neural Network (RNN), is proposed for resilient and efficient intra-chip data transmission. RNN has a feature to find partially-clustered time-series data stream from an input data stream and predict the next input data from previous input data stream, which can be utilized for realizing an error correction corresponding to the "context" of the data stream. Through the evaluation of intra-chip data transmission in a general-purpose 32-bit microprocessor, it is demonstrated that the proposed scheme performs 95.9% error reduction with 2-times better data transfer efficiency and 94.2% error reduction with 4-times better data transfer efficiency compared with a conventional error correction scheme.
{"title":"Context-Based Error Correction Scheme Using Recurrent Neural Network for Resilient and Efficient Intra-Chip Data Transmission","authors":"Naoto Sugaya, M. Natsui, T. Hanyu","doi":"10.1109/ISMVL.2016.42","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.42","url":null,"abstract":"An error correction scheme utilizing a brain-inspired learning algorithm, called Recurrent Neural Network (RNN), is proposed for resilient and efficient intra-chip data transmission. RNN has a feature to find partially-clustered time-series data stream from an input data stream and predict the next input data from previous input data stream, which can be utilized for realizing an error correction corresponding to the \"context\" of the data stream. Through the evaluation of intra-chip data transmission in a general-purpose 32-bit microprocessor, it is demonstrated that the proposed scheme performs 95.9% error reduction with 2-times better data transfer efficiency and 94.2% error reduction with 4-times better data transfer efficiency compared with a conventional error correction scheme.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124369474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, novel Instrumentation Amplifier (IA) architectures for biological signal processing are proposed. The proposed IA architectures consist of Fully Balanced Differential Difference Amplifier (FBDDA) and Differential Difference Amplifier (DDA). These were evaluated by using HSPICE simulation with 1P 2M 0.6-μm CMOS process. From the simulation results, we could confirm that average CMRR of the second proposed IA architecture was much higher than that of conventional one andwas 169.5 dB. Furthermore, the offset voltage could be reducedby using chopper stabilization technique.
{"title":"Novel Instrumentation Amplifier Architectures Insensitive to Resistor Mismatches and Offset Voltage for Biological Signal Processing","authors":"Zainul Abidin, K. Tanno, Shota Mago, H. Tamura","doi":"10.1109/ISMVL.2016.46","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.46","url":null,"abstract":"In this paper, novel Instrumentation Amplifier (IA) architectures for biological signal processing are proposed. The proposed IA architectures consist of Fully Balanced Differential Difference Amplifier (FBDDA) and Differential Difference Amplifier (DDA). These were evaluated by using HSPICE simulation with 1P 2M 0.6-μm CMOS process. From the simulation results, we could confirm that average CMRR of the second proposed IA architecture was much higher than that of conventional one andwas 169.5 dB. Furthermore, the offset voltage could be reducedby using chopper stabilization technique.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133143143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We consider properties of local and of perfect residuated lattices in terms of filters and give characterization theorems of these residuated lattices. Moreover, we show that, for a perfect residuated lattice X, a set D(X) of elements with infinite order is a normal, maximal and Boolean filter. This implies that the quotient algebra X/D(X) is the two element Boolean algebra {0,1}.
{"title":"Simple Characterizations of Perfect Residuated Lattices","authors":"M. Kondo","doi":"10.1109/ISMVL.2016.28","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.28","url":null,"abstract":"We consider properties of local and of perfect residuated lattices in terms of filters and give characterization theorems of these residuated lattices. Moreover, we show that, for a perfect residuated lattice X, a set D(X) of elements with infinite order is a normal, maximal and Boolean filter. This implies that the quotient algebra X/D(X) is the two element Boolean algebra {0,1}.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130178959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes a heuristic for linear decomposition of index generation functions using a balanced decision tree. The proposed heuristic finds a good linear decomposition of an index generation function by recursively dividing aset of its function values into two balanced subsets. Since the proposed heuristic is fast and requires a small amount of memory, it is applicable even to large index generation functions that cannot be solved in a reasonable time by existing heuristics. This paper shows time and space complexities of the proposed heuristic, and experimental results using some large examples to show its efficiency.
{"title":"An Efficient Heuristic for Linear Decomposition of Index Generation Functions","authors":"Shinobu Nagayama, Tsutomu Sasao, J. T. Butler","doi":"10.1109/ISMVL.2016.52","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.52","url":null,"abstract":"This paper proposes a heuristic for linear decomposition of index generation functions using a balanced decision tree. The proposed heuristic finds a good linear decomposition of an index generation function by recursively dividing aset of its function values into two balanced subsets. Since the proposed heuristic is fast and requires a small amount of memory, it is applicable even to large index generation functions that cannot be solved in a reasonable time by existing heuristics. This paper shows time and space complexities of the proposed heuristic, and experimental results using some large examples to show its efficiency.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127135406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The rapid advances of quantum technologies are opening up new challenges, of which, protecting quantum states from errors is a major one. Among quantum error correction schemes, the surface code is emerging as a natural choice with high-fidelity quantum gates reported for experimental platforms. Surface codes also necessitate the quantum gates to be formed with strict nearest neighbour coupling. State-of-the-art-reversible logic synthesis techniques for quantum circuit implementation do not ensure the logic gates to be formed in a nearest neighbor fashion, and this is handled as a post processing optimization by the insertion of swap gates. In this paper, we propose, for the first time, the inclusion of nearest neighbourhood criteria in a widely used ancilla free reversible logic synthesis method. Experimental results show that this method easily outperforms the earlier two step techniques in terms of gate count without any runtime overhead.
{"title":"Integrated Synthesis of Linear Nearest Neighbor Ancilla-Free MCT Circuits","authors":"M. Rahman, G. Dueck, A. Chattopadhyay, R. Wille","doi":"10.1109/ISMVL.2016.54","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.54","url":null,"abstract":"The rapid advances of quantum technologies are opening up new challenges, of which, protecting quantum states from errors is a major one. Among quantum error correction schemes, the surface code is emerging as a natural choice with high-fidelity quantum gates reported for experimental platforms. Surface codes also necessitate the quantum gates to be formed with strict nearest neighbour coupling. State-of-the-art-reversible logic synthesis techniques for quantum circuit implementation do not ensure the logic gates to be formed in a nearest neighbor fashion, and this is handled as a post processing optimization by the insertion of swap gates. In this paper, we propose, for the first time, the inclusion of nearest neighbourhood criteria in a widely used ancilla free reversible logic synthesis method. Experimental results show that this method easily outperforms the earlier two step techniques in terms of gate count without any runtime overhead.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133399121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Our society becomes increasingly dependent on wireless communications. The tremendous growth in the number and type of wirelessly connected devices in a combination with the dropping cost for performing cyberattacks create new challenges for assuring security of services and applications provided by the next generation of wireless communication networks. The situation is complicated even further by the fact that many end-point Internet of Things (IoT) devices have very limited resources for implementing security functionality. This paper addresses one of the aspects of this important, many-faceted problem - the design of hardware-efficient cryptographic primitives suitable for the protection of resource-constrained IoT devices. We focus on cryptographic primitives based on the invertible mappings of type {0,1,,2n-1} → {0,1,,2n-1}. In order to check if a given mapping is invertible or not, we generally need an exponential in n number of steps. In this paper, we derive a sufficient condition for invertibility which can be checked in O(n2N) time, where N is the size of representation of the largest function in the mapping. Our results can be used for constructing cryptographically secure invertible mappings which can be efficiently implemented in hardware.
{"title":"On Constructing Secure and Hardware-Efficient Invertible Mappings","authors":"E. Dubrova","doi":"10.1109/ISMVL.2016.15","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.15","url":null,"abstract":"Our society becomes increasingly dependent on wireless communications. The tremendous growth in the number and type of wirelessly connected devices in a combination with the dropping cost for performing cyberattacks create new challenges for assuring security of services and applications provided by the next generation of wireless communication networks. The situation is complicated even further by the fact that many end-point Internet of Things (IoT) devices have very limited resources for implementing security functionality. This paper addresses one of the aspects of this important, many-faceted problem - the design of hardware-efficient cryptographic primitives suitable for the protection of resource-constrained IoT devices. We focus on cryptographic primitives based on the invertible mappings of type {0,1,,2n-1} → {0,1,,2n-1}. In order to check if a given mapping is invertible or not, we generally need an exponential in n number of steps. In this paper, we derive a sufficient condition for invertibility which can be checked in O(n2N) time, where N is the size of representation of the largest function in the mapping. Our results can be used for constructing cryptographically secure invertible mappings which can be efficiently implemented in hardware.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132661125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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