S. Koshita, N. Onizawa, M. Abe, T. Hanyu, M. Kawamata
Recently, some attempts have been made to apply stochastic computation to realization of Finite Impulse Response (FIR) digital filters. Such new FIR filter realizations lead to significant reduction of hardware complexity over the conventional filter realizations based on binary computation. However, the stochastic FIR filters suffer from lower computational accuracy than the FIR filters based on binary computation. This paper presents a new method for realization of stochastic FIR filters to improve computational accuracy. In the proposed method, multipliers are realized using stochastic computation but adders are realized using binary computation. Evaluation results demonstrate that our method achieves a 7dB improvement in stopband attenuation.
{"title":"Realization of FIR Digital Filters Based on Stochastic/Binary Hybrid Computation","authors":"S. Koshita, N. Onizawa, M. Abe, T. Hanyu, M. Kawamata","doi":"10.1109/ISMVL.2016.40","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.40","url":null,"abstract":"Recently, some attempts have been made to apply stochastic computation to realization of Finite Impulse Response (FIR) digital filters. Such new FIR filter realizations lead to significant reduction of hardware complexity over the conventional filter realizations based on binary computation. However, the stochastic FIR filters suffer from lower computational accuracy than the FIR filters based on binary computation. This paper presents a new method for realization of stochastic FIR filters to improve computational accuracy. In the proposed method, multipliers are realized using stochastic computation but adders are realized using binary computation. Evaluation results demonstrate that our method achieves a 7dB improvement in stopband attenuation.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117071541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a cut-free Gentzen-type sequent calculus RBL for a restricted version of bi-intuitionistic logic is introduced as an alternative to a non-cut-free Gentzen-type sequent calculus BL for bi-intuitionistic logic. RBL is obtained from BL by imposing some restrictions to the implication-right and co-implication-left rules. RBL is a conservative extension of some Gentzen-type sequent calculi for intuitionistic and dual-intuitionistic logics. Syntactic dualities of RBL and its subsystems are also shown. Moreover, a Gentzen-type sequent calculus RBCL for a restricted version of bi-intuitionistic connexive logic, which is regarded as a variant of paraconsistent four-valued logics, is obtained from RBL by adding some initial sequents and logical inference rules for a paraconsistent negation connective. The cut-elimination theorem for RBCL is also proved using a theorem for embedding RBCL into RBL.
{"title":"Cut-Free Systems for Restricted Bi-Intuitionistic Logic and Its Connexive Extension","authors":"N. Kamide","doi":"10.1109/ISMVL.2016.11","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.11","url":null,"abstract":"In this paper, a cut-free Gentzen-type sequent calculus RBL for a restricted version of bi-intuitionistic logic is introduced as an alternative to a non-cut-free Gentzen-type sequent calculus BL for bi-intuitionistic logic. RBL is obtained from BL by imposing some restrictions to the implication-right and co-implication-left rules. RBL is a conservative extension of some Gentzen-type sequent calculi for intuitionistic and dual-intuitionistic logics. Syntactic dualities of RBL and its subsystems are also shown. Moreover, a Gentzen-type sequent calculus RBCL for a restricted version of bi-intuitionistic connexive logic, which is regarded as a variant of paraconsistent four-valued logics, is obtained from RBL by adding some initial sequents and logical inference rules for a paraconsistent negation connective. The cut-elimination theorem for RBCL is also proved using a theorem for embedding RBCL into RBL.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117003325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
For pure three-qubit states the classification of entanglement is both non-trivial and well understood. In this work, we study the quantum algorithmic complexity introduced in [1] of three-qubit pure states belonging to the most general class of entanglement. Contrary to expectations we find out that the degree of entanglement of states in this class quantified by the measure of 3-tangle, does not correlate with the quantum algorithmic complexity, defined as the length of the shortest circuit needed to prepare the state. For a given entangled state the evaluation of its quantum complexity is done via a pseudo random evolutionary algorithm. This algorithm allows us not only to determine the complexity of a quantum circuit in terms of the number of required quantum gates, but also to estimate another type of complexity related to the time required to obtain the correct answer.
{"title":"Quantum Algorithmic Complexity of Three-Qubit Pure States","authors":"M. Lukac, A. Mandilara","doi":"10.1109/ISMVL.2016.37","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.37","url":null,"abstract":"For pure three-qubit states the classification of entanglement is both non-trivial and well understood. In this work, we study the quantum algorithmic complexity introduced in [1] of three-qubit pure states belonging to the most general class of entanglement. Contrary to expectations we find out that the degree of entanglement of states in this class quantified by the measure of 3-tangle, does not correlate with the quantum algorithmic complexity, defined as the length of the shortest circuit needed to prepare the state. For a given entangled state the evaluation of its quantum complexity is done via a pseudo random evolutionary algorithm. This algorithm allows us not only to determine the complexity of a quantum circuit in terms of the number of required quantum gates, but also to estimate another type of complexity related to the time required to obtain the correct answer.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127418965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Many problems can be described by the question: Is there an assignment of values to given variables that satisfies certain conditions? Such problems are called satisfiability problems (SAT-problems). The values of the variables are usually encodedby Boolean values, and the conditions are transformed into a single expression consisting of conjunctions (C) of disjunctions(D) of Boolean variables. Due to this structure of the Boolean expression these satisfiability problems are more precisely calledCD-SAT-problems. Due to the wide field of applications and the simple unique representation, universal SAT-solvers were developed and stronglyimproved over the decades [2]. It is possible to solve CDSAT-problems of a few hundred Boolean variables and severalthousand disjunctions. The necessary Boolean encoding of binary variables restricts the application of CD-SAT-solvers for multivalued problems to a relatively small number of multi-valued variables and a small size of their domains. Therefore, wedeveloped a multi-valued problem solver that allows the solution for conjunctions (C) of disjunctions (D) of multi-valued variablesin the expression to be solved, we call it MV-CD-SAT-solver. A drawback of the required specification of a CD-SAT-problemis the distribution of knowledge about the problem over a large number of disjunctions (clauses). Some problems to be solved canbe specified more compactly by a conjunction (C) of disjunctions (D) of conjunctions (C). We utilized this possibility in an MVCDC-SAT-solver. Our experimental results confirm the benefits of this approach for the solution of multi-valued problems.
许多问题都可以用这个问题来描述:是否存在满足某些条件的给定变量的赋值?这样的问题被称为可满足性问题(SAT-problems)。变量的值通常由布尔值编码，并将条件转换为由布尔变量的连词(C)或断词(D)组成的单个表达式。由于布尔表达式的这种结构，这些可满足性问题更准确地称为cd - sat问题。由于广泛的应用领域和简单独特的表示，通用sat求解器在过去的几十年里得到了发展和大力改进[2]。有可能解决cdsat的几百个布尔变量和几千个析取的问题。二进制变量的布尔编码限制了多值问题的cd - sat解算器的应用，使其只适用于相对较少的多值变量及其域。因此，我们开发了一个多值问题求解器，它允许求解表达式中多值变量的析取(D)的连词(C)，我们称之为mv - cd - sat -求解器。cd - sat问题的要求说明的一个缺点是，关于问题的知识分布在大量的断语(从句)上。一些待解决的问题可以通过连词(C)的析取(D)来更紧凑地指定。我们在mvcdc - sat -求解器中利用了这种可能性。实验结果证实了该方法在求解多值问题中的优越性。
{"title":"Multi-valued Problem Solvers","authors":"B. Steinbach, S. Heinrich, C. Posthoff","doi":"10.1109/ISMVL.2016.16","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.16","url":null,"abstract":"Many problems can be described by the question: Is there an assignment of values to given variables that satisfies certain conditions? Such problems are called satisfiability problems (SAT-problems). The values of the variables are usually encodedby Boolean values, and the conditions are transformed into a single expression consisting of conjunctions (C) of disjunctions(D) of Boolean variables. Due to this structure of the Boolean expression these satisfiability problems are more precisely calledCD-SAT-problems. Due to the wide field of applications and the simple unique representation, universal SAT-solvers were developed and stronglyimproved over the decades [2]. It is possible to solve CDSAT-problems of a few hundred Boolean variables and severalthousand disjunctions. The necessary Boolean encoding of binary variables restricts the application of CD-SAT-solvers for multivalued problems to a relatively small number of multi-valued variables and a small size of their domains. Therefore, wedeveloped a multi-valued problem solver that allows the solution for conjunctions (C) of disjunctions (D) of multi-valued variablesin the expression to be solved, we call it MV-CD-SAT-solver. A drawback of the required specification of a CD-SAT-problemis the distribution of knowledge about the problem over a large number of disjunctions (clauses). Some problems to be solved canbe specified more compactly by a conjunction (C) of disjunctions (D) of conjunctions (C). We utilized this possibility in an MVCDC-SAT-solver. Our experimental results confirm the benefits of this approach for the solution of multi-valued problems.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"361 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115892038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In multiplication, partial products must first be generated by single-digit multipliers. Then, a parallel addition technique is required to add them. Both steps are addressed in this paper by proposing novel current-mode circuits in ternary logic. All of the designs are simulated by HSPICE and 32nm CNTFET. Moreover, the second step of multiplication is completely demonstrated in this paper for multiplying two five-digit ternary numbers. The method is based on the ability of linear addition in current-mode logic and redundant number sets. The ternary model is compared with a comparable binary structure. The findings of this paper show that the proposed ternary multiplier has 629 fewer transistors, and it also operates approximately 40% faster than the binary counterpart.
{"title":"Ternary Versus Binary Multiplication with Current-Mode CNTFET-Based K-Valued Converters","authors":"M. Moradi, R. F. Mirzaee, K. Navi","doi":"10.1109/ISMVL.2016.19","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.19","url":null,"abstract":"In multiplication, partial products must first be generated by single-digit multipliers. Then, a parallel addition technique is required to add them. Both steps are addressed in this paper by proposing novel current-mode circuits in ternary logic. All of the designs are simulated by HSPICE and 32nm CNTFET. Moreover, the second step of multiplication is completely demonstrated in this paper for multiplying two five-digit ternary numbers. The method is based on the ability of linear addition in current-mode logic and redundant number sets. The ternary model is compared with a comparable binary structure. The findings of this paper show that the proposed ternary multiplier has 629 fewer transistors, and it also operates approximately 40% faster than the binary counterpart.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116523312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The data rate of VLSI system interconnections has been increasing in response to the demand for high-speed interfaces. At high-speed data rates, achieving data transmission without bit errors is difficult because of intersymbol interference (ISI). We have proposed high-speed data communication techniques for VLSI systems using Tomlinson-Harashima precoding (THP). Because THP can eliminate ISI by inverting the characteristics of channels with limited peak power at the transmitter, it is suitable for implementing advanced low-voltage, high-speed VLSI systems. In this study, to further improve the THP performance, a novel double-rate THP equalization technique designed especially for multi-valued data transmission is presented. Simulation and measurement results show that the proposed THP equalization with a double sampling rate can enhance the transition time of data and hence improve the eye opening.
{"title":"Double-Rate Equalization Using Tomlinson-Harashima Precoding for Multi-valued Data Transmission","authors":"Yosuke Iijima, Y. Yuminaka","doi":"10.1109/ISMVL.2016.27","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.27","url":null,"abstract":"The data rate of VLSI system interconnections has been increasing in response to the demand for high-speed interfaces. At high-speed data rates, achieving data transmission without bit errors is difficult because of intersymbol interference (ISI). We have proposed high-speed data communication techniques for VLSI systems using Tomlinson-Harashima precoding (THP). Because THP can eliminate ISI by inverting the characteristics of channels with limited peak power at the transmitter, it is suitable for implementing advanced low-voltage, high-speed VLSI systems. In this study, to further improve the THP performance, a novel double-rate THP equalization technique designed especially for multi-valued data transmission is presented. Simulation and measurement results show that the proposed THP equalization with a double sampling rate can enhance the transition time of data and hence improve the eye opening.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123898287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An energy-efficient and highly-reliable nonvolatile FPGA using a self-terminated power-gating scheme is proposed. Since the write current is automatically cut off just after the temporal data in the flip-flop is successfully backed up in the nonvolatile device, the amount of write energy can be minimized with no write failure. Moreover, when the backup operation in a particular logic cluster is completed, power supply of the cluster is immediately turned off, which minimizes standby energy due to leakage current. In fact, the total amount of energy consumption during the backup operation is reduced by 64% in comparison with that of a conventional worst-case based approach where the long time write current pulse is used for the reliable write.
{"title":"Energy-Efficient and Highly-Reliable Nonvolatile FPGA Using Self-Terminated Power-Gating Scheme","authors":"D. Suzuki, T. Hanyu","doi":"10.1109/ISMVL.2016.50","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.50","url":null,"abstract":"An energy-efficient and highly-reliable nonvolatile FPGA using a self-terminated power-gating scheme is proposed. Since the write current is automatically cut off just after the temporal data in the flip-flop is successfully backed up in the nonvolatile device, the amount of write energy can be minimized with no write failure. Moreover, when the backup operation in a particular logic cluster is completed, power supply of the cluster is immediately turned off, which minimizes standby energy due to leakage current. In fact, the total amount of energy consumption during the backup operation is reduced by 64% in comparison with that of a conventional worst-case based approach where the long time write current pulse is used for the reliable write.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"149 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122500452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper the models of reversible Toffoli and quantum Deutsch gates are extended to the p-valued domain. Their structural parameters are determined and their behavior is proven. Both conjunctive and disjunctive control strategies with positive and mixed polarities are introduced for the first time in a p-valued domain. The design is based on elementary Muthukrishnan-Stroud quantum gates, hence the realizability of the extended gates in the context of ion traps should be possible.
{"title":"Quantum p-Valued Toffoli and Deutsch Gates with Conjunctive or Disjunctive Mixed Polarity Control","authors":"C. Moraga","doi":"10.1109/ISMVL.2016.22","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.22","url":null,"abstract":"In this paper the models of reversible Toffoli and quantum Deutsch gates are extended to the p-valued domain. Their structural parameters are determined and their behavior is proven. Both conjunctive and disjunctive control strategies with positive and mixed polarities are introduced for the first time in a p-valued domain. The design is based on elementary Muthukrishnan-Stroud quantum gates, hence the realizability of the extended gates in the context of ion traps should be possible.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117297101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A new classical paraconsistent logic (CP), which is a variant of Nelson's paraconsistent four-valued logic, is introduced as a Gentzen-type sequent calculus. The logic CP can simulate the classical negation in classical logic by paraconsistent double negation in CP. Some theorems for syntactically and semantically embedding CP into a Gentzen-type sequent calculus LK for classical logic and vice versa are proved. The cut-elimination and completeness theorems for CP are also shown using these embedding theorems.
{"title":"Paraconsistent Double Negation That Can Simulate Classical Negation","authors":"N. Kamide","doi":"10.1109/ISMVL.2016.12","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.12","url":null,"abstract":"A new classical paraconsistent logic (CP), which is a variant of Nelson's paraconsistent four-valued logic, is introduced as a Gentzen-type sequent calculus. The logic CP can simulate the classical negation in classical logic by paraconsistent double negation in CP. Some theorems for syntactically and semantically embedding CP into a Gentzen-type sequent calculus LK for classical logic and vice versa are proved. The cut-elimination and completeness theorems for CP are also shown using these embedding theorems.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133189101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Biswal, Chandan Bandyopadhyay, A. Chattopadhyay, R. Wille, R. Drechsler, H. Rahaman
The quest of achieving higher computing performance is driving the research on quantum computing, which is reporting new milestones almost on a daily basis. For practical quantum circuit design, fault tolerance is an essential condition. This is achieved by mapping the target functions into the Clifford+T group of elementary quantum gates. Furthermore, the application of error-correcting codes in quantum circuits requires the quantum gates to be formed between adjacent Qubits. In this work, we improve the state-of-the-art quantum circuit design by addressing both of the above challenges. First, we propose a novel mapping of Multiple-Control Toffoli (MCT) gates to Clifford+T group gates, which achieves lower gate count compared to earlier work. Secondly, we show a generic way to convert any Clifford+T circuit into a nearest neighbor one. We validate the efficacy of our approach with detailed experimental studies.
{"title":"Nearest-Neighbor and Fault-Tolerant Quantum Circuit Implementation","authors":"L. Biswal, Chandan Bandyopadhyay, A. Chattopadhyay, R. Wille, R. Drechsler, H. Rahaman","doi":"10.1109/ISMVL.2016.48","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.48","url":null,"abstract":"The quest of achieving higher computing performance is driving the research on quantum computing, which is reporting new milestones almost on a daily basis. For practical quantum circuit design, fault tolerance is an essential condition. This is achieved by mapping the target functions into the Clifford+T group of elementary quantum gates. Furthermore, the application of error-correcting codes in quantum circuits requires the quantum gates to be formed between adjacent Qubits. In this work, we improve the state-of-the-art quantum circuit design by addressing both of the above challenges. First, we propose a novel mapping of Multiple-Control Toffoli (MCT) gates to Clifford+T group gates, which achieves lower gate count compared to earlier work. Secondly, we show a generic way to convert any Clifford+T circuit into a nearest neighbor one. We validate the efficacy of our approach with detailed experimental studies.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114796485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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