{"title":"Session details: Special Session: Bio Design Automation","authors":"Yu Wang","doi":"10.1145/3254022","DOIUrl":"https://doi.org/10.1145/3254022","url":null,"abstract":"","PeriodicalId":255133,"journal":{"name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","volume":"27 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120858068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Power consumption of main memory has become a critical concern and has led to proposals to employ emerging non-volatile memories (NVMs) to replace or augment DRAM. This paper proposes Space Oblivious COmpression (SOCO), an in-place lightweight compression mechanism particularly designed for reducing NVM-based main-memory energy rather than saving space. SOCO can significantly reduce the number of bits written to save considerable energy for NVM-based main memories. By relaxing the goal of a conventional compression, the proposed approach practically eliminates memory addressing and management overheads incurred by compression techniques designed to save space. Our experiments show that SOCO provides more than 50% reduction in bits written, resulting in 23% and 34% energy savings for Spin-transfer Torque (STT)-MRAM and Phase Change Memory (PCM), respectively.
{"title":"Space Oblivious Compression: Power Reduction for Non-Volatile Main Memories","authors":"Yong Li, Haifeng Xu, R. Melhem, A. Jones","doi":"10.1145/2742060.2742107","DOIUrl":"https://doi.org/10.1145/2742060.2742107","url":null,"abstract":"Power consumption of main memory has become a critical concern and has led to proposals to employ emerging non-volatile memories (NVMs) to replace or augment DRAM. This paper proposes Space Oblivious COmpression (SOCO), an in-place lightweight compression mechanism particularly designed for reducing NVM-based main-memory energy rather than saving space. SOCO can significantly reduce the number of bits written to save considerable energy for NVM-based main memories. By relaxing the goal of a conventional compression, the proposed approach practically eliminates memory addressing and management overheads incurred by compression techniques designed to save space. Our experiments show that SOCO provides more than 50% reduction in bits written, resulting in 23% and 34% energy savings for Spin-transfer Torque (STT)-MRAM and Phase Change Memory (PCM), respectively.","PeriodicalId":255133,"journal":{"name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115108690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Session details: CAD for New Technologies","authors":"C. Y. Chen","doi":"10.1145/3254007","DOIUrl":"https://doi.org/10.1145/3254007","url":null,"abstract":"","PeriodicalId":255133,"journal":{"name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","volume":"323 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124566470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Neurons encode many parameters simultaneously, but the encoding fidelity at the level of individual neurons is weak. In contrast, with a better understanding of neural population function we can now decode complex arm and hand movement. We have developed a simple extraction algorithm to capture arm movement data and shown that a paralyzed patient who cannot move any part of her body below her neck can control a high-performance "modular prosthetic limb" using 10 degrees-of-freedom simultaneously. The control of this artificial limb is intuitive, with coordinated, graceful motion, closely resembling natural arm and hand movement.
{"title":"Recent Advances in Brain-controlled Prosthetics for Paralysis: Friday Keynote","authors":"A. Schwartz","doi":"10.1145/2742060.2742124","DOIUrl":"https://doi.org/10.1145/2742060.2742124","url":null,"abstract":"Neurons encode many parameters simultaneously, but the encoding fidelity at the level of individual neurons is weak. In contrast, with a better understanding of neural population function we can now decode complex arm and hand movement. We have developed a simple extraction algorithm to capture arm movement data and shown that a paralyzed patient who cannot move any part of her body below her neck can control a high-performance \"modular prosthetic limb\" using 10 degrees-of-freedom simultaneously. The control of this artificial limb is intuitive, with coordinated, graceful motion, closely resembling natural arm and hand movement.","PeriodicalId":255133,"journal":{"name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131387567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Session details: Keynote III","authors":"Alex K. Jones","doi":"10.1145/3254009","DOIUrl":"https://doi.org/10.1145/3254009","url":null,"abstract":"","PeriodicalId":255133,"journal":{"name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","volume":"162 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123056281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Polar codes, as the new generation of channel codes, have potential applications in communication and storage systems. Successive-cancellation list (SCL) algorithm is the main decoding approach for improving the error-correcting performance of polar codes. Recently low-complexity SCL decoders in the log-likelihood-ratio (LLR) form were proposed to replace the original ones in the likelihood form. However, these LLR-based SCL decoders can only decode 1 bit in one cycle, which leads to very long latency. This paper, for the first time, presents a reduced-latency LLR-based SCL decoder. With the new decoding scheme that determines 2 bits simultaneously, the proposed (n, k) decoder reduces the entire decoding latency from 3n-2 to 3n-2 clock cycles with the same critical path delay as the prior LLR-based SCL decoders. As a result, the decoding throughput and hardware efficiency are increased by a factor of 1.5. In addition, compared to a prior reduced-latency non-LLR-based SCL decoder, the proposed work reduces the area by two times as well.
{"title":"Reduced-latency LLR-based SC List Decoder for Polar Codes","authors":"Bo Yuan, K. Parhi","doi":"10.1145/2742060.2742108","DOIUrl":"https://doi.org/10.1145/2742060.2742108","url":null,"abstract":"Polar codes, as the new generation of channel codes, have potential applications in communication and storage systems. Successive-cancellation list (SCL) algorithm is the main decoding approach for improving the error-correcting performance of polar codes. Recently low-complexity SCL decoders in the log-likelihood-ratio (LLR) form were proposed to replace the original ones in the likelihood form. However, these LLR-based SCL decoders can only decode 1 bit in one cycle, which leads to very long latency. This paper, for the first time, presents a reduced-latency LLR-based SCL decoder. With the new decoding scheme that determines 2 bits simultaneously, the proposed (n, k) decoder reduces the entire decoding latency from 3n-2 to 3n-2 clock cycles with the same critical path delay as the prior LLR-based SCL decoders. As a result, the decoding throughput and hardware efficiency are increased by a factor of 1.5. In addition, compared to a prior reduced-latency non-LLR-based SCL decoder, the proposed work reduces the area by two times as well.","PeriodicalId":255133,"journal":{"name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115143845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Session details: Poster Session 2","authors":"Matthias Fuegger","doi":"10.1145/3254013","DOIUrl":"https://doi.org/10.1145/3254013","url":null,"abstract":"","PeriodicalId":255133,"journal":{"name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115238759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Are fine arts and technology compatible partners" Do these disciplines support each other or flinch when they are combined like oil and water" Do collaborative efforts provide interesting insights and opportunities for students" For practitioners" There seems to be an explosion of interest in exploring arts and technology connections: new media, digital media, kinetic art, new frontiers, emergent media, interdisciplinary, multidisciplinary, and transdisciplinary are only some of the terms used to describe this fusion of disciplines. A visit to the SIGGRAPH art gallery or the SIGCHI Interactivity sessions, for example, will showcase a wide variety of uses of computing, embedded control, sensors, and actuators in the service of art. Kinetic art using embedded control is a marriage of art and technology. Artistic sensibility and creativity are required for concept and planning, and computer science and engineering skills are required to realize the artistic vision. However, these different skills are often taught in extremely different parts of a university campus. In this talk I will start with some thoughts on the nature of combining arts and technology, and show some historical and contemporary examples specifically relating to kinetic art. I will then describe an ongoing collaborative course that involves Computer Science and Art students working together to design and create computer-controlled kinetic art. Students in the course explore interfacing of embedded computer systems with sensors and actuators of all sorts. They also explore physical and conceptual aspects of machine-making as a fine-art sculpture process. Our goal is to enhance the educational experience of both groups of students. We believe that both student groups gain significant and unusual benefits that they can apply in a variety of ways in their respective disciplines.
{"title":"Computational Thinking Meets Design Thinking: Technology and Arts Collaborations","authors":"E. Brunvand","doi":"10.1145/2742060.2742123","DOIUrl":"https://doi.org/10.1145/2742060.2742123","url":null,"abstract":"Are fine arts and technology compatible partners\" Do these disciplines support each other or flinch when they are combined like oil and water\" Do collaborative efforts provide interesting insights and opportunities for students\" For practitioners\" There seems to be an explosion of interest in exploring arts and technology connections: new media, digital media, kinetic art, new frontiers, emergent media, interdisciplinary, multidisciplinary, and transdisciplinary are only some of the terms used to describe this fusion of disciplines. A visit to the SIGGRAPH art gallery or the SIGCHI Interactivity sessions, for example, will showcase a wide variety of uses of computing, embedded control, sensors, and actuators in the service of art. Kinetic art using embedded control is a marriage of art and technology. Artistic sensibility and creativity are required for concept and planning, and computer science and engineering skills are required to realize the artistic vision. However, these different skills are often taught in extremely different parts of a university campus. In this talk I will start with some thoughts on the nature of combining arts and technology, and show some historical and contemporary examples specifically relating to kinetic art. I will then describe an ongoing collaborative course that involves Computer Science and Art students working together to design and create computer-controlled kinetic art. Students in the course explore interfacing of embedded computer systems with sensors and actuators of all sorts. They also explore physical and conceptual aspects of machine-making as a fine-art sculpture process. Our goal is to enhance the educational experience of both groups of students. We believe that both student groups gain significant and unusual benefits that they can apply in a variety of ways in their respective disciplines.","PeriodicalId":255133,"journal":{"name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129322018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Fatemeh Tehranipoor, Nima Karimian, K. Xiao, J. Chandy
Physical Unclonable Functions (PUF) are the result of random uncontrollable variables in the manufacturing process. A PUF can be used as a source of random but reliable data for applications such as generating chip identification and encryption keys. Among various types of PUFs, an intrinsic PUF is the result of a preexisting manufacturing process, does not require any additional circuitry, and is cost effective. In this paper, we introduce an intrinsic PUF based on dynamic random access memories (DRAM). DRAM PUFs can be used in low cost identification applications and also have several advantages over other PUFs such as large input patterns. The DRAM PUF relies on the fact that the capacitor in the DRAM initializes to random values at startup. We demonstrate real DRAM PUFs and describe an experimental setup to test different operating conditions on three DRAMs to achieve the highest reliable results. Finally, we select the most stable bits to use as chip ID using our enrollment algorithm.
{"title":"DRAM based Intrinsic Physical Unclonable Functions for System Level Security","authors":"Fatemeh Tehranipoor, Nima Karimian, K. Xiao, J. Chandy","doi":"10.1145/2742060.2742069","DOIUrl":"https://doi.org/10.1145/2742060.2742069","url":null,"abstract":"Physical Unclonable Functions (PUF) are the result of random uncontrollable variables in the manufacturing process. A PUF can be used as a source of random but reliable data for applications such as generating chip identification and encryption keys. Among various types of PUFs, an intrinsic PUF is the result of a preexisting manufacturing process, does not require any additional circuitry, and is cost effective. In this paper, we introduce an intrinsic PUF based on dynamic random access memories (DRAM). DRAM PUFs can be used in low cost identification applications and also have several advantages over other PUFs such as large input patterns. The DRAM PUF relies on the fact that the capacitor in the DRAM initializes to random values at startup. We demonstrate real DRAM PUFs and describe an experimental setup to test different operating conditions on three DRAMs to achieve the highest reliable results. Finally, we select the most stable bits to use as chip ID using our enrollment algorithm.","PeriodicalId":255133,"journal":{"name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114988391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Three dimensional (3D) Network-on-Chip (NoC) architectures enable design of low power and high performance communication fabrics for multicore chips. In spite of achievable performance benefits, 3D NoCs are still bottlenecked by the planar interconnects. To exploit the benefits introduced by the vertical dimension, it is imperative to explore novel 3D NoC architectures. In this paper, we propose design of a small-world (SW) network based 3D NoCs. We demonstrate that the proposed 3D SW NoC outperforms its conventional 3D mesh-based counterparts. On average, it provides ~25% reduction in the energy delay product (EDP) compared to 3D MESH without introducing any additional link overhead in presence of conventional SPLASH-2 and PARSEC benchmarks. The proposed 3D SW NoC is more robust in presence of TSV failures and performs better than fault-free 3D MESH even in the presence of 25% TSVs failure.
{"title":"Small-World Network Enabled Energy Efficient and Robust 3D NoC Architectures","authors":"Sourav Das, Dongjin Lee, D. Kim, P. Pande","doi":"10.1145/2742060.2742085","DOIUrl":"https://doi.org/10.1145/2742060.2742085","url":null,"abstract":"Three dimensional (3D) Network-on-Chip (NoC) architectures enable design of low power and high performance communication fabrics for multicore chips. In spite of achievable performance benefits, 3D NoCs are still bottlenecked by the planar interconnects. To exploit the benefits introduced by the vertical dimension, it is imperative to explore novel 3D NoC architectures. In this paper, we propose design of a small-world (SW) network based 3D NoCs. We demonstrate that the proposed 3D SW NoC outperforms its conventional 3D mesh-based counterparts. On average, it provides ~25% reduction in the energy delay product (EDP) compared to 3D MESH without introducing any additional link overhead in presence of conventional SPLASH-2 and PARSEC benchmarks. The proposed 3D SW NoC is more robust in presence of TSV failures and performs better than fault-free 3D MESH even in the presence of 25% TSVs failure.","PeriodicalId":255133,"journal":{"name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","volume":"25 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114034438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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