Ali Akbari, S. Pour-Mozafari, Hamid Noori, Farhad Mehdipour
This paper presents a task priority scaling algorithm for dynamic thermal management of multi-core processors. The unique features of this algorithm include: 1) enabling task-level Dynamic Frequency Scaling (DFS) capability through software, 2) reducing task migration and provide load balancing using dynamic task priority scaling, 3) targeting DTM for systems with high workload. This algorithm is evaluated on a commercial quad-core processor. The experimental results indicate that the proposed approach can decrease the average and peak temperature by 9.73% and 7.1%, respectively, compared to Linux standard scheduler.
{"title":"Dynamic Task Priority Scaling for Thermal Management of Multi-core Processors with Heavy Workload","authors":"Ali Akbari, S. Pour-Mozafari, Hamid Noori, Farhad Mehdipour","doi":"10.1145/2742060.2742101","DOIUrl":"https://doi.org/10.1145/2742060.2742101","url":null,"abstract":"This paper presents a task priority scaling algorithm for dynamic thermal management of multi-core processors. The unique features of this algorithm include: 1) enabling task-level Dynamic Frequency Scaling (DFS) capability through software, 2) reducing task migration and provide load balancing using dynamic task priority scaling, 3) targeting DTM for systems with high workload. This algorithm is evaluated on a commercial quad-core processor. The experimental results indicate that the proposed approach can decrease the average and peak temperature by 9.73% and 7.1%, respectively, compared to Linux standard scheduler.","PeriodicalId":255133,"journal":{"name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121551979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The minimum voltage of operation (Vmin) for memory arrays often limits the lowest system operating voltage. This paper introduces a novel read assist topology for a domino-based evaluation architecture in a read only memory (ROM). The implementation incorporates an assist pull-down (PD) device, which activates during the evaluation phase in order to increase the effective pull-down strength of the bit cells. This implementation maintains Vmin without increasing the size of pull down devices inside the bit cells. The assist topology improves read delay by 11-30% and increases noise margin. Area overhead can be limited to 27% in a typical ROM.
{"title":"Optimizing VMIN of ROM Arrays Without Loss of Noise Margin","authors":"Avijit Chakraborty, D. Walker","doi":"10.1145/2742060.2742100","DOIUrl":"https://doi.org/10.1145/2742060.2742100","url":null,"abstract":"The minimum voltage of operation (Vmin) for memory arrays often limits the lowest system operating voltage. This paper introduces a novel read assist topology for a domino-based evaluation architecture in a read only memory (ROM). The implementation incorporates an assist pull-down (PD) device, which activates during the evaluation phase in order to increase the effective pull-down strength of the bit cells. This implementation maintains Vmin without increasing the size of pull down devices inside the bit cells. The assist topology improves read delay by 11-30% and increases noise margin. Area overhead can be limited to 27% in a typical ROM.","PeriodicalId":255133,"journal":{"name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121563701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Gate sizing is one of the most important techniques for circuit optimization. Over the years, Elmore delay model (EDM) has been the predominant timing model used in gate sizing due to its simplicity. However, EDM is no longer effective in meeting the increasing demand of timing accuracy. In this paper, we propose a new gate delay model, which characterizes the timing information of lookup tables and creates a model which is mathematically similar to EDM, and can be easily incorporated into well-known EDM based gate sizing techniques using Lagrangian Relaxation (LR) with minor modifications. Experimental data show that it can produce even better results than those directly based on lookup tables, while keeping the benefit of the simplicity of EDM.
{"title":"Lookup Table Based Discrete Gate Sizing for Delay Minimization with Modified Elmore Delay Model","authors":"Jiani Xie, C. Y. Chen","doi":"10.1145/2742060.2742094","DOIUrl":"https://doi.org/10.1145/2742060.2742094","url":null,"abstract":"Gate sizing is one of the most important techniques for circuit optimization. Over the years, Elmore delay model (EDM) has been the predominant timing model used in gate sizing due to its simplicity. However, EDM is no longer effective in meeting the increasing demand of timing accuracy. In this paper, we propose a new gate delay model, which characterizes the timing information of lookup tables and creates a model which is mathematically similar to EDM, and can be easily incorporated into well-known EDM based gate sizing techniques using Lagrangian Relaxation (LR) with minor modifications. Experimental data show that it can produce even better results than those directly based on lookup tables, while keeping the benefit of the simplicity of EDM.","PeriodicalId":255133,"journal":{"name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121114176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Stochastic computing (SC) employs conventional logic circuits to implement analog-style arithmetic functions acting on digital bit-streams. It exploits the advantages of analog computation -powerful basic operations, high operating speed, and error tolerance- in important applications such as sensory image processing and neuromorphic systems. At the same time, SC exhibits the analog drawbacks of low precision and complex underlying behavior. Although studied since the 1960s, many of SC"s fundamental properties are not well known or well understood. This paper presents, in a uniform manner and notation, what is known about the relations between the logical and stochastic behavior of stochastic circuits. It also considers how correlation among input bit-streams and the presence of memory elements influences stochastic behavior. Some related research challenges posed by SC are also discussed.
{"title":"On the Functions Realized by Stochastic Computing Circuits","authors":"Armin Alaghi, J. Hayes","doi":"10.1145/2742060.2743758","DOIUrl":"https://doi.org/10.1145/2742060.2743758","url":null,"abstract":"Stochastic computing (SC) employs conventional logic circuits to implement analog-style arithmetic functions acting on digital bit-streams. It exploits the advantages of analog computation -powerful basic operations, high operating speed, and error tolerance- in important applications such as sensory image processing and neuromorphic systems. At the same time, SC exhibits the analog drawbacks of low precision and complex underlying behavior. Although studied since the 1960s, many of SC\"s fundamental properties are not well known or well understood. This paper presents, in a uniform manner and notation, what is known about the relations between the logical and stochastic behavior of stochastic circuits. It also considers how correlation among input bit-streams and the presence of memory elements influences stochastic behavior. Some related research challenges posed by SC are also discussed.","PeriodicalId":255133,"journal":{"name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","volume":"170 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116124915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Unsupervised learning with sparse coding is widely adopted in applications of feature extraction, pattern classification, and compressive sensing. However, even with the state-of-the-art hardware platform of CPUs/GPUs, solving a sparse coding problem is still expensive in computation. In this paper, the resistive cross-point array architecture (CPA) is proposed to achieve on-chip acceleration of sparse coding, especially the matrix/vector operations that are intensively used in the algorithm. Learning and recognition experiments are conducted with the MNIST handwriting dataset. By co-optimizing the algorithm, architecture, circuit, and resistive synaptic devices, SPICE simulation at 65nm demonstrates that the CPA is able to accelerate sparse coding computation by more than 3800X, compared to software running on an 8-core CPU. Furthermore, this work investigates the technological limitations of a realistic resistive CPA, including reduced ON/OFF range of synaptic devices, nonlinearity in programming, spatial and temporal variations, and interconnect parasitics. The results illustrate both enormous opportunities and practical barriers of resistive CPA in real-time learning on a chip.
{"title":"On-chip Sparse Learning with Resistive Cross-point Array Architecture","authors":"Shimeng Yu, Yu Cao","doi":"10.1145/2742060.2743757","DOIUrl":"https://doi.org/10.1145/2742060.2743757","url":null,"abstract":"Unsupervised learning with sparse coding is widely adopted in applications of feature extraction, pattern classification, and compressive sensing. However, even with the state-of-the-art hardware platform of CPUs/GPUs, solving a sparse coding problem is still expensive in computation. In this paper, the resistive cross-point array architecture (CPA) is proposed to achieve on-chip acceleration of sparse coding, especially the matrix/vector operations that are intensively used in the algorithm. Learning and recognition experiments are conducted with the MNIST handwriting dataset. By co-optimizing the algorithm, architecture, circuit, and resistive synaptic devices, SPICE simulation at 65nm demonstrates that the CPA is able to accelerate sparse coding computation by more than 3800X, compared to software running on an 8-core CPU. Furthermore, this work investigates the technological limitations of a realistic resistive CPA, including reduced ON/OFF range of synaptic devices, nonlinearity in programming, spatial and temporal variations, and interconnect parasitics. The results illustrate both enormous opportunities and practical barriers of resistive CPA in real-time learning on a chip.","PeriodicalId":255133,"journal":{"name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116125890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes several approximate divider designs; two different levels of approximation (cell and array levels) are investigated for non-restoring division. Three approximate subtractor cells are proposed and designed for the basic subtraction; these cells mitigate accuracy in subtraction with other metrics, such as circuit complexity and power dissipation. At array level, by considering the exact cells, both replacement and truncation schemes are introduced for approximate array divider design. A comprehensive evaluation of approximation at both cell and divider level is pursued. Different circuit metrics including complexity and power dissipation are evaluated by HSPICE simulation. Mean error distance (MED), normalized error distance (NED) and MED-power product (MPP) are provided to substantiate the accuracy and power trade-off of inexact computing. Different applications in image processing are investigated by utilizing the proposed approximate arithmetic circuits.
{"title":"Design of Approximate Unsigned Integer Non-restoring Divider for Inexact Computing","authors":"Linbin Chen, Jie Han, Weiqiang Liu, F. Lombardi","doi":"10.1145/2742060.2742063","DOIUrl":"https://doi.org/10.1145/2742060.2742063","url":null,"abstract":"This paper proposes several approximate divider designs; two different levels of approximation (cell and array levels) are investigated for non-restoring division. Three approximate subtractor cells are proposed and designed for the basic subtraction; these cells mitigate accuracy in subtraction with other metrics, such as circuit complexity and power dissipation. At array level, by considering the exact cells, both replacement and truncation schemes are introduced for approximate array divider design. A comprehensive evaluation of approximation at both cell and divider level is pursued. Different circuit metrics including complexity and power dissipation are evaluated by HSPICE simulation. Mean error distance (MED), normalized error distance (NED) and MED-power product (MPP) are provided to substantiate the accuracy and power trade-off of inexact computing. Different applications in image processing are investigated by utilizing the proposed approximate arithmetic circuits.","PeriodicalId":255133,"journal":{"name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","volume":"549 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116513902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Qinsi Wang, Nataša Miškov-Živanov, C. Telmer, E. Clarke
In this work, we developed a methodology to analyze a bacteria model that mimics the stages through which bacteria change when phage therapy is applied. Due to the widespread misuse and overuse of antibiotics, drug resistant bacteria now pose significant risks to health, agriculture and the environment. Therefore, we were interested in an alternative to conventional antibiotics, a phage therapy. Our model was designed according to an experimental procedure to engineer a temperate phage, Lambda (λ), and then kill bacteria via light-activated production of superoxide. We applied formal analysis to our model and the results show that such an approach can speed up evaluation of the system, which would be impractical or possibly not even feasible to study in a wet lab.
{"title":"Formal Analysis Provides Parameters for Guiding Hyperoxidation in Bacteria using Phototoxic Proteins","authors":"Qinsi Wang, Nataša Miškov-Živanov, C. Telmer, E. Clarke","doi":"10.1145/2742060.2743762","DOIUrl":"https://doi.org/10.1145/2742060.2743762","url":null,"abstract":"In this work, we developed a methodology to analyze a bacteria model that mimics the stages through which bacteria change when phage therapy is applied. Due to the widespread misuse and overuse of antibiotics, drug resistant bacteria now pose significant risks to health, agriculture and the environment. Therefore, we were interested in an alternative to conventional antibiotics, a phage therapy. Our model was designed according to an experimental procedure to engineer a temperate phage, Lambda (λ), and then kill bacteria via light-activated production of superoxide. We applied formal analysis to our model and the results show that such an approach can speed up evaluation of the system, which would be impractical or possibly not even feasible to study in a wet lab.","PeriodicalId":255133,"journal":{"name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132129728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Memory design has radically changed in the last few years; the emergence of new technologies has further improved performance and the traditional separation of storage levels between Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM) is not viable as in the past. Recently, the embedded DRAM (eDRAM) has been proposed for cache utilization to improve density while attempting to retain high performance operations; this scheme is often referred as hybrid due to the utilization of different technologies in a memory. In this paper, a hybrid scheme is proposed by adding non-volatile features and related circuits to the SRAM/eDRAM; an Oxide Resistive Random Access Memory (RRAM) is utilized as non-volatile storage in the embedded memory circuit. Different memory cells are proposed in this manuscript; they are evaluated with respect to circuit-level figures of merit as related to operational features (read, write, static noise margin, power delay product) as well as tolerance to event upsets (critical charge) and variations. Extensive simulation results using nanometric PTMs are provided. It is shown that the proposed designs offer substantial improvements over previous hybrid cells as well as a conventional NAND Flash memory cell.
{"title":"Novel Designs of Embedded Hybrid Cells for High Performance Memory Circuits","authors":"F. Lombardi, Wei Wei, K. Namba","doi":"10.1145/2742060.2742103","DOIUrl":"https://doi.org/10.1145/2742060.2742103","url":null,"abstract":"Memory design has radically changed in the last few years; the emergence of new technologies has further improved performance and the traditional separation of storage levels between Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM) is not viable as in the past. Recently, the embedded DRAM (eDRAM) has been proposed for cache utilization to improve density while attempting to retain high performance operations; this scheme is often referred as hybrid due to the utilization of different technologies in a memory. In this paper, a hybrid scheme is proposed by adding non-volatile features and related circuits to the SRAM/eDRAM; an Oxide Resistive Random Access Memory (RRAM) is utilized as non-volatile storage in the embedded memory circuit. Different memory cells are proposed in this manuscript; they are evaluated with respect to circuit-level figures of merit as related to operational features (read, write, static noise margin, power delay product) as well as tolerance to event upsets (critical charge) and variations. Extensive simulation results using nanometric PTMs are provided. It is shown that the proposed designs offer substantial improvements over previous hybrid cells as well as a conventional NAND Flash memory cell.","PeriodicalId":255133,"journal":{"name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134068538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Welcome to the 25th edition of the Great Lakes Symposium on VLSI (GLSVLSI) 2015 held at the Pittsburgh Marriott City Center in Pittsburgh, Pennsylvania, USA. GLSVLSI is a premier venue for the dissemination of manuscripts of the highest quality in all areas related to VLSI, devices, and system-level design. The venue of this year's GLSVLSI is Pittsburgh, which continues GLSVLSI's meetings near noted bodies of water. Pittsburgh is the famous confluence of the Allegheny and Monongahela rivers to form the Ohio River. The Ohio River links with the Mississippi River to reach the Gulf of Mexico, and while not a "great lake", it is a great body of water. Pittsburgh is one of the US oldest cities due to its water passages and also boasts a wonderful geography rich with hiking, water sports, skiing, and many other outdoor activities. You will also find a rich cultural heritage here due to great gifts by philanthropist Andrew Carnegie and cultural treasures like Stephen Foster and Andy Warhol as well as a world class symphony orchestra, museums of art and natural history, and the U.S. National Aviary. We truly believe that Pittsburgh is a great location for a symposium on VLSI 2015 and you will enjoy the beautiful city as well as the program over the three days of this year's GLSVLSI activity. This year, GLSVLSI is co-located with the IEEE Computer Society Microelectronics Systems Education (MSE) conference. This brings another facet to the scope of the GLSVLSI meeting to include pedagogical innovations as well as research innovations in the area of VLSI and microsystems. Your full conference registration will entitle you to attend sessions at either GLSVLSI or MSE as your interests dictate. Moreover, this year's special theme for GLSVLSI is related to Biology and the cross overs between VLSI, CAD, and Biology. To support this theme, we have included several keynote talks from recognized experts in both biology and computing technologies. On Wednesday we will open the symposium with Krishnendu Chakrabarty, William H. Younger Distinguished Professor at Duke University who will speak about Digital Microfluidic Biochips. On Thursday, Lynn H. Matthias Professor Zhenqiang (Jack) Ma will talk about his work in bio-neural graphene sensors for in vivo imaging and optogenetics. Finally, Friday's keynote will host Dr. Andrew Schwartz, Professor of Neurobiology at the University of Pittsburgh, who will discuss recent advances in brain-controlled prosthetics for paralysis. Additionally, we have four terrific special sessions including sessions on BioEDA and Neuromorphic Computing that supplement our special theme. The speakers of each special session are internationally renowned experts and they will discuss the state-of-the-art progress in these emerging domains from multidisciplinary perspectives. As for the technical meeting, GLSVLSI 2015 was a resounding success: 148 papers were submitted, including authors from 34 different countries, of which 41 papers
欢迎参加在美国宾夕法尼亚州匹兹堡万豪城市中心举行的第25届超大规模集成电路大湖研讨会(GLSVLSI) 2015。GLSVLSI是传播与VLSI，设备和系统级设计相关的所有领域的最高质量手稿的首要场所。今年glslsi的会议地点在匹兹堡，glslsi的会议继续在著名的水体附近举行。匹兹堡是著名的阿勒格尼河和莫农加希拉河汇合处，形成俄亥俄河。俄亥俄河与密西西比河相连，汇入墨西哥湾，虽然不是一个“大湖”，但它是一个巨大的水体。匹兹堡是美国最古老的城市之一，因为它的水上通道，也拥有丰富的徒步旅行，水上运动，滑雪和许多其他户外活动的美妙地理。你还会发现这里有丰富的文化遗产，因为慈善家安德鲁·卡内基(Andrew Carnegie)的慷慨馈赠，还有斯蒂芬·福斯特(Stephen Foster)和安迪·沃霍尔(Andy Warhol)等文化瑰宝，还有世界级的交响乐团、艺术和自然历史博物馆，以及美国国家鸟舍(U.S. National Aviary)。我们坚信匹兹堡是举办2015年VLSI研讨会的绝佳地点，您将在为期三天的GLSVLSI活动中享受这座美丽的城市和项目。今年，GLSVLSI与IEEE计算机学会微电子系统教育(MSE)会议在同一地点举行。这为GLSVLSI会议的范围带来了另一个方面，包括教学创新以及VLSI和微系统领域的研究创新。您的完整会议注册将使您有权根据您的兴趣参加glslsi或MSE的会议。此外，今年glslsi的特别主题与生物学以及VLSI, CAD和生物学之间的交叉有关。为了支持这一主题，我们包括了几位来自生物学和计算技术领域的知名专家的主题演讲。周三，我们将与杜克大学William H. Younger杰出教授Krishnendu Chakrabarty一起开启研讨会，他将谈论数字微流控生物芯片。周四，Lynn H. Matthias教授马振强(Jack)将谈论他在生物神经石墨烯传感器方面的工作，用于体内成像和光遗传学。最后，周五的主题演讲将由匹兹堡大学神经生物学教授Andrew Schwartz博士主持，他将讨论脑控制瘫痪假肢的最新进展。此外，我们有四个非常棒的特别会议，包括生物eda和神经形态计算会议，以补充我们的特别主题。每个特别会议的演讲者都是国际知名专家，他们将从多学科的角度讨论这些新兴领域的最新进展。在技术会议方面，glslsi 2015取得了巨大的成功，共提交了148篇论文，包括来自34个不同国家的作者，其中41篇论文被采纳为研讨会口头报告全文(接受率为28%)。包括海报论文在内，共有60篇论文将被收录在研讨会论文集中。项目论文作者中，48%来自北美，23%来自亚洲，23%来自欧洲，2.5%来自非洲，2.5%来自南美，1%来自澳大利亚。最终的技术方案包括在11次口头会议上的21个长篇报告和20个简短报告，以及在两次海报会议上的19个海报。特别会议为专题讨论会的会议记录增加了另外14篇令人兴奋的论文。glslsi 2015将于2015年5月20日(周三)开幕，届时将有一系列令人兴奋的演讲者，就包括弹性和鲁棒性、CAD和电路的新方法、互连和片上网络以及节能系统在内的广泛问题发表演讲。第二天，除了继续讨论弹性和稳健性、CAD和VLSI设计挑战外，我们还将重点讨论新兴技术和后cmos VLSI。在第三天，我们专门讨论了电源和温度感知设计，伴随着CAD和电路轨道。GLSVLSI 2015的技术计划包括两个平行的轨道，以便在三天的研讨会期间进行更长时间的介绍和讨论。同时，MSE将提供第三个并行部分。总的来说，在技术项目中有10个常规会议，4个特别会议，2个海报会议，以及研讨会第一天的一个会议，“最佳论文奖”候选人将有机会展示他们的优秀作品。GLSVLSI 2015的社会项目包括今年的两个特别活动。第一场活动是周二晚上由匹兹堡大学主办的酒会。
{"title":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","authors":"A. Jones, Hai Helen Li, A. Coskun, M. Margala","doi":"10.1145/2742060","DOIUrl":"https://doi.org/10.1145/2742060","url":null,"abstract":"Welcome to the 25th edition of the Great Lakes Symposium on VLSI (GLSVLSI) 2015 held at the Pittsburgh Marriott City Center in Pittsburgh, Pennsylvania, USA. GLSVLSI is a premier venue for the dissemination of manuscripts of the highest quality in all areas related to VLSI, devices, and system-level design. The venue of this year's GLSVLSI is Pittsburgh, which continues GLSVLSI's meetings near noted bodies of water. Pittsburgh is the famous confluence of the Allegheny and Monongahela rivers to form the Ohio River. The Ohio River links with the Mississippi River to reach the Gulf of Mexico, and while not a \"great lake\", it is a great body of water. Pittsburgh is one of the US oldest cities due to its water passages and also boasts a wonderful geography rich with hiking, water sports, skiing, and many other outdoor activities. You will also find a rich cultural heritage here due to great gifts by philanthropist Andrew Carnegie and cultural treasures like Stephen Foster and Andy Warhol as well as a world class symphony orchestra, museums of art and natural history, and the U.S. National Aviary. We truly believe that Pittsburgh is a great location for a symposium on VLSI 2015 and you will enjoy the beautiful city as well as the program over the three days of this year's GLSVLSI activity. \u0000 \u0000This year, GLSVLSI is co-located with the IEEE Computer Society Microelectronics Systems Education (MSE) conference. This brings another facet to the scope of the GLSVLSI meeting to include pedagogical innovations as well as research innovations in the area of VLSI and microsystems. Your full conference registration will entitle you to attend sessions at either GLSVLSI or MSE as your interests dictate. \u0000 \u0000Moreover, this year's special theme for GLSVLSI is related to Biology and the cross overs between VLSI, CAD, and Biology. To support this theme, we have included several keynote talks from recognized experts in both biology and computing technologies. On Wednesday we will open the symposium with Krishnendu Chakrabarty, William H. Younger Distinguished Professor at Duke University who will speak about Digital Microfluidic Biochips. On Thursday, Lynn H. Matthias Professor Zhenqiang (Jack) Ma will talk about his work in bio-neural graphene sensors for in vivo imaging and optogenetics. Finally, Friday's keynote will host Dr. Andrew Schwartz, Professor of Neurobiology at the University of Pittsburgh, who will discuss recent advances in brain-controlled prosthetics for paralysis. Additionally, we have four terrific special sessions including sessions on BioEDA and Neuromorphic Computing that supplement our special theme. The speakers of each special session are internationally renowned experts and they will discuss the state-of-the-art progress in these emerging domains from multidisciplinary perspectives. \u0000 \u0000As for the technical meeting, GLSVLSI 2015 was a resounding success: 148 papers were submitted, including authors from 34 different countries, of which 41 papers ","PeriodicalId":255133,"journal":{"name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114609185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Session details: Poster Session 1","authors":"T. Moreshet","doi":"10.1145/3254016","DOIUrl":"https://doi.org/10.1145/3254016","url":null,"abstract":"","PeriodicalId":255133,"journal":{"name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126196935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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