Pub Date : 1994-06-21DOI: 10.1109/IWRSP.1994.315900
J. D. S. Babcock, A. Dollas
System design is typically done in VHDL to facilitate top-down design and to enable the mapping of a design to many implementations. Reusability of subsystems to date has largely been performed with libraries of synthesizable VHDL subsystems. This paper presents recommended extensions to VHDL to allow the VHDL designer to interact with nonsynthesizable subsystems while still designing in VHDL. The extended VHDL code is passed through a precompiler that outputs two standard VHDL files: a simulatable VHDL model of the system, and a synthesizable model of the design where subsystems are replaced by signals to the external hardware.<>
{"title":"Extended VHDL for the rapid prototyping of systems with synthesizable and nonsynthesizable subsystems","authors":"J. D. S. Babcock, A. Dollas","doi":"10.1109/IWRSP.1994.315900","DOIUrl":"https://doi.org/10.1109/IWRSP.1994.315900","url":null,"abstract":"System design is typically done in VHDL to facilitate top-down design and to enable the mapping of a design to many implementations. Reusability of subsystems to date has largely been performed with libraries of synthesizable VHDL subsystems. This paper presents recommended extensions to VHDL to allow the VHDL designer to interact with nonsynthesizable subsystems while still designing in VHDL. The extended VHDL code is passed through a precompiler that outputs two standard VHDL files: a simulatable VHDL model of the system, and a synthesizable model of the design where subsystems are replaced by signals to the external hardware.<<ETX>>","PeriodicalId":261113,"journal":{"name":"Proceedings of IEEE 5th International Workshop on Rapid System Prototyping","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124562424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-21DOI: 10.1109/IWRSP.1994.315893
L. Carro, A. Suzim
This paper describes some techniques currently under research to explore hardware-software tradeoffs during a system development. We show that the moving of SW operations to HW can be further improved if the source code is modified in order to increase the overall parallelism of the system. We then show the limits of this approach and a new RISC architecture under research to overcome this limitations.<>
{"title":"Algorithms and architectures to computational systems implementation","authors":"L. Carro, A. Suzim","doi":"10.1109/IWRSP.1994.315893","DOIUrl":"https://doi.org/10.1109/IWRSP.1994.315893","url":null,"abstract":"This paper describes some techniques currently under research to explore hardware-software tradeoffs during a system development. We show that the moving of SW operations to HW can be further improved if the source code is modified in order to increase the overall parallelism of the system. We then show the limits of this approach and a new RISC architecture under research to overcome this limitations.<<ETX>>","PeriodicalId":261113,"journal":{"name":"Proceedings of IEEE 5th International Workshop on Rapid System Prototyping","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125604323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-21DOI: 10.1109/IWRSP.1994.315906
C. S. Myers, P. Fiore, J. Letellier
This paper presents two case studies of the rapid development of military signal processors and a description of how the experiences learned on these programs are being leveraged into an ARPA/Tri-Service initiative. The two case studies emphasize end-to-end system simulation and the use of rapid prototyping tools and special hardware for rapid development. Rapid Prototyping of Application Specific Signal Processors, or RASSP, is an initiative to create a new process for the development of military signal processors. The objective of RASSP is to specify a process which both reduces the development time and the cost of military signal processing systems while improving their quality and their long term supportability. RASSP processors are meant to be incrementally upgradable over long development and life cycles. While RASSP represents a significantly harder problem than the two examples described here, the lessons learned in these examples are being incorporated in the RASSP approach.<>
{"title":"Rapid development of signal processors and the RASSP program","authors":"C. S. Myers, P. Fiore, J. Letellier","doi":"10.1109/IWRSP.1994.315906","DOIUrl":"https://doi.org/10.1109/IWRSP.1994.315906","url":null,"abstract":"This paper presents two case studies of the rapid development of military signal processors and a description of how the experiences learned on these programs are being leveraged into an ARPA/Tri-Service initiative. The two case studies emphasize end-to-end system simulation and the use of rapid prototyping tools and special hardware for rapid development. Rapid Prototyping of Application Specific Signal Processors, or RASSP, is an initiative to create a new process for the development of military signal processors. The objective of RASSP is to specify a process which both reduces the development time and the cost of military signal processing systems while improving their quality and their long term supportability. RASSP processors are meant to be incrementally upgradable over long development and life cycles. While RASSP represents a significantly harder problem than the two examples described here, the lessons learned in these examples are being incorporated in the RASSP approach.<<ETX>>","PeriodicalId":261113,"journal":{"name":"Proceedings of IEEE 5th International Workshop on Rapid System Prototyping","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130936407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-21DOI: 10.1109/IWRSP.1994.315913
R. Wieler, Zaifu Zhang, R. McLeod
Circuit emulation, using dynamically reconfigurable hardware is a high speed alternative to circuit simulation, especially for large and complex designs. Dynamic reconfiguration enhances the ability to efficiently analyze the test of combinational and sequential circuits by providing statistical information on fault grading, detectability, and signature analysis. We present a hardware emulation environment based on dynamically reconfigurable field programmable devices. For this work our main interests are in hardware acceleration of fault simulation in a built-in self-test environment and rapid prototyping of new BIST techniques.<>
{"title":"Using an FPGA based computer as a hardware emulator for built-in self-test structures","authors":"R. Wieler, Zaifu Zhang, R. McLeod","doi":"10.1109/IWRSP.1994.315913","DOIUrl":"https://doi.org/10.1109/IWRSP.1994.315913","url":null,"abstract":"Circuit emulation, using dynamically reconfigurable hardware is a high speed alternative to circuit simulation, especially for large and complex designs. Dynamic reconfiguration enhances the ability to efficiently analyze the test of combinational and sequential circuits by providing statistical information on fault grading, detectability, and signature analysis. We present a hardware emulation environment based on dynamically reconfigurable field programmable devices. For this work our main interests are in hardware acceleration of fault simulation in a built-in self-test environment and rapid prototyping of new BIST techniques.<<ETX>>","PeriodicalId":261113,"journal":{"name":"Proceedings of IEEE 5th International Workshop on Rapid System Prototyping","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130814608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-21DOI: 10.1109/IWRSP.1994.315914
M. Engels, T. Meng
We describe the rapid prototyping of a video encoder intended for transmitting compressed video data through a wireless local area network. Our work proves the feasibility of using a multiprocessor for prototyping high-data rate applications with a minimum development effort.<>
{"title":"Rapid prototyping of a real-time video encoder","authors":"M. Engels, T. Meng","doi":"10.1109/IWRSP.1994.315914","DOIUrl":"https://doi.org/10.1109/IWRSP.1994.315914","url":null,"abstract":"We describe the rapid prototyping of a video encoder intended for transmitting compressed video data through a wireless local area network. Our work proves the feasibility of using a multiprocessor for prototyping high-data rate applications with a minimum development effort.<<ETX>>","PeriodicalId":261113,"journal":{"name":"Proceedings of IEEE 5th International Workshop on Rapid System Prototyping","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129442367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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