Pub Date : 1994-06-21DOI: 10.1109/IWRSP.1994.315909
W. Kaim, F. Kordon
Rapid prototyping of parallel systems is of interest to quickly produce a parallel prototype. The emergence of distributed systems technology has enabled one to develop software systems distributed over large networks. Rapid prototyping must deal with real parallelism over a set of processors, either closely or loosely coupled. We describe an extension of the CPN/TAGADA project to manage distributed code generation over a set of CPU. To achieve a mapping of components over the target architecture, both hardware and software have to be described. We expose our technique and apply it to a multi producer and consumer example that is studied for several communication strategies.<>
{"title":"An integrated framework for rapid system prototyping and automatic code distribution","authors":"W. Kaim, F. Kordon","doi":"10.1109/IWRSP.1994.315909","DOIUrl":"https://doi.org/10.1109/IWRSP.1994.315909","url":null,"abstract":"Rapid prototyping of parallel systems is of interest to quickly produce a parallel prototype. The emergence of distributed systems technology has enabled one to develop software systems distributed over large networks. Rapid prototyping must deal with real parallelism over a set of processors, either closely or loosely coupled. We describe an extension of the CPN/TAGADA project to manage distributed code generation over a set of CPU. To achieve a mapping of components over the target architecture, both hardware and software have to be described. We expose our technique and apply it to a multi producer and consumer example that is studied for several communication strategies.<<ETX>>","PeriodicalId":261113,"journal":{"name":"Proceedings of IEEE 5th International Workshop on Rapid System Prototyping","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129346915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-21DOI: 10.1109/IWRSP.1994.315892
P. Kission, Hong Ding, A. Jerraya
This paper deals with using architectural synthesis and structured design methodology in order to accelerate the design process. Such task will be achieved using AMICAL, an architectural synthesis tool allowing the design of complex systems. The design starts with a behavioral description and a library of functional units. The library may include standard components and/or complex sub-systems that may be designed using other design tools and methodologies or using AMICAL itself. A design example, namely a PID (Proportional Integral Derivative) is used to illustrate the methodology. The synthesis of the PID is done using several functional unit libraries. The most interesting synthesis results are those obtained on having a sub-system (fixed-point unit) designed using AMICAL, and re-used as a functional unit for the synthesis of the full design.<>
{"title":"Accelerating the design process by using architectural synthesis","authors":"P. Kission, Hong Ding, A. Jerraya","doi":"10.1109/IWRSP.1994.315892","DOIUrl":"https://doi.org/10.1109/IWRSP.1994.315892","url":null,"abstract":"This paper deals with using architectural synthesis and structured design methodology in order to accelerate the design process. Such task will be achieved using AMICAL, an architectural synthesis tool allowing the design of complex systems. The design starts with a behavioral description and a library of functional units. The library may include standard components and/or complex sub-systems that may be designed using other design tools and methodologies or using AMICAL itself. A design example, namely a PID (Proportional Integral Derivative) is used to illustrate the methodology. The synthesis of the PID is done using several functional unit libraries. The most interesting synthesis results are those obtained on having a sub-system (fixed-point unit) designed using AMICAL, and re-used as a functional unit for the synthesis of the full design.<<ETX>>","PeriodicalId":261113,"journal":{"name":"Proceedings of IEEE 5th International Workshop on Rapid System Prototyping","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133411248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-21DOI: 10.1109/IWRSP.1994.315894
A. Attoui, Michel Schneider
Design and prototyping of real time/concurrent systems needs formal approaches in order to permit verification and validation at each step. Methods based on formal logic have been suggested but they often work only on a specific domain and are generally reserved to specialized users. In an attempt to overcome these two restrictions, we propose in this paper a method based on the rewriting logic. Theoretical backgrounds are not a prerequisite for the users. The method supports modularity and abstraction and follows the great principles of an object oriented approach. Different tools are available: a graphical editor for the specification of the structure and the behavior of the objects, an inference engine for rule validation, a generator of prototypes.<>
{"title":"A formal approach based on the rewriting logic for prototyping distributed information systems","authors":"A. Attoui, Michel Schneider","doi":"10.1109/IWRSP.1994.315894","DOIUrl":"https://doi.org/10.1109/IWRSP.1994.315894","url":null,"abstract":"Design and prototyping of real time/concurrent systems needs formal approaches in order to permit verification and validation at each step. Methods based on formal logic have been suggested but they often work only on a specific domain and are generally reserved to specialized users. In an attempt to overcome these two restrictions, we propose in this paper a method based on the rewriting logic. Theoretical backgrounds are not a prerequisite for the users. The method supports modularity and abstraction and follows the great principles of an object oriented approach. Different tools are available: a graphical editor for the specification of the structure and the behavior of the objects, an inference engine for rule validation, a generator of prototypes.<<ETX>>","PeriodicalId":261113,"journal":{"name":"Proceedings of IEEE 5th International Workshop on Rapid System Prototyping","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128248634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-21DOI: 10.1109/IWRSP.1994.315907
T. B. Ismail, M. Abid, K. O'Brien, A. Jerraya
This paper presents a method for modeling and synthesizing mixed HW/SW systems. The proposed method starts from a full system-level specification. Systems are modeled in a synthesis-oriented manner by means of an extended finite state machine model. System-level synthesis is composed of three tasks: partitioning systems into inter-dependent sub-systems, inter-subsystem communication synthesis and architecture mapping onto a flexible architecture platform which includes both hardware and software components. The overall method is illustrated with an example.<>
{"title":"An approach for hardware-software codesign","authors":"T. B. Ismail, M. Abid, K. O'Brien, A. Jerraya","doi":"10.1109/IWRSP.1994.315907","DOIUrl":"https://doi.org/10.1109/IWRSP.1994.315907","url":null,"abstract":"This paper presents a method for modeling and synthesizing mixed HW/SW systems. The proposed method starts from a full system-level specification. Systems are modeled in a synthesis-oriented manner by means of an extended finite state machine model. System-level synthesis is composed of three tasks: partitioning systems into inter-dependent sub-systems, inter-subsystem communication synthesis and architecture mapping onto a flexible architecture platform which includes both hardware and software components. The overall method is illustrated with an example.<<ETX>>","PeriodicalId":261113,"journal":{"name":"Proceedings of IEEE 5th International Workshop on Rapid System Prototyping","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125427099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-21DOI: 10.1109/IWRSP.1994.315908
D. Dolev, R. Strong, E. Wimmers
The goals of the RAPID environment are: firstly to make the programming of distributed protocols simple without restricting the protocol relevant choices of the programmer; secondly to provide encapsulation and reusability that are at least as powerful as those offered by object oriented programming; and thirdly to provide for different styles of programming that make RAPID an easy transitional programming environment between older and lower level languages and C. The environment provides and is programmed in the RAPID-FL subset of the functional language FL. Although the full power of FL is available to the programmer, a very small number of concepts need to be learned to program in RAPID-FL. Moreover, restriction to RAPID-FL means that one can have the safety of a functional language combined with reasonable uses of assignment. RAPID makes storage management trivial and reduces the complexity of communication management to handling a few simple commands. We describe our experience using RAPID to perform clock synchronization experiments and to serve as scaffolding for high performance C code that implements a collective communication protocol for parallel machines.<>
{"title":"Experience with RAPID prototypes","authors":"D. Dolev, R. Strong, E. Wimmers","doi":"10.1109/IWRSP.1994.315908","DOIUrl":"https://doi.org/10.1109/IWRSP.1994.315908","url":null,"abstract":"The goals of the RAPID environment are: firstly to make the programming of distributed protocols simple without restricting the protocol relevant choices of the programmer; secondly to provide encapsulation and reusability that are at least as powerful as those offered by object oriented programming; and thirdly to provide for different styles of programming that make RAPID an easy transitional programming environment between older and lower level languages and C. The environment provides and is programmed in the RAPID-FL subset of the functional language FL. Although the full power of FL is available to the programmer, a very small number of concepts need to be learned to program in RAPID-FL. Moreover, restriction to RAPID-FL means that one can have the safety of a functional language combined with reasonable uses of assignment. RAPID makes storage management trivial and reduces the complexity of communication management to handling a few simple commands. We describe our experience using RAPID to perform clock synchronization experiments and to serve as scaffolding for high performance C code that implements a collective communication protocol for parallel machines.<<ETX>>","PeriodicalId":261113,"journal":{"name":"Proceedings of IEEE 5th International Workshop on Rapid System Prototyping","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125390378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-21DOI: 10.1109/IWRSP.1994.315905
R. Lauwereins, P. Wauters, M. Adé, J. Peperstraete
Describes two novel features that are supported in GRAPE-II (Graphical RApid Prototyping Environment): geometric parallelism and cyclo-static data flow. GRAPE-II is intended as a system level tool for the rapid prototyping of digital signal processing (DSP) applications on multiprocessors. GRAPE-II fully supports code generation for multi-rate and asynchronous DSP applications on heterogeneous target multiprocessors. The first feature detailed in the paper, geometric parallelism, allows the programmer to efficiently specify data parallel operations, where multiple identical functions operate on different data sets. The second feature, cyclo-static data flow, enables the specification of cyclicly changing data dependencies, while still leading to static schedules.<>
{"title":"Geometric parallelism and cyclo-static data flow in GRAPE-II","authors":"R. Lauwereins, P. Wauters, M. Adé, J. Peperstraete","doi":"10.1109/IWRSP.1994.315905","DOIUrl":"https://doi.org/10.1109/IWRSP.1994.315905","url":null,"abstract":"Describes two novel features that are supported in GRAPE-II (Graphical RApid Prototyping Environment): geometric parallelism and cyclo-static data flow. GRAPE-II is intended as a system level tool for the rapid prototyping of digital signal processing (DSP) applications on multiprocessors. GRAPE-II fully supports code generation for multi-rate and asynchronous DSP applications on heterogeneous target multiprocessors. The first feature detailed in the paper, geometric parallelism, allows the programmer to efficiently specify data parallel operations, where multiple identical functions operate on different data sets. The second feature, cyclo-static data flow, enables the specification of cyclicly changing data dependencies, while still leading to static schedules.<<ETX>>","PeriodicalId":261113,"journal":{"name":"Proceedings of IEEE 5th International Workshop on Rapid System Prototyping","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127798242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-21DOI: 10.1109/IWRSP.1994.315899
E. Mariatos, M. Birbas, A. Birbas
In this paper, a reconfigurable rapid prototyping system, oriented to DSP applications is proposed. Using the novel approach of combining the reconfigurability offered by an FPGA unit and the processing power of the CORDIC architecture, a fast, scalable and highly parallel structure has been developed. The results obtained by experimenting with the implementation of DCT algorithms are really promising, in terms of performance and versatility, which allows us to proceed for the development of a prototype that will be targeted to an image compression standard like H.261. Moreover, it is envisioned to build a parametrised library of hardware compilers that will map a wide range of DSP algorithms on the proposed board.<>
{"title":"A reconfigurable DSP board based on CORDIC elements","authors":"E. Mariatos, M. Birbas, A. Birbas","doi":"10.1109/IWRSP.1994.315899","DOIUrl":"https://doi.org/10.1109/IWRSP.1994.315899","url":null,"abstract":"In this paper, a reconfigurable rapid prototyping system, oriented to DSP applications is proposed. Using the novel approach of combining the reconfigurability offered by an FPGA unit and the processing power of the CORDIC architecture, a fast, scalable and highly parallel structure has been developed. The results obtained by experimenting with the implementation of DCT algorithms are really promising, in terms of performance and versatility, which allows us to proceed for the development of a prototype that will be targeted to an image compression standard like H.261. Moreover, it is envisioned to build a parametrised library of hardware compilers that will map a wide range of DSP algorithms on the proposed board.<<ETX>>","PeriodicalId":261113,"journal":{"name":"Proceedings of IEEE 5th International Workshop on Rapid System Prototyping","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134377748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-21DOI: 10.1109/IWRSP.1994.315895
S. Cross, R. Estrada
Improving software development is an area of American national technical interest. This is especially true in the Department of Defense (DoD), where software acquisition and maintenance costs have grown dramatically and where failed software development programs can no longer be afforded. This paper explores the software development process that was used in DART (Dynamic Analysis and Replanning Tool), a user-interactive information system which assists military planners in developing and analyzing war plans for deploying large numbers of troops and equipment. The program went from initial concept to fielded operational system in 23 months. (Normally, DoD programs take between 5 and 8 years to get from initial concept to operational system.) This paper focuses on the parts of the development process that accelerated the DART effort.<>
{"title":"DART: an example of accelerated evolutionary development","authors":"S. Cross, R. Estrada","doi":"10.1109/IWRSP.1994.315895","DOIUrl":"https://doi.org/10.1109/IWRSP.1994.315895","url":null,"abstract":"Improving software development is an area of American national technical interest. This is especially true in the Department of Defense (DoD), where software acquisition and maintenance costs have grown dramatically and where failed software development programs can no longer be afforded. This paper explores the software development process that was used in DART (Dynamic Analysis and Replanning Tool), a user-interactive information system which assists military planners in developing and analyzing war plans for deploying large numbers of troops and equipment. The program went from initial concept to fielded operational system in 23 months. (Normally, DoD programs take between 5 and 8 years to get from initial concept to operational system.) This paper focuses on the parts of the development process that accelerated the DART effort.<<ETX>>","PeriodicalId":261113,"journal":{"name":"Proceedings of IEEE 5th International Workshop on Rapid System Prototyping","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132011855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-21DOI: 10.1109/IWRSP.1994.315898
D. Lavenier, R. McConnell
Presents an approach for developing register transfer level (RTL) system models from behavioral models. Synchronous data flow principals are used to assist the transition. Our approach is based on a model of synchronous VLSI components which describes both their behavior, and their timing diagrams at a register transfer level. The component model permits the verification of correct synchronization at a system level. Initialization and termination conditions are explicitly checked.<>
{"title":"From behavioral to RTL models: an approach","authors":"D. Lavenier, R. McConnell","doi":"10.1109/IWRSP.1994.315898","DOIUrl":"https://doi.org/10.1109/IWRSP.1994.315898","url":null,"abstract":"Presents an approach for developing register transfer level (RTL) system models from behavioral models. Synchronous data flow principals are used to assist the transition. Our approach is based on a model of synchronous VLSI components which describes both their behavior, and their timing diagrams at a register transfer level. The component model permits the verification of correct synchronization at a system level. Initialization and termination conditions are explicitly checked.<<ETX>>","PeriodicalId":261113,"journal":{"name":"Proceedings of IEEE 5th International Workshop on Rapid System Prototyping","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126669709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-21DOI: 10.1109/IWRSP.1994.315911
C. Papadopoulos, A. Maniatopoulos, T. Antonakopoulos, V. Makios
This paper presents the basic components and configurations of a real-time test-bed developed for prototyping cell-based communication systems. Although it was initially developed for demonstrating the effectiveness of compression and adaptation techniques in 3DTV transmission over B-ISDN, the test-bed can also be used for measuring the performance of various services and applications over B-ISDN and other cell-based networks. The hardware has been based mainly on FPGAs, allowing the implementation of various communication functions following either the CCITT recommendations or proprietary access protocols.<>
{"title":"A real-time test-bed for prototyping cell-based communication networks","authors":"C. Papadopoulos, A. Maniatopoulos, T. Antonakopoulos, V. Makios","doi":"10.1109/IWRSP.1994.315911","DOIUrl":"https://doi.org/10.1109/IWRSP.1994.315911","url":null,"abstract":"This paper presents the basic components and configurations of a real-time test-bed developed for prototyping cell-based communication systems. Although it was initially developed for demonstrating the effectiveness of compression and adaptation techniques in 3DTV transmission over B-ISDN, the test-bed can also be used for measuring the performance of various services and applications over B-ISDN and other cell-based networks. The hardware has been based mainly on FPGAs, allowing the implementation of various communication functions following either the CCITT recommendations or proprietary access protocols.<<ETX>>","PeriodicalId":261113,"journal":{"name":"Proceedings of IEEE 5th International Workshop on Rapid System Prototyping","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129288148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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