This paper investigates an enhanced iterative scheduling called enhanced parallel iterative matching (EPIM) for input-buffered switches. EPIM is a modification of parallel iterative matching (PIM), and still maintains the original three-phase structure. Its capability for scheduling cell transmission is more than one time slot in each iteration which greatly increases the scheduling speed of the switch. Simulation shows that our algorithm outperforms PIM by a significant reduction in the number of iterations needed to approach the performance of the output queuing switch. Through incorporation with a static scheduling algorithm, EPIM can also operate in an environment containing a mix of cells belonging to both bandwidth-guaranteed and best-effort service categories.
{"title":"An enhanced iterative scheduling algorithm for ATM input-buffered switch","authors":"S. Liew, S. Cheng, T.T. Lee","doi":"10.1109/ATM.1999.786842","DOIUrl":"https://doi.org/10.1109/ATM.1999.786842","url":null,"abstract":"This paper investigates an enhanced iterative scheduling called enhanced parallel iterative matching (EPIM) for input-buffered switches. EPIM is a modification of parallel iterative matching (PIM), and still maintains the original three-phase structure. Its capability for scheduling cell transmission is more than one time slot in each iteration which greatly increases the scheduling speed of the switch. Simulation shows that our algorithm outperforms PIM by a significant reduction in the number of iterations needed to approach the performance of the output queuing switch. Through incorporation with a static scheduling algorithm, EPIM can also operate in an environment containing a mix of cells belonging to both bandwidth-guaranteed and best-effort service categories.","PeriodicalId":266412,"journal":{"name":"IEEE ATM Workshop '99 Proceedings (Cat. No. 99TH8462)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123422477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this contribution we focus on providing bandwidth guarantees for the guaranteed frame rate (GFR) transfer capability in the context of ATM-based passive optical networks (APONs). Our work builds on the research performed on ATM multiplexers and extends it with the specificities of the APON network. We study the performance of several known buffer management schemes (DFBA, WFBA, per-VC threshold), combined with either FIFO or per-VC scheduling, when applied on virtual circuits carrying TCP/IP traffic. We find that with fairly small buffers at the ONUs (optical network units), the schemes based on per-VC scheduling yield very good performance in a large number of cases. The schemes based on FIFO scheduling suffer from unfairness, although they do provide bandwidth guarantees in case the GFR bandwidth reservation is kept reasonably small.
{"title":"Support of the GFR transfer capability over a PON access system","authors":"S. Stojanovski, M. Gagnaire, R. Hoebeke","doi":"10.1109/ATM.1999.786855","DOIUrl":"https://doi.org/10.1109/ATM.1999.786855","url":null,"abstract":"In this contribution we focus on providing bandwidth guarantees for the guaranteed frame rate (GFR) transfer capability in the context of ATM-based passive optical networks (APONs). Our work builds on the research performed on ATM multiplexers and extends it with the specificities of the APON network. We study the performance of several known buffer management schemes (DFBA, WFBA, per-VC threshold), combined with either FIFO or per-VC scheduling, when applied on virtual circuits carrying TCP/IP traffic. We find that with fairly small buffers at the ONUs (optical network units), the schemes based on per-VC scheduling yield very good performance in a large number of cases. The schemes based on FIFO scheduling suffer from unfairness, although they do provide bandwidth guarantees in case the GFR bandwidth reservation is kept reasonably small.","PeriodicalId":266412,"journal":{"name":"IEEE ATM Workshop '99 Proceedings (Cat. No. 99TH8462)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129304971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper compares three ATM network design options in terms of the required link capacities and traffic flows for specified GoS and QoS requirements. The design options are referred to as: (i) end-to-end VP design; (ii) concatenated VP design; and (iii) VN design. Numerical results are presented for various large-scale networks and traffic conditions which demonstrate the cost-effectiveness of the VN design approach relative to the other design options.
{"title":"Comparison of the VP, CVP and VN approaches in ATM network design","authors":"L. Mason, Y. Xiong, I. Woungang","doi":"10.1109/ATM.1999.786879","DOIUrl":"https://doi.org/10.1109/ATM.1999.786879","url":null,"abstract":"This paper compares three ATM network design options in terms of the required link capacities and traffic flows for specified GoS and QoS requirements. The design options are referred to as: (i) end-to-end VP design; (ii) concatenated VP design; and (iii) VN design. Numerical results are presented for various large-scale networks and traffic conditions which demonstrate the cost-effectiveness of the VN design approach relative to the other design options.","PeriodicalId":266412,"journal":{"name":"IEEE ATM Workshop '99 Proceedings (Cat. No. 99TH8462)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130365396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper studies the overlayed virtual network approach to IP/ATM integration which closely resembles the ITU-T direct approach. Access of IP packets is controlled by a selective windowing mechanism to maximize the network power. New performance results for AAL3/4 and AAL5 protocols are shown. Performance is compared for the Poisson and self-similar IP packet traffic generation processes.
{"title":"Performance studies of IP over ATM via access flow controlled virtual networks","authors":"L. Mason, F. Vazqez-Abad, B. Kamte","doi":"10.1109/ATM.1999.786904","DOIUrl":"https://doi.org/10.1109/ATM.1999.786904","url":null,"abstract":"This paper studies the overlayed virtual network approach to IP/ATM integration which closely resembles the ITU-T direct approach. Access of IP packets is controlled by a selective windowing mechanism to maximize the network power. New performance results for AAL3/4 and AAL5 protocols are shown. Performance is compared for the Poisson and self-similar IP packet traffic generation processes.","PeriodicalId":266412,"journal":{"name":"IEEE ATM Workshop '99 Proceedings (Cat. No. 99TH8462)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121661424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes input buffering of controllable traffic as a simple and effective solution for congestion control in ATM WANs. ERICA and adaptive stochastic (AS) flow control schemes are used for comparing two network configurations: network "A"-where feedback messages travel to each individual source and network "B"-where feedback messages are sent from the output port to the input buffer of the switch where the total lower priority; i.e., controllable traffic, is queued. The requirements tested include queue size, queuing delay, queuing delay variance, and utilization. The results indicate that network "B", due to its insensitivity to lengths of links, manifested superior performance.
{"title":"A novel approach to congestion control in ATM wide area networks","authors":"S. Petrovic, A. Jamalipour","doi":"10.1109/ATM.1999.786886","DOIUrl":"https://doi.org/10.1109/ATM.1999.786886","url":null,"abstract":"This paper proposes input buffering of controllable traffic as a simple and effective solution for congestion control in ATM WANs. ERICA and adaptive stochastic (AS) flow control schemes are used for comparing two network configurations: network \"A\"-where feedback messages travel to each individual source and network \"B\"-where feedback messages are sent from the output port to the input buffer of the switch where the total lower priority; i.e., controllable traffic, is queued. The requirements tested include queue size, queuing delay, queuing delay variance, and utilization. The results indicate that network \"B\", due to its insensitivity to lengths of links, manifested superior performance.","PeriodicalId":266412,"journal":{"name":"IEEE ATM Workshop '99 Proceedings (Cat. No. 99TH8462)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115791381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sungjoon Park, Souhwan Jung, Gye Tae Khil, S. Gweon
This paper investigates the costs of building optical access networks by modeling cost functions on STAR, PON and ADS structures. A number of cost factors including the number of ONU, user bandwidth, distribution factor of a splitter, and cabling were considered in estimating the IFC of each configuration. Our analysis shows that the PON and ADS structures have lower costs than STAR at low user bandwidth, but increases over STAR at high user bandwidth.
{"title":"A cost analysis on optical access network architectures","authors":"Sungjoon Park, Souhwan Jung, Gye Tae Khil, S. Gweon","doi":"10.1109/ATM.1999.786874","DOIUrl":"https://doi.org/10.1109/ATM.1999.786874","url":null,"abstract":"This paper investigates the costs of building optical access networks by modeling cost functions on STAR, PON and ADS structures. A number of cost factors including the number of ONU, user bandwidth, distribution factor of a splitter, and cabling were considered in estimating the IFC of each configuration. Our analysis shows that the PON and ADS structures have lower costs than STAR at low user bandwidth, but increases over STAR at high user bandwidth.","PeriodicalId":266412,"journal":{"name":"IEEE ATM Workshop '99 Proceedings (Cat. No. 99TH8462)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123602721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Uematsu, H. Ohta, R. Iwase, K. Watanabe, M. Matsuda, M. Hiraki, T. Tsuboi
The ATM virtual path (VP)-based transport network is a candidate for the future multi-reliability and broadband integrated service infrastructure. This paper compares the performance attributes of the VP transport network with those of the conventional SDH network and future optical path-based transport network. This paper shows that the VP-based network is superior in terms of path-grooming efficiency and connection capability, and will still play an important role when WDM technologies are introduced to carrier networks. This paper also describes the recently fabricated VP cross connect (VP-XC) system configuration and the VP automatic protection switching (APS) performance of the XC.
{"title":"ATM VP-based economical transport network architecture for multi-reliability and broadband integrated service infrastructure","authors":"Y. Uematsu, H. Ohta, R. Iwase, K. Watanabe, M. Matsuda, M. Hiraki, T. Tsuboi","doi":"10.1109/ATM.1999.786877","DOIUrl":"https://doi.org/10.1109/ATM.1999.786877","url":null,"abstract":"The ATM virtual path (VP)-based transport network is a candidate for the future multi-reliability and broadband integrated service infrastructure. This paper compares the performance attributes of the VP transport network with those of the conventional SDH network and future optical path-based transport network. This paper shows that the VP-based network is superior in terms of path-grooming efficiency and connection capability, and will still play an important role when WDM technologies are introduced to carrier networks. This paper also describes the recently fabricated VP cross connect (VP-XC) system configuration and the VP automatic protection switching (APS) performance of the XC.","PeriodicalId":266412,"journal":{"name":"IEEE ATM Workshop '99 Proceedings (Cat. No. 99TH8462)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129533494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we propose a new network protocol framework, the adaptive mobile network protocol (AMNP) for general mobile networks based on the idea behind the hybrid IP/ATM. In AMNP, two operation modes are defined for each network layer packet present at a mobile network node, namely, the connection mode and the connectionless mode. The modes are inter-changeable depending on the mobility of the nodes. AMNP is adaptive to the network mobility and able to adjust its own behavior for the best delivery of QoS to the end services. In essence, AMNP exploits the advantages of the flexibility of IP and the high efficiency of ATM, and combines them to provide a robust performance under a wide range of mobility conditions.
{"title":"Adaptive mobile network protocol-extending the idea of hybrid IP/ATM for general mobile network","authors":"Yang Yang, Patricia Morreale, D. Vaman","doi":"10.1109/ATM.1999.786861","DOIUrl":"https://doi.org/10.1109/ATM.1999.786861","url":null,"abstract":"In this paper, we propose a new network protocol framework, the adaptive mobile network protocol (AMNP) for general mobile networks based on the idea behind the hybrid IP/ATM. In AMNP, two operation modes are defined for each network layer packet present at a mobile network node, namely, the connection mode and the connectionless mode. The modes are inter-changeable depending on the mobility of the nodes. AMNP is adaptive to the network mobility and able to adjust its own behavior for the best delivery of QoS to the end services. In essence, AMNP exploits the advantages of the flexibility of IP and the high efficiency of ATM, and combines them to provide a robust performance under a wide range of mobility conditions.","PeriodicalId":266412,"journal":{"name":"IEEE ATM Workshop '99 Proceedings (Cat. No. 99TH8462)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125654348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As its name implies, P-NNI (private network-network interface) was originally designed for private enterprise networks. However, many public carriers are seriously considering deployment of P-NNI networks. P-NNI promises fault-tolerant, dynamic QoS routing, in a highly scalable multi-vendor plug-and-play environment. The down side to P-NNI is its complexity. The ATM Forum specification totals over six hundred pages, including errata and addenda. Clearly, it is no small task to ensure that the switch you are building conforms to standards, and will inter-operate with others. If you are building a P-NNI network, and purchasing equipment off the shelf from one or more vendors, the same questions arise. This presentation provides a brief overview of the P-NNI standard, outlines some of the factors that need to be considered when developing a P-NNI test strategy, and illustrates how conformance testing can be performed.
{"title":"ATM Forum conformance testing to ensure your P-NNI implementation is ready to plug-and-play","authors":"R. Salier, G. Nelson","doi":"10.1109/ATM.1999.786871","DOIUrl":"https://doi.org/10.1109/ATM.1999.786871","url":null,"abstract":"As its name implies, P-NNI (private network-network interface) was originally designed for private enterprise networks. However, many public carriers are seriously considering deployment of P-NNI networks. P-NNI promises fault-tolerant, dynamic QoS routing, in a highly scalable multi-vendor plug-and-play environment. The down side to P-NNI is its complexity. The ATM Forum specification totals over six hundred pages, including errata and addenda. Clearly, it is no small task to ensure that the switch you are building conforms to standards, and will inter-operate with others. If you are building a P-NNI network, and purchasing equipment off the shelf from one or more vendors, the same questions arise. This presentation provides a brief overview of the P-NNI standard, outlines some of the factors that need to be considered when developing a P-NNI test strategy, and illustrates how conformance testing can be performed.","PeriodicalId":266412,"journal":{"name":"IEEE ATM Workshop '99 Proceedings (Cat. No. 99TH8462)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131947931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We have developed a switch access LSI with multiple ports, SAM, which functions as an interface to an ATM switch fabric. It constitutes a switch chipset with another two chips, and it can be used to construct a non-blocking ATM switch. SAM has a unique queueing architecture to achieve remarkable features that include shaping port, per-VC queueing, and flexible multicast. Additionally, SAM provides various ATM layer functions required in most ATM switch systems, i.e., ER mode and EFCI mode of ABR switch behavior with BECN mechanism, frame discarding, EFCI marking, CLP selective discarding, UPC cell tagging and discarding, and automatic OAM cell processing.
{"title":"A 622 Mbps ATM switch access LSI with multicast capable per-VC queueing architecture","authors":"Y. Shimojo, T. Saito, J. Hasegawa, T. Fujisawa","doi":"10.1109/ATM.1999.786884","DOIUrl":"https://doi.org/10.1109/ATM.1999.786884","url":null,"abstract":"We have developed a switch access LSI with multiple ports, SAM, which functions as an interface to an ATM switch fabric. It constitutes a switch chipset with another two chips, and it can be used to construct a non-blocking ATM switch. SAM has a unique queueing architecture to achieve remarkable features that include shaping port, per-VC queueing, and flexible multicast. Additionally, SAM provides various ATM layer functions required in most ATM switch systems, i.e., ER mode and EFCI mode of ABR switch behavior with BECN mechanism, frame discarding, EFCI marking, CLP selective discarding, UPC cell tagging and discarding, and automatic OAM cell processing.","PeriodicalId":266412,"journal":{"name":"IEEE ATM Workshop '99 Proceedings (Cat. No. 99TH8462)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127716326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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