M. Nishihara, K. Yamada, M. Masuda, T. Hayashi, K. Murakami, K. Miyahara
This paper proposes a new scheme for connectionless transmission of IP packets over an ATM network. The proposed scheme uses cut-through transfer of IP packets on a packet by packet basis. The proposed connectionless (CL) network uses VCI in the ATM header as the packet identification label. VC resources required on a given VP link is the number of IP packets that are concurrently transmitted within that VP. The proposed CL network is composed of network edge devices, called CL-GW (connectionless gateways), and core network nodes, called CL-XN (connectionless exchange nodes). They are interconnected by a semi-permanent virtual path in a partial mesh configuration. There is neither need for connection establishment prior to packet transfer nor need to provision a separate network to carry IP packets, i.e., connection-oriented ATM traffic and IP traffic can coexist within the same ATM network. Our proposed scheme is based on a concept where core network nodes should be able to transfer IP packets quickly at an ATM cell level (thus, need to eliminate packet level processing or special signaling between nodes), and process intensive functions be distributed to the network edge devices. CL-GW utilize a newly developed hardware address search engine, which can perform wire-speed search even for a 622 Mbit/s link speed. CL-GW and CL-XN are implemented as interface cards of an ATM crossconnect platform, which means that the proposed scheme can be installed cost-effectively.
{"title":"A cut-through transmission of IP packets and novel address resolution technique with cost-effective implementation","authors":"M. Nishihara, K. Yamada, M. Masuda, T. Hayashi, K. Murakami, K. Miyahara","doi":"10.1109/ATM.1999.786850","DOIUrl":"https://doi.org/10.1109/ATM.1999.786850","url":null,"abstract":"This paper proposes a new scheme for connectionless transmission of IP packets over an ATM network. The proposed scheme uses cut-through transfer of IP packets on a packet by packet basis. The proposed connectionless (CL) network uses VCI in the ATM header as the packet identification label. VC resources required on a given VP link is the number of IP packets that are concurrently transmitted within that VP. The proposed CL network is composed of network edge devices, called CL-GW (connectionless gateways), and core network nodes, called CL-XN (connectionless exchange nodes). They are interconnected by a semi-permanent virtual path in a partial mesh configuration. There is neither need for connection establishment prior to packet transfer nor need to provision a separate network to carry IP packets, i.e., connection-oriented ATM traffic and IP traffic can coexist within the same ATM network. Our proposed scheme is based on a concept where core network nodes should be able to transfer IP packets quickly at an ATM cell level (thus, need to eliminate packet level processing or special signaling between nodes), and process intensive functions be distributed to the network edge devices. CL-GW utilize a newly developed hardware address search engine, which can perform wire-speed search even for a 622 Mbit/s link speed. CL-GW and CL-XN are implemented as interface cards of an ATM crossconnect platform, which means that the proposed scheme can be installed cost-effectively.","PeriodicalId":266412,"journal":{"name":"IEEE ATM Workshop '99 Proceedings (Cat. No. 99TH8462)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130307538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
W. Rhee, Hwa-Suk Kim, Kyu-Ouk Lee, Byeung-Nam Yoon
In this paper, we describe the necessity of interoperability control between heterogeneous ATM transfer capabilities (ATC) in public networks and propose a service interworking method and a network interworking method for an interoperability control mechanism depending on the closed-loop range of each ATM transfer capability. Additionally, we propose DBR (deterministic bit rate) with backward explicit congestion notification method for the ABR (available bit rate)/DBR interoperability control and the block cell rate re-negotiation with state dependent mechanism for the ABR/ABT (ATM block transfer) interoperability control when DBR and ABT capabilities are implemented in public networks. Also, we analyzed the performance of the proposed interoperability control mechanisms in terms of the maximum queue length and the bandwidth utilization through the simulation.
{"title":"Interoperability control between heterogeneous ATCs in ATM public networks","authors":"W. Rhee, Hwa-Suk Kim, Kyu-Ouk Lee, Byeung-Nam Yoon","doi":"10.1109/ATM.1999.786869","DOIUrl":"https://doi.org/10.1109/ATM.1999.786869","url":null,"abstract":"In this paper, we describe the necessity of interoperability control between heterogeneous ATM transfer capabilities (ATC) in public networks and propose a service interworking method and a network interworking method for an interoperability control mechanism depending on the closed-loop range of each ATM transfer capability. Additionally, we propose DBR (deterministic bit rate) with backward explicit congestion notification method for the ABR (available bit rate)/DBR interoperability control and the block cell rate re-negotiation with state dependent mechanism for the ABR/ABT (ATM block transfer) interoperability control when DBR and ABT capabilities are implemented in public networks. Also, we analyzed the performance of the proposed interoperability control mechanisms in terms of the maximum queue length and the bandwidth utilization through the simulation.","PeriodicalId":266412,"journal":{"name":"IEEE ATM Workshop '99 Proceedings (Cat. No. 99TH8462)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114167235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The design of effective traffic and resource management policies is a key issue in the deployment of ATM-satellite systems. This paper proposes a technique of call admission control and dynamic resource management to support ATM traffic classes in satellite environments. The effectiveness of the strategy is assessed by referring to a multimedia satellite platform, based on Ka-band payload and on-board processing, called EuroSkyWay. The main advantage is the effective exploitation of the satellite bandwidth by means of the statistical multiplexing of traffic sources and the guarantee of QoS provisioning to both real-time and non-real-time, constant and variable bit rate sources.
{"title":"Real-time VBR traffic management in satellite-based ATM networks","authors":"A. Iera, A. Molinaro, S. Marano, M. Petrone","doi":"10.1109/ATM.1999.786787","DOIUrl":"https://doi.org/10.1109/ATM.1999.786787","url":null,"abstract":"The design of effective traffic and resource management policies is a key issue in the deployment of ATM-satellite systems. This paper proposes a technique of call admission control and dynamic resource management to support ATM traffic classes in satellite environments. The effectiveness of the strategy is assessed by referring to a multimedia satellite platform, based on Ka-band payload and on-board processing, called EuroSkyWay. The main advantage is the effective exploitation of the satellite bandwidth by means of the statistical multiplexing of traffic sources and the guarantee of QoS provisioning to both real-time and non-real-time, constant and variable bit rate sources.","PeriodicalId":266412,"journal":{"name":"IEEE ATM Workshop '99 Proceedings (Cat. No. 99TH8462)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117078252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Input buffered switches are known to suffer from head-of-line (HOL) blocking that limits the throughput to approximately 58.6%. It has been shown that 100% throughput can be achieved with virtual output queueing (VOQ) and an arbitration algorithm that controls the access to the switch fabric in each time slot. No weight-dependent algorithm was known that supports priorities, which are necessary for the isolation of connections with different QoS requirements in ATM or IPv6 switches. In this paper we show how a weighted matching can be extended to support priorities in order to separate CBR, VBR and ABR traffic. The number of bits per priority is exposed as the main parameter. Based on simulation results the priority performance is evaluated for the ideal algorithm and an approximation SIMP which offers a delay performance close to the ideal maximum weight matching.
{"title":"Prioritized arbitration for input-queued switches with 100% throughput","authors":"Rainer Schoenen, G. Post, G. Sander","doi":"10.1109/ATM.1999.786865","DOIUrl":"https://doi.org/10.1109/ATM.1999.786865","url":null,"abstract":"Input buffered switches are known to suffer from head-of-line (HOL) blocking that limits the throughput to approximately 58.6%. It has been shown that 100% throughput can be achieved with virtual output queueing (VOQ) and an arbitration algorithm that controls the access to the switch fabric in each time slot. No weight-dependent algorithm was known that supports priorities, which are necessary for the isolation of connections with different QoS requirements in ATM or IPv6 switches. In this paper we show how a weighted matching can be extended to support priorities in order to separate CBR, VBR and ABR traffic. The number of bits per priority is exposed as the main parameter. Based on simulation results the priority performance is evaluated for the ideal algorithm and an approximation SIMP which offers a delay performance close to the ideal maximum weight matching.","PeriodicalId":266412,"journal":{"name":"IEEE ATM Workshop '99 Proceedings (Cat. No. 99TH8462)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115243550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Kado, R. Konuma, M. Fujita, M. Murata, H. Miyahara
Scalability is one of key issues for cell scheduling disciplines in ATM (asynchronous transfer mode) switches when QoS of individual flows are guaranteed. In this paper, we show that a classed and chained queue (CCQ) scheduling discipline can provide better bandwidth guarantees of scalable number of flows compared with existing methods.
{"title":"Performance analysis of QoS guarantees scheduling disciplines over scalable number of flows","authors":"Y. Kado, R. Konuma, M. Fujita, M. Murata, H. Miyahara","doi":"10.1109/ATM.1999.786775","DOIUrl":"https://doi.org/10.1109/ATM.1999.786775","url":null,"abstract":"Scalability is one of key issues for cell scheduling disciplines in ATM (asynchronous transfer mode) switches when QoS of individual flows are guaranteed. In this paper, we show that a classed and chained queue (CCQ) scheduling discipline can provide better bandwidth guarantees of scalable number of flows compared with existing methods.","PeriodicalId":266412,"journal":{"name":"IEEE ATM Workshop '99 Proceedings (Cat. No. 99TH8462)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122726895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper addresses the provision and customization of virtual networks, and discusses how a virtual network can be programmed to support different approaches for integration of ATM and IP. First, the virtual network concept is introduced, followed by a discussion of a management system architecture for the control of the virtual network. Then, the paper discusses how a virtual network can be provided and customized through the partitioning of network resources and the programmability of the management system. This paper proceeds with a discussion of how the management system can support the integration of ATM and IP in order to demonstrate the capability of full customization of the network environment support. Finally, the partitioning of our NAL (Network Architecture Laboratory) testbed network is presented.
{"title":"Provision and customization of ATM virtual networks for supporting IP services","authors":"W. Ng, R. Boutaba, A. Leon-Garcia","doi":"10.1109/ATM.1999.786858","DOIUrl":"https://doi.org/10.1109/ATM.1999.786858","url":null,"abstract":"This paper addresses the provision and customization of virtual networks, and discusses how a virtual network can be programmed to support different approaches for integration of ATM and IP. First, the virtual network concept is introduced, followed by a discussion of a management system architecture for the control of the virtual network. Then, the paper discusses how a virtual network can be provided and customized through the partitioning of network resources and the programmability of the management system. This paper proceeds with a discussion of how the management system can support the integration of ATM and IP in order to demonstrate the capability of full customization of the network environment support. Finally, the partitioning of our NAL (Network Architecture Laboratory) testbed network is presented.","PeriodicalId":266412,"journal":{"name":"IEEE ATM Workshop '99 Proceedings (Cat. No. 99TH8462)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125831551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The classical method of max-min fair-rate allocation doesn't support the weighted-rate guarantee. The weighted-rate guarantee is necessary to available-bit rate (ABR) service models. This fact has motivated the wide study of weighted max-min (WMM) fair-fate allocation for ABR traffic. However, the combination of close-loop feedback control with the WMM algorithm has not appeared in the previous research. In this paper, a practical WMM fair-rate allocation model is proposed. This scheduling scheme combines and integrates congestion avoidance using proportional control (CAPC) and weighted max-min fair-rate allocation. In the system under analysis, a new weighted traffic scheduler is introduced. This model is designed to achieve higher utilization and also bounded delay for ABR traffic flow control.
{"title":"Combining CAPC and weighted traffic scheduling to achieve high quality ABR traffic control","authors":"Jun Lu, N. Mir","doi":"10.1109/ATM.1999.786856","DOIUrl":"https://doi.org/10.1109/ATM.1999.786856","url":null,"abstract":"The classical method of max-min fair-rate allocation doesn't support the weighted-rate guarantee. The weighted-rate guarantee is necessary to available-bit rate (ABR) service models. This fact has motivated the wide study of weighted max-min (WMM) fair-fate allocation for ABR traffic. However, the combination of close-loop feedback control with the WMM algorithm has not appeared in the previous research. In this paper, a practical WMM fair-rate allocation model is proposed. This scheduling scheme combines and integrates congestion avoidance using proportional control (CAPC) and weighted max-min fair-rate allocation. In the system under analysis, a new weighted traffic scheduler is introduced. This model is designed to achieve higher utilization and also bounded delay for ABR traffic flow control.","PeriodicalId":266412,"journal":{"name":"IEEE ATM Workshop '99 Proceedings (Cat. No. 99TH8462)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129190676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Stefan Dresler, Robert Lisak, Hartmut Ritter, H. Wiltfang
ATM, the asynchronous transfer mode, represents a flexible transmission technology, which offers a set of new services to the user. In order to take advantage of ATM's strength and to be able to integrate access to ATM services into applications, a powerful ATM application programming interface (API) is needed. At our institute, we have implemented three different variants of such an API for accessing native ATM functions. In this paper we first present the design and implementation of an ATM API in C for Digital Alpha workstations running Digital UNIX. We then describe a Java ATM API offering the socket programming environment Java programmers are used to, and finally a set of Java functions accessing the Windows NT Winsock 2 interface. We contrast the different philosophies and architectural approaches with each other and give throughput numbers.
异步传输方式ATM代表了一种灵活的传输技术，它为用户提供了一系列新的服务。为了充分利用ATM的优势，并能够将对ATM服务的访问集成到应用程序中，需要一个功能强大的ATM应用程序编程接口(API)。在我们的研究所，我们实现了这种API的三种不同变体，用于访问本机ATM功能。在本文中，我们首先提出了一个基于C语言的ATM API的设计和实现，该API适用于运行数字UNIX的Digital Alpha工作站。然后我们描述了一个Java ATM API，提供Java程序员习惯的套接字编程环境，最后是一组访问Windows NT Winsock 2接口的Java函数。我们对比了不同的理念和架构方法，并给出了吞吐量数字。
{"title":"Native ATM interfaces in C and Java: implementation and experiences","authors":"Stefan Dresler, Robert Lisak, Hartmut Ritter, H. Wiltfang","doi":"10.1109/ATM.1999.786894","DOIUrl":"https://doi.org/10.1109/ATM.1999.786894","url":null,"abstract":"ATM, the asynchronous transfer mode, represents a flexible transmission technology, which offers a set of new services to the user. In order to take advantage of ATM's strength and to be able to integrate access to ATM services into applications, a powerful ATM application programming interface (API) is needed. At our institute, we have implemented three different variants of such an API for accessing native ATM functions. In this paper we first present the design and implementation of an ATM API in C for Digital Alpha workstations running Digital UNIX. We then describe a Java ATM API offering the socket programming environment Java programmers are used to, and finally a set of Java functions accessing the Windows NT Winsock 2 interface. We contrast the different philosophies and architectural approaches with each other and give throughput numbers.","PeriodicalId":266412,"journal":{"name":"IEEE ATM Workshop '99 Proceedings (Cat. No. 99TH8462)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114940418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Resource allocation is one of major issues on SVC-based IP-over-ATM networks. We study the effect of the system design parameters on the performance using a finite-capacity single-vacation model, with close-down/setup times and a Markovian arrival process (MAP). We show the packet loss probability as a function of buffer size, SVC timeout period, and bandwidth. If the SVC setup delay and release delay are small, the loss during SVC setup is relatively small, and the loss in the service phase is dominant. However, if the SVC setup delay and release delay are large, the loss in SVC setup is significantly larger than the loss in the service phase. When the SVC timeout period is changed, there is a tradeoff between SVC setup rate and SVC utilization rate. Therefore, the timeout period must be set to maximize SVC utilization rate and to minimize the processing power of the SVC processor.
{"title":"Performance study of SVC-based IP-over-ATM networks","authors":"N. Endo, Z. Niu, A. Sawada","doi":"10.1109/ATM.1999.786906","DOIUrl":"https://doi.org/10.1109/ATM.1999.786906","url":null,"abstract":"Resource allocation is one of major issues on SVC-based IP-over-ATM networks. We study the effect of the system design parameters on the performance using a finite-capacity single-vacation model, with close-down/setup times and a Markovian arrival process (MAP). We show the packet loss probability as a function of buffer size, SVC timeout period, and bandwidth. If the SVC setup delay and release delay are small, the loss during SVC setup is relatively small, and the loss in the service phase is dominant. However, if the SVC setup delay and release delay are large, the loss in SVC setup is significantly larger than the loss in the service phase. When the SVC timeout period is changed, there is a tradeoff between SVC setup rate and SVC utilization rate. Therefore, the timeout period must be set to maximize SVC utilization rate and to minimize the processing power of the SVC processor.","PeriodicalId":266412,"journal":{"name":"IEEE ATM Workshop '99 Proceedings (Cat. No. 99TH8462)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128190322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A new high-capacity switching scheme for ATM/WDM networks is presented. The proposed architecture is contention-free, flexible and highly scalable. Switching performance is studied for data rates of up to 10 Gbit/s/port, providing aggregated capacity of over 1 Terabit/s. Simulation results show that low latency is achieved, yielding a powerful solution for high-performance packet-switching networks.
{"title":"A novel Tbit/sec switch architecture for ATM/WDM high-speed networks","authors":"I. Elhanany, D. Sadot","doi":"10.1109/ATM.1999.786792","DOIUrl":"https://doi.org/10.1109/ATM.1999.786792","url":null,"abstract":"A new high-capacity switching scheme for ATM/WDM networks is presented. The proposed architecture is contention-free, flexible and highly scalable. Switching performance is studied for data rates of up to 10 Gbit/s/port, providing aggregated capacity of over 1 Terabit/s. Simulation results show that low latency is achieved, yielding a powerful solution for high-performance packet-switching networks.","PeriodicalId":266412,"journal":{"name":"IEEE ATM Workshop '99 Proceedings (Cat. No. 99TH8462)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131935858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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