This paper proposes a distributed traffic control method for large multi-stage ATM switching systems. In the proposed switching system, each port of the basic switches has its own traffic monitor, and each line unit (LU) periodically obtains congestion information about available paths from OAM cells in order to route a new virtual circuit independently. The performance of the proposed system depends on the interval between OAM cells. We show how an appropriate interval can be determined in order to maximize the number of user cells that each LU can send.
{"title":"Distributed traffic control method for Tbit/s multi-stage ATM switching systems","authors":"K. Nakai, E. Oki, N. Yamanaka","doi":"10.1109/ATM.1999.786844","DOIUrl":"https://doi.org/10.1109/ATM.1999.786844","url":null,"abstract":"This paper proposes a distributed traffic control method for large multi-stage ATM switching systems. In the proposed switching system, each port of the basic switches has its own traffic monitor, and each line unit (LU) periodically obtains congestion information about available paths from OAM cells in order to route a new virtual circuit independently. The performance of the proposed system depends on the interval between OAM cells. We show how an appropriate interval can be determined in order to maximize the number of user cells that each LU can send.","PeriodicalId":266412,"journal":{"name":"IEEE ATM Workshop '99 Proceedings (Cat. No. 99TH8462)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133573796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes a new scheduling algorithm for input-queued ATM switches, called the iterative quasi-oldest-cell-first (i-QOCF) algorithm. In i-QOCF, each input port and each output port maintains its own list. The length of the list can be N,2/spl times/N,...,B/spl times/N, where B is the size of the buffer that queues cells destined for an output port. The list maintained by an input port contains the identifiers of those output ports to which that input port will send a cell. The list maintained by an output port contains the identifiers of input ports which have a cell destined for that output port. We show the performance of i-QOCF and results in which we compare i-QOCF with i-OCF in terms of cell delay time. We find that an input-queued ATM switch with i-QOCF and virtual output queue (VOQ) can achieve 100% throughput for independent arrival processes. The 3-QOCF is enough to achieve convergence during one cell time. If we use a 3-QOCF in which the list length is 3/spl times/N, then its cell delay time performance is almost the same as that of a 4-OCF.
{"title":"The i-QOCF (iterative quasi-oldest-cell-first) algorithm for input-queued ATM switches","authors":"M. Nabeshima, N. Yamanaka","doi":"10.1109/ATM.1999.786768","DOIUrl":"https://doi.org/10.1109/ATM.1999.786768","url":null,"abstract":"This paper proposes a new scheduling algorithm for input-queued ATM switches, called the iterative quasi-oldest-cell-first (i-QOCF) algorithm. In i-QOCF, each input port and each output port maintains its own list. The length of the list can be N,2/spl times/N,...,B/spl times/N, where B is the size of the buffer that queues cells destined for an output port. The list maintained by an input port contains the identifiers of those output ports to which that input port will send a cell. The list maintained by an output port contains the identifiers of input ports which have a cell destined for that output port. We show the performance of i-QOCF and results in which we compare i-QOCF with i-OCF in terms of cell delay time. We find that an input-queued ATM switch with i-QOCF and virtual output queue (VOQ) can achieve 100% throughput for independent arrival processes. The 3-QOCF is enough to achieve convergence during one cell time. If we use a 3-QOCF in which the list length is 3/spl times/N, then its cell delay time performance is almost the same as that of a 4-OCF.","PeriodicalId":266412,"journal":{"name":"IEEE ATM Workshop '99 Proceedings (Cat. No. 99TH8462)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116802780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes a multi-QoS scalable-distributed-arbitration (MSDA) ATM switch that supports both the high-priority class and the low-priority class under the head-of-line-priority discipline. It has a crosspoint buffer and a transit buffer, each consisting of a high-priority buffer and a low-priority buffer. Arbitration is executed between the crosspoint buffer and the transit buffer in a distributed manner. The MSDA switch extends the advantage of our previously proposed single-QoS scalable-distributed-arbitration (SSDA) switch. It is expandable while permitting high output-line speeds due to the distributed arbitration. The SSDA switch has a problem when its delay-time-based cell selection mechanism is applied to the low-priority class due to the limitation of the number of bits for the delay measure in the cell overhead. We solved this problem by introducing a distributed-ring-arbiter-based cell selection mechanism at each crosspoint for the low-priority class. The low-priority transit buffer at each crosspoint has virtual queues in accordance with the upper input ports. Cells for the low-priority class are selected by distributed ring arbitration among the low-priority crosspoint buffer and the virtual queues at the low-priority transit buffer. Simulations confirm that the MSDA switch ensures fairness in terms of delay time for the high-priority class, while it ensures fairness in terms of throughput for the low-priority class.
{"title":"Scalable-distributed-arbitration ATM switch supporting multiple QoS classes","authors":"E. Oki, N. Yamanaka, M. Nabeshima","doi":"10.1109/ATM.1999.786875","DOIUrl":"https://doi.org/10.1109/ATM.1999.786875","url":null,"abstract":"This paper proposes a multi-QoS scalable-distributed-arbitration (MSDA) ATM switch that supports both the high-priority class and the low-priority class under the head-of-line-priority discipline. It has a crosspoint buffer and a transit buffer, each consisting of a high-priority buffer and a low-priority buffer. Arbitration is executed between the crosspoint buffer and the transit buffer in a distributed manner. The MSDA switch extends the advantage of our previously proposed single-QoS scalable-distributed-arbitration (SSDA) switch. It is expandable while permitting high output-line speeds due to the distributed arbitration. The SSDA switch has a problem when its delay-time-based cell selection mechanism is applied to the low-priority class due to the limitation of the number of bits for the delay measure in the cell overhead. We solved this problem by introducing a distributed-ring-arbiter-based cell selection mechanism at each crosspoint for the low-priority class. The low-priority transit buffer at each crosspoint has virtual queues in accordance with the upper input ports. Cells for the low-priority class are selected by distributed ring arbitration among the low-priority crosspoint buffer and the virtual queues at the low-priority transit buffer. Simulations confirm that the MSDA switch ensures fairness in terms of delay time for the high-priority class, while it ensures fairness in terms of throughput for the low-priority class.","PeriodicalId":266412,"journal":{"name":"IEEE ATM Workshop '99 Proceedings (Cat. No. 99TH8462)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116086105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A multi-stage switching architecture is a key technology for building a high-speed ATM switching system. An effective way to make a multi-stage switch nonblocking is to use cell-based routing. However, cell-based routing may cause cell-sequence disorder at the output of the switching fabric. This paper proposes a hierarchical cell-sorting (HCS) switch architecture, which is a nonblocking multi-stage ATM switch using cell-based routing technology. Each basic HCS switch performs cell sorting at every crosspoint, based on timestamp information in the cell-header. This arranges the cells in sequence at the output of each basic HCS switch, since the crosspoints are hierarchically interconnected from the input port to the output port of a basic HCS switch. A multi-stage HCS switch is constructed by interconnecting the input and output lines of these basic HCS switches in a hierarchical manner. Thus, the cell sequence in each final output of the multi-stage switch is preserved in a hierarchical manner. In this way, cell-based routing with 100% throughput is achieved, with no need for internal speed-up techniques.
{"title":"A nonblocking multi-stage ATM switch using cell-based routing with a hierarchical cell sorting mechanism","authors":"D. Santoso, S. Yasukawa, N. Yamanaka, T. Miki","doi":"10.1109/ATM.1999.786867","DOIUrl":"https://doi.org/10.1109/ATM.1999.786867","url":null,"abstract":"A multi-stage switching architecture is a key technology for building a high-speed ATM switching system. An effective way to make a multi-stage switch nonblocking is to use cell-based routing. However, cell-based routing may cause cell-sequence disorder at the output of the switching fabric. This paper proposes a hierarchical cell-sorting (HCS) switch architecture, which is a nonblocking multi-stage ATM switch using cell-based routing technology. Each basic HCS switch performs cell sorting at every crosspoint, based on timestamp information in the cell-header. This arranges the cells in sequence at the output of each basic HCS switch, since the crosspoints are hierarchically interconnected from the input port to the output port of a basic HCS switch. A multi-stage HCS switch is constructed by interconnecting the input and output lines of these basic HCS switches in a hierarchical manner. Thus, the cell sequence in each final output of the multi-stage switch is preserved in a hierarchical manner. In this way, cell-based routing with 100% throughput is achieved, with no need for internal speed-up techniques.","PeriodicalId":266412,"journal":{"name":"IEEE ATM Workshop '99 Proceedings (Cat. No. 99TH8462)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116918194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The combined input output queued (CIOQ) architecture such as crossbar fabrics with speedup has recently been proposed to build a large-capacity switch for future broadband integrated services networks. Unlike an output queued (OQ) switch where queueing happens only at output ports, it is much more difficult for a CIOQ switch to provide quality of service (QoS) guarantee. Obviously, to achieve good performance in a CIOQ switch, the usage of switching fabrics has to be wisely scheduled. A scheduling algorithm named the least output occupancy first algorithm has been proposed to achieve 100% throughput in a CIOQ switch with a speedup factor of 2. However, achieving 100% throughput is not sufficient for per-connection QoS guarantees. Another proposed algorithm makes a CIOQ switch with a speedup factor of 4 to exactly emulate an output queued (OQ) switch which adopts FIFO as the service discipline at each output port. Unfortunately, FIFO is inappropriate for providing QoS guarantees. In this paper, we propose a new scheduling algorithm called the least cushion first/most urgent fist (LCF/MUF) algorithm and formally prove that a CIOQ switch with a speedup factor of 2 can exact emulate an OQ switch which adopts any service scheduling algorithm for cell transmission.
{"title":"Emulation of an output queued switch with a combined input output queued switch","authors":"Tsern-Huei Lee, Yaw-Wen Kuo, Jyh-Chiun Huang","doi":"10.1109/ATM.1999.786897","DOIUrl":"https://doi.org/10.1109/ATM.1999.786897","url":null,"abstract":"The combined input output queued (CIOQ) architecture such as crossbar fabrics with speedup has recently been proposed to build a large-capacity switch for future broadband integrated services networks. Unlike an output queued (OQ) switch where queueing happens only at output ports, it is much more difficult for a CIOQ switch to provide quality of service (QoS) guarantee. Obviously, to achieve good performance in a CIOQ switch, the usage of switching fabrics has to be wisely scheduled. A scheduling algorithm named the least output occupancy first algorithm has been proposed to achieve 100% throughput in a CIOQ switch with a speedup factor of 2. However, achieving 100% throughput is not sufficient for per-connection QoS guarantees. Another proposed algorithm makes a CIOQ switch with a speedup factor of 4 to exactly emulate an output queued (OQ) switch which adopts FIFO as the service discipline at each output port. Unfortunately, FIFO is inappropriate for providing QoS guarantees. In this paper, we propose a new scheduling algorithm called the least cushion first/most urgent fist (LCF/MUF) algorithm and formally prove that a CIOQ switch with a speedup factor of 2 can exact emulate an OQ switch which adopts any service scheduling algorithm for cell transmission.","PeriodicalId":266412,"journal":{"name":"IEEE ATM Workshop '99 Proceedings (Cat. No. 99TH8462)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130607773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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