Pub Date : 2009-01-05DOI: 10.1109/VLSI.Design.2009.101
W. Sansen
In nanometer CMOS technologies, several new effects emerge, such as velocity saturation and gate leakage currents. As a result the transconductance and speed are both limited by velocity saturation. Also noise and mismatch are affected as a result of the thinner gate oxides used. Moreover the supply voltage is reduced to values below 1 Volt, creating new challenges for analog circuit design. This presentation provides a review of the modifications in model parameters, including noise and distortion. It is followed by an exploration of the noise/power compromise in existing circuit blocks such as Miller operational amplifiers and Gm-C filters. An overview is the given of low-voltage amplifiers/filters configurations with both Gate and Bulk drives. Several sub-1 Volt circuits are finally discussed for different applications.
{"title":"Analog IC Design in Nanometer CMOS Technologies","authors":"W. Sansen","doi":"10.1109/VLSI.Design.2009.101","DOIUrl":"https://doi.org/10.1109/VLSI.Design.2009.101","url":null,"abstract":"In nanometer CMOS technologies, several new effects emerge, such as velocity saturation and gate leakage currents. As a result the transconductance and speed are both limited by velocity saturation. Also noise and mismatch are affected as a result of the thinner gate oxides used. Moreover the supply voltage is reduced to values below 1 Volt, creating new challenges for analog circuit design. This presentation provides a review of the modifications in model parameters, including noise and distortion. It is followed by an exploration of the noise/power compromise in existing circuit blocks such as Miller operational amplifiers and Gm-C filters. An overview is the given of low-voltage amplifiers/filters configurations with both Gate and Bulk drives. Several sub-1 Volt circuits are finally discussed for different applications.","PeriodicalId":267121,"journal":{"name":"2009 22nd International Conference on VLSI Design","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127962606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-01-05DOI: 10.1109/VLSI.Design.2009.80
A. Dixit, A. Bandhyopadhyay, N. Collaert, K. Meyer, M. Jurczak
FinFET is one of the promising device architectures for sub-32nm CMOS technology nodes. These non-planar devices benefit from near bulk-Si processing and improved control of short channels due to quasi gate-all-around operation. Their device operation is well studied and optimized in last half decade by various research groups. In this paper, we help evaluate the circuit potential of FinFETs by experimentally comparing their parasitic capacitance to that of the planar FDSOI MOSFETs. It is shown that n- and p-channel FinFETs achieve as high as 50% and 28% parasitic capacitance reduction compared to the planar FDSOI MOSFETs respectively.
{"title":"Measurement and Analysis of Parasitic Capacitance in FinFETs with High-k Dielectrics and Metal-Gate Stack","authors":"A. Dixit, A. Bandhyopadhyay, N. Collaert, K. Meyer, M. Jurczak","doi":"10.1109/VLSI.Design.2009.80","DOIUrl":"https://doi.org/10.1109/VLSI.Design.2009.80","url":null,"abstract":"FinFET is one of the promising device architectures for sub-32nm CMOS technology nodes. These non-planar devices benefit from near bulk-Si processing and improved control of short channels due to quasi gate-all-around operation. Their device operation is well studied and optimized in last half decade by various research groups. In this paper, we help evaluate the circuit potential of FinFETs by experimentally comparing their parasitic capacitance to that of the planar FDSOI MOSFETs. It is shown that n- and p-channel FinFETs achieve as high as 50% and 28% parasitic capacitance reduction compared to the planar FDSOI MOSFETs respectively.","PeriodicalId":267121,"journal":{"name":"2009 22nd International Conference on VLSI Design","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121479726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-01-05DOI: 10.1109/VLSI.Design.2009.71
Xiaoke Qin, P. Mishra
Code compression is important in embedded systems design since it reduces the code size (memory requirement) and thereby improves overall area, power and performance. Existing researches in this field have explored two directions: efficient compression with slow decompression, or fast decompression at the cost of compression efficiency. This paper combines the advantages of both approaches by introducing a novel bitstream placement method. The contribution of this paper is a novel code placement technique to enable parallel decompression without sacrificing the compression efficiency. The proposed technique splits a single bitstream (instruction binary) fetched from memory into multiple bitstreams, which are then fed into different decoders. As a result, multiple slow-decoders can work simultaneously to produce the effect of high decode bandwidth. Our experimental results demonstrate that our approach can improve decode bandwidth up to four times with minor impact (less than 1%) on compression efficiency.
{"title":"Efficient Placement of Compressed Code for Parallel Decompression","authors":"Xiaoke Qin, P. Mishra","doi":"10.1109/VLSI.Design.2009.71","DOIUrl":"https://doi.org/10.1109/VLSI.Design.2009.71","url":null,"abstract":"Code compression is important in embedded systems design since it reduces the code size (memory requirement) and thereby improves overall area, power and performance. Existing researches in this field have explored two directions: efficient compression with slow decompression, or fast decompression at the cost of compression efficiency. This paper combines the advantages of both approaches by introducing a novel bitstream placement method. The contribution of this paper is a novel code placement technique to enable parallel decompression without sacrificing the compression efficiency. The proposed technique splits a single bitstream (instruction binary) fetched from memory into multiple bitstreams, which are then fed into different decoders. As a result, multiple slow-decoders can work simultaneously to produce the effect of high decode bandwidth. Our experimental results demonstrate that our approach can improve decode bandwidth up to four times with minor impact (less than 1%) on compression efficiency.","PeriodicalId":267121,"journal":{"name":"2009 22nd International Conference on VLSI Design","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128513992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-01-05DOI: 10.1109/VLSI.Design.2009.56
Theja Tulabandhula, Y. Mitikiri
The design of an N-comparator based asynchronous Successive Approximation Analog-to-Digital Converter(SAR ADC) is described (with N = 6) working at 20 MS/sand consuming only 5.6 mW for low power high speed applications like communication systems. Resetting the comparators in each conversion cycle is avoided (reducing power consumption compared to [1]) and only N latches are used overall (incl. comparator latches) for the output code. Further using only N comparators instead of 2^N − 1 as in [2], leads to huge savings in terms of area at comparable power consumption. For example, a saving of ~90% comparator area is achieved for the 6 bit ADC design when compared to the design in [2].
{"title":"A 20MS/s 5.6 mW 6b Asynchronous ADC in 0.6µm CMOS","authors":"Theja Tulabandhula, Y. Mitikiri","doi":"10.1109/VLSI.Design.2009.56","DOIUrl":"https://doi.org/10.1109/VLSI.Design.2009.56","url":null,"abstract":"The design of an N-comparator based asynchronous Successive Approximation Analog-to-Digital Converter(SAR ADC) is described (with N = 6) working at 20 MS/sand consuming only 5.6 mW for low power high speed applications like communication systems. Resetting the comparators in each conversion cycle is avoided (reducing power consumption compared to [1]) and only N latches are used overall (incl. comparator latches) for the output code. Further using only N comparators instead of 2^N − 1 as in [2], leads to huge savings in terms of area at comparable power consumption. For example, a saving of ~90% comparator area is achieved for the 6 bit ADC design when compared to the design in [2].","PeriodicalId":267121,"journal":{"name":"2009 22nd International Conference on VLSI Design","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115304205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-01-05DOI: 10.1109/VLSI.Design.2009.53
K. Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Y. Higami, T. Aikyo, Y. Takamatsu, H. Yotsuyanagi, M. Hashizume
With the shrinking process technologies and the use of copper process, open defects on interconnect wires, contacts and vias often cause failure. Development of an efficient fault diagnosis method for open faults is desired. However, the diagnosis method for open faults has not been established yet. In this paper, we propose a novel approach for improving the diagnostic quality of open faults by introducing a threshold function in which the logical value of the line with open defect depends on the weighted logical values of its adjacent lines. By using the threshold function, we can deduce not only a faulty line but also an open defect site at the faulty line. Experimental results show that the proposed method can identify an exact faulty line in most cases with a very small computation cost. The proposed method can also identify the open defect site within 25%-length of the faulty line.
{"title":"A Novel Approach for Improving the Quality of Open Fault Diagnosis","authors":"K. Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Y. Higami, T. Aikyo, Y. Takamatsu, H. Yotsuyanagi, M. Hashizume","doi":"10.1109/VLSI.Design.2009.53","DOIUrl":"https://doi.org/10.1109/VLSI.Design.2009.53","url":null,"abstract":"With the shrinking process technologies and the use of copper process, open defects on interconnect wires, contacts and vias often cause failure. Development of an efficient fault diagnosis method for open faults is desired. However, the diagnosis method for open faults has not been established yet. In this paper, we propose a novel approach for improving the diagnostic quality of open faults by introducing a threshold function in which the logical value of the line with open defect depends on the weighted logical values of its adjacent lines. By using the threshold function, we can deduce not only a faulty line but also an open defect site at the faulty line. Experimental results show that the proposed method can identify an exact faulty line in most cases with a very small computation cost. The proposed method can also identify the open defect site within 25%-length of the faulty line.","PeriodicalId":267121,"journal":{"name":"2009 22nd International Conference on VLSI Design","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114857716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-01-05DOI: 10.1109/VLSI.Design.2009.86
A. Rahmani, I. Kamali, P. Lotfi-Kamran, A. Afzali-Kusha, S. Safari
In this paper, we propose a synthetic traffic model based on Negative Exponential Distribution (NED). This synthetic traffic profile is more similar to some statistical behavior of realistic traces obtained by running different applications on Network-on-chips that those of conventional synthetic traffic profiles. To assess usefulness of this traffic model, the average packet hops for the proposed traffic profile is compared with those of some synthetic and realistic traffic patterns obtained from running applications on NoCs. The results show that the NED traffic profile has more similarity with the realistic traffic profiles than those of conventional synthetic ones.
{"title":"Negative Exponential Distribution Traffic Pattern for Power/Performance Analysis of Network on Chips","authors":"A. Rahmani, I. Kamali, P. Lotfi-Kamran, A. Afzali-Kusha, S. Safari","doi":"10.1109/VLSI.Design.2009.86","DOIUrl":"https://doi.org/10.1109/VLSI.Design.2009.86","url":null,"abstract":"In this paper, we propose a synthetic traffic model based on Negative Exponential Distribution (NED). This synthetic traffic profile is more similar to some statistical behavior of realistic traces obtained by running different applications on Network-on-chips that those of conventional synthetic traffic profiles. To assess usefulness of this traffic model, the average packet hops for the proposed traffic profile is compared with those of some synthetic and realistic traffic patterns obtained from running applications on NoCs. The results show that the NED traffic profile has more similarity with the realistic traffic profiles than those of conventional synthetic ones.","PeriodicalId":267121,"journal":{"name":"2009 22nd International Conference on VLSI Design","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123500410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-01-05DOI: 10.1109/VLSI.Design.2009.19
S. Ramasamy, B. Venkataramani, R. Niranjini, K. Suganya
This paper proposes a modified, inverter based transconductor using double CMOS pair for implementation of biquad Gm-C low-pass filter with bandwidth tunable from 100 kHz to 20 MHz. This bandwidth range meets the requirements of zero IF receivers for wireless applications. Major contributions of this paper are proposal for operating the Gm stage in sub-threshold region so as to minimize the power dissipation, proposal for switching in both dummy stages and load capacitors (accumulation MOS-Capacitor) to maintain constant capacitance. The centre frequency of the filter is varied by switching in different Gm cells. The proposed filter is designed and implemented on TSMC-0.18µm CMOS process with 1.8V supply using Gm/Id design methodology. The simulation results demonstrate the tunability of the centre frequency from 100KHz to 20MHz. The power dissipated by the filter is 12µW and 900µW at 100KHz and 20MHz respectively. The SFDR over the entire band is 57dB. The proposed approach guarantees the upper bound on THD to be -40dB for 300mVpp signal swing. The use of inverters with double CMOS pair results in 34dB higher PSRR compared to those using push pull inverter.
{"title":"100KHz-20MHz Programmable Subthreshold G_m-C Low-Pass Filter in 0.18µ-m CMOS","authors":"S. Ramasamy, B. Venkataramani, R. Niranjini, K. Suganya","doi":"10.1109/VLSI.Design.2009.19","DOIUrl":"https://doi.org/10.1109/VLSI.Design.2009.19","url":null,"abstract":"This paper proposes a modified, inverter based transconductor using double CMOS pair for implementation of biquad Gm-C low-pass filter with bandwidth tunable from 100 kHz to 20 MHz. This bandwidth range meets the requirements of zero IF receivers for wireless applications. Major contributions of this paper are proposal for operating the Gm stage in sub-threshold region so as to minimize the power dissipation, proposal for switching in both dummy stages and load capacitors (accumulation MOS-Capacitor) to maintain constant capacitance. The centre frequency of the filter is varied by switching in different Gm cells. The proposed filter is designed and implemented on TSMC-0.18µm CMOS process with 1.8V supply using Gm/Id design methodology. The simulation results demonstrate the tunability of the centre frequency from 100KHz to 20MHz. The power dissipated by the filter is 12µW and 900µW at 100KHz and 20MHz respectively. The SFDR over the entire band is 57dB. The proposed approach guarantees the upper bound on THD to be -40dB for 300mVpp signal swing. The use of inverters with double CMOS pair results in 34dB higher PSRR compared to those using push pull inverter.","PeriodicalId":267121,"journal":{"name":"2009 22nd International Conference on VLSI Design","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116536485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-01-05DOI: 10.1109/VLSI.Design.2009.88
R. Dutta, T. K. Bhattacharyya
A low power architecture to extend the frequency range of quadrature clock is proposed. This architecture is based on a series of dividers. It can enhance the lower frequency limit of a Quadrature Voltage Controlled Oscillator (QVCO) clock to any arbitrarily small frequency. Based on the architecture a design is shown which enhances the low frequency range up to -90% of the center frequency, assuming the QVCO tuning range is +20%. The dividers are made of Dynamic Transmission Gate Logic (DTGL) to reduce power consumption. Simulation result shows that the power consumption of the extender circuit, excluding the QVCO, is 2.1mW from 1.2V supply voltage at 3GHz input frequency in 90nm CMOS technology. The output jitter contribution by this circuit is 2ps and 0.15ps for mismatch and thermal noise respectively. Maximum output frequency achieved is 4.8GHz for differential clock and 2.4GHz for quadrature clock.
{"title":"A Low Power Architecture to Extend the Tuning Range of a Quadrature Clock","authors":"R. Dutta, T. K. Bhattacharyya","doi":"10.1109/VLSI.Design.2009.88","DOIUrl":"https://doi.org/10.1109/VLSI.Design.2009.88","url":null,"abstract":"A low power architecture to extend the frequency range of quadrature clock is proposed. This architecture is based on a series of dividers. It can enhance the lower frequency limit of a Quadrature Voltage Controlled Oscillator (QVCO) clock to any arbitrarily small frequency. Based on the architecture a design is shown which enhances the low frequency range up to -90% of the center frequency, assuming the QVCO tuning range is +20%. The dividers are made of Dynamic Transmission Gate Logic (DTGL) to reduce power consumption. Simulation result shows that the power consumption of the extender circuit, excluding the QVCO, is 2.1mW from 1.2V supply voltage at 3GHz input frequency in 90nm CMOS technology. The output jitter contribution by this circuit is 2ps and 0.15ps for mismatch and thermal noise respectively. Maximum output frequency achieved is 4.8GHz for differential clock and 2.4GHz for quadrature clock.","PeriodicalId":267121,"journal":{"name":"2009 22nd International Conference on VLSI Design","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133356961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-01-05DOI: 10.1109/VLSI.Design.2009.70
P. Bhargava, Mohit Arora
Applications like Energy Meters that rely on real time data require accurate time under all environmental conditions. Typically, these applications rely on Real Time Clock (RTC) for all real time operations but there are many factors like crystal aging, incorrect loading and temperature variations that tend to change the frequency of the clock used for RTC resulting in inaccurate time. Hence there is an unavoidable need to have compensation technique inside the RTC to counter balance this error in clock frequency of crystal. This paper describes a digital hardware compensation technique which compensates by adding or removing pulses in a particular timing window thus maintaining accurate clock. Technique described in this paper uses simple hardware to ensure low power consumption thus maintaining longer battery life. This enables applications to use cheaper crystal that may be inaccurate and compensate for the inaccuracies within the hardware thus reducing board cost.
{"title":"A \"Stitch\" in Time: Accurate Timekeeping with On-Chip Compensation","authors":"P. Bhargava, Mohit Arora","doi":"10.1109/VLSI.Design.2009.70","DOIUrl":"https://doi.org/10.1109/VLSI.Design.2009.70","url":null,"abstract":"Applications like Energy Meters that rely on real time data require accurate time under all environmental conditions. Typically, these applications rely on Real Time Clock (RTC) for all real time operations but there are many factors like crystal aging, incorrect loading and temperature variations that tend to change the frequency of the clock used for RTC resulting in inaccurate time. Hence there is an unavoidable need to have compensation technique inside the RTC to counter balance this error in clock frequency of crystal. This paper describes a digital hardware compensation technique which compensates by adding or removing pulses in a particular timing window thus maintaining accurate clock. Technique described in this paper uses simple hardware to ensure low power consumption thus maintaining longer battery life. This enables applications to use cheaper crystal that may be inaccurate and compensate for the inaccuracies within the hardware thus reducing board cost.","PeriodicalId":267121,"journal":{"name":"2009 22nd International Conference on VLSI Design","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130569683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-01-05DOI: 10.1109/VLSI.Design.2009.100
G. Martin
It has been 10 years since a group of us wrote the book “Surviving the SoC Revolution: A Guide to Platform-Based Design”, and almost a decade since I gave a talk at VLSI 2000 in Kolkata about this theme. The intervening time has seen considerable development in the platform based design approach. It has become the near ubiquitous approach to the development of complex SoCs for many application areas. It has branched out from its original, mainly hardware-centric focus, to assume much more of a system and software focus complementing hardware. And the nature of platform architectures have changed: we now see many more embedded processors of all kinds in SoC platforms, from application-specific processors (ASIPs) to clusters of homogeneous or heterogeneous processing engines and many integrated subsystems each including one or more ASIPs or general purpose cores. This talk will look back at the past decade in platform based design and describe the evolution of architectures, design approaches and tools, and also look forward at the next decade or two and try to paint some possible scenarios for the future evolution of the platform-based approach. As we move towards new generations of design tools and higher level design approaches, what will be the main forms of platforms in future and how will designers use them?
{"title":"A Decade of Platform-Based Design: A look backwards, a look forwards","authors":"G. Martin","doi":"10.1109/VLSI.Design.2009.100","DOIUrl":"https://doi.org/10.1109/VLSI.Design.2009.100","url":null,"abstract":"It has been 10 years since a group of us wrote the book “Surviving the SoC Revolution: A Guide to Platform-Based Design”, and almost a decade since I gave a talk at VLSI 2000 in Kolkata about this theme. The intervening time has seen considerable development in the platform based design approach. It has become the near ubiquitous approach to the development of complex SoCs for many application areas. It has branched out from its original, mainly hardware-centric focus, to assume much more of a system and software focus complementing hardware. And the nature of platform architectures have changed: we now see many more embedded processors of all kinds in SoC platforms, from application-specific processors (ASIPs) to clusters of homogeneous or heterogeneous processing engines and many integrated subsystems each including one or more ASIPs or general purpose cores. This talk will look back at the past decade in platform based design and describe the evolution of architectures, design approaches and tools, and also look forward at the next decade or two and try to paint some possible scenarios for the future evolution of the platform-based approach. As we move towards new generations of design tools and higher level design approaches, what will be the main forms of platforms in future and how will designers use them?","PeriodicalId":267121,"journal":{"name":"2009 22nd International Conference on VLSI Design","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124129898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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