We study the impact of using 3D monolithic (3DM) standard cells on improving detailed routability and pin access. We propose a design flow which transforms standard rows of single-tier "2D" cells into rows of standard 3DM cells folded into two tiers. The transformation preserves layout characteristics such as overall area and number of metal layers for signal routing (i.e., M2 and above). It also creates redundant pins and free routing tracks in the two tiers used by the 3DM cells. We then propose an Integer Linear Program which routes as many nets as possible on the free 3DM routing tracks, leaving the rest of the nets to be routed via a standard global and detailed router on the metal layers dedicated for signal routing. Our experiments show significant improvement in detailed routability metrics using 3DM cells compared to using 2D standard cells.
{"title":"Improving Detailed Routability and Pin Access with 3D Monolithic Standard Cells","authors":"Daohang Shi, A. Davoodi","doi":"10.1145/3036669.3036676","DOIUrl":"https://doi.org/10.1145/3036669.3036676","url":null,"abstract":"We study the impact of using 3D monolithic (3DM) standard cells on improving detailed routability and pin access. We propose a design flow which transforms standard rows of single-tier \"2D\" cells into rows of standard 3DM cells folded into two tiers. The transformation preserves layout characteristics such as overall area and number of metal layers for signal routing (i.e., M2 and above). It also creates redundant pins and free routing tracks in the two tiers used by the 3DM cells. We then propose an Integer Linear Program which routes as many nets as possible on the free 3DM routing tracks, leaving the rest of the nets to be routed via a standard global and detailed router on the metal layers dedicated for signal routing. Our experiments show significant improvement in detailed routability metrics using 3DM cells compared to using 2D standard cells.","PeriodicalId":269197,"journal":{"name":"Proceedings of the 2017 ACM on International Symposium on Physical Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129927410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Biography Satoshi Goto received the B.E. and the M.E. Degrees in Electronics and Communication Engineering from Waseda University in 1968 and 1970 respectively. He also received the Dr. of Engineering from the same University in 1978. He joined NEC Laboratories in 1970 where he worked for LSI design, Multimedia system and Software as GM and Vice President. Since 2002, he has been Professor, at Graduate School of Information, Production and Systems of Waseda University at Kitakyushu and now Emeritus Professor at Waseda University, Japan. He served as GC of ICCAD, ASPDAC, VLSI-SOC, ASICON and ISOCC and was a board member of IEEE CAS society. He is IEEE Life Fellow and IEICE Fellow. He is Visiting Professor at Shanghai Jiao Tang University, Sun Yat-sen University and Tsinghua University of China and Member of Science Council of Japan.
{"title":"Past, Present and Future of the Research","authors":"S. Goto","doi":"10.1145/3036669.3038254","DOIUrl":"https://doi.org/10.1145/3036669.3038254","url":null,"abstract":"Biography Satoshi Goto received the B.E. and the M.E. Degrees in Electronics and Communication Engineering from Waseda University in 1968 and 1970 respectively. He also received the Dr. of Engineering from the same University in 1978. He joined NEC Laboratories in 1970 where he worked for LSI design, Multimedia system and Software as GM and Vice President. Since 2002, he has been Professor, at Graduate School of Information, Production and Systems of Waseda University at Kitakyushu and now Emeritus Professor at Waseda University, Japan. He served as GC of ICCAD, ASPDAC, VLSI-SOC, ASICON and ISOCC and was a board member of IEEE CAS society. He is IEEE Life Fellow and IEICE Fellow. He is Visiting Professor at Shanghai Jiao Tang University, Sun Yat-sen University and Tsinghua University of China and Member of Science Council of Japan.","PeriodicalId":269197,"journal":{"name":"Proceedings of the 2017 ACM on International Symposium on Physical Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132855644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Deep Learning has emerged as a singularly critical technology for enabling human-like intelligence in online services such as Azure, Office 365, Bing, Cortana, Skype, and other high-valued scenarios at Microsoft. While Deep Neural Networks (DNNs) have enabled state-of-the-art accuracy in many intelligence tasks, they are notoriously expensive and difficult to deploy in hyperscale datacenters constrained by power, cost, and latency. Furthermore, the escalating (and insatiable) demand for DNNs comes at an inopportune time as ideal silicon scaling (Moore's Law) comes to a diminishing end. At Microsoft, we have developed a new cloud architecture that's enhanced using FPGA (Field Programmable Gate Array). FPGAs can be viewed as programmable silicon and are being deployed into each and every new server in Microsoft's hyperscale infrastructure. The flexibility of FPGAs combined with a novel Hardware-as-a-Service (HaaS) architecture unlocks the full potential of a completely programmable hardware and software acceleration plane. In this talk, I'll give a history and overview of the project, discuss the key enabling technologies behind our enhanced cloud, present opportunities to harness this technology for accelerated deep learning, and conclude with directions for future work.
{"title":"Deep Learning in the Enhanced Cloud","authors":"Eric S. Chung","doi":"10.1145/3036669.3038243","DOIUrl":"https://doi.org/10.1145/3036669.3038243","url":null,"abstract":"Deep Learning has emerged as a singularly critical technology for enabling human-like intelligence in online services such as Azure, Office 365, Bing, Cortana, Skype, and other high-valued scenarios at Microsoft. While Deep Neural Networks (DNNs) have enabled state-of-the-art accuracy in many intelligence tasks, they are notoriously expensive and difficult to deploy in hyperscale datacenters constrained by power, cost, and latency. Furthermore, the escalating (and insatiable) demand for DNNs comes at an inopportune time as ideal silicon scaling (Moore's Law) comes to a diminishing end. At Microsoft, we have developed a new cloud architecture that's enhanced using FPGA (Field Programmable Gate Array). FPGAs can be viewed as programmable silicon and are being deployed into each and every new server in Microsoft's hyperscale infrastructure. The flexibility of FPGAs combined with a novel Hardware-as-a-Service (HaaS) architecture unlocks the full potential of a completely programmable hardware and software acceleration plane. In this talk, I'll give a history and overview of the project, discuss the key enabling technologies behind our enhanced cloud, present opportunities to harness this technology for accelerated deep learning, and conclude with directions for future work.","PeriodicalId":269197,"journal":{"name":"Proceedings of the 2017 ACM on International Symposium on Physical Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125442796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The presentation will discuss security techniques such as IC camouflaging and logic encryption.
演讲将讨论IC伪装和逻辑加密等安全技术。
{"title":"Research Challenges in Security-Aware Physical Design","authors":"R. Karri","doi":"10.1145/3036669.3051456","DOIUrl":"https://doi.org/10.1145/3036669.3051456","url":null,"abstract":"The presentation will discuss security techniques such as IC camouflaging and logic encryption.","PeriodicalId":269197,"journal":{"name":"Proceedings of the 2017 ACM on International Symposium on Physical Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121237252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Innovations and advancements on physical design (PD) in the past half century significantly contribute to the progresses of modern VLSI designs. While ``Moore's Law'' and ``Dennard Scaling'' have become slowing down recently, physical design society encountered a set of challenges and opportunities. This article is presented at the event of the Life Time Achievement Award for Dr. Satoshi Goto by ISPD 2017. Dr. Goto's career in VLSI designs sets an exemplar role model for young engineers. Thus, we use his contributions as a thread to describe our personal view of physical layout from early back-board ordering to recent multi-dimensional placement and the future.
{"title":"Physical Layout after Half a Century: From Back-Board Ordering to Multi-Dimensional Placement and Beyond","authors":"Ilgweon Kang, Chung-Kuan Cheng","doi":"10.1145/3036669.3038251","DOIUrl":"https://doi.org/10.1145/3036669.3038251","url":null,"abstract":"Innovations and advancements on physical design (PD) in the past half century significantly contribute to the progresses of modern VLSI designs. While ``Moore's Law'' and ``Dennard Scaling'' have become slowing down recently, physical design society encountered a set of challenges and opportunities. This article is presented at the event of the Life Time Achievement Award for Dr. Satoshi Goto by ISPD 2017. Dr. Goto's career in VLSI designs sets an exemplar role model for young engineers. Thus, we use his contributions as a thread to describe our personal view of physical layout from early back-board ordering to recent multi-dimensional placement and the future.","PeriodicalId":269197,"journal":{"name":"Proceedings of the 2017 ACM on International Symposium on Physical Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130190704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hyper-pipelining is a design technique that results in significant performance and throughput improvements in latency-insensitive designs. Modern FPGA architectures like Intel's Stratix®10 feature a revolutionary register-rich HyperFlex? core fabric architecture that make it amenable for hyper-pipelining. Design implementation CAD tools can provide insights into performance bottlenecks and how hyper-pipelining can result in improved performance, that can then be implemented using well-known techniques like retiming. Retiming was first introduced as a powerful sequential design optimization technique three decades ago, yet gained limited popularity in the ASIC industry. In recent years, retiming has gained tremendous popularity in the FPGA industry. This talk will discuss why this is the case, and provide insights into some of the interesting opportunities it presents for design implementation, analysis, and verification CAD tools. Impacts of hyper-pipelining on the physical design CAD flow and timing closure will also be discussed.
{"title":"CAD Opportunities with Hyper-Pipelining","authors":"M. Iyer","doi":"10.1145/3036669.3044804","DOIUrl":"https://doi.org/10.1145/3036669.3044804","url":null,"abstract":"Hyper-pipelining is a design technique that results in significant performance and throughput improvements in latency-insensitive designs. Modern FPGA architectures like Intel's Stratix®10 feature a revolutionary register-rich HyperFlex? core fabric architecture that make it amenable for hyper-pipelining. Design implementation CAD tools can provide insights into performance bottlenecks and how hyper-pipelining can result in improved performance, that can then be implemented using well-known techniques like retiming. Retiming was first introduced as a powerful sequential design optimization technique three decades ago, yet gained limited popularity in the ASIC industry. In recent years, retiming has gained tremendous popularity in the FPGA industry. This talk will discuss why this is the case, and provide insights into some of the interesting opportunities it presents for design implementation, analysis, and verification CAD tools. Impacts of hyper-pipelining on the physical design CAD flow and timing closure will also be discussed.","PeriodicalId":269197,"journal":{"name":"Proceedings of the 2017 ACM on International Symposium on Physical Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130255928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Nima Karimpour Darav, Ismail Bustany, A. Kennings, L. Behjat
The standard-cell placement legalization problem has become critical due to increasing design rule complexity and design utilization at 16nm and lower technology nodes. An ideal legalization approach should preserve the quality of the input placement in terms of routability and timing, as well as effectively manage white space availability and have low runtime. In this work, we present a robust legalization algorithm for standard cell placement that minimizes maximum cell movements fast and effectively based on a novel network-flow approach. The idea is inspired by path augmentation but with important differences. In contrast to the classical path augmentation approaches, we resolve bin overflows by finding several candidate paths that guarantee realizable (legal) flow solutions. In addition, we show how the proposed algorithm can be seamlessly extended to handle relevant cell edge spacing design rules. Our experimental results on the ISPD 2014 benchmarks illustrate that our proposed method yields 2.5x and 3.3x less maximum and average cell movement, respectively, and the runtime is significantly (18x) lower compared to best-in-class academic legalizers.
{"title":"A Fast, Robust Network Flow-based Standard-Cell Legalization Method for Minimizing Maximum Movement","authors":"Nima Karimpour Darav, Ismail Bustany, A. Kennings, L. Behjat","doi":"10.1145/3036669.3036680","DOIUrl":"https://doi.org/10.1145/3036669.3036680","url":null,"abstract":"The standard-cell placement legalization problem has become critical due to increasing design rule complexity and design utilization at 16nm and lower technology nodes. An ideal legalization approach should preserve the quality of the input placement in terms of routability and timing, as well as effectively manage white space availability and have low runtime. In this work, we present a robust legalization algorithm for standard cell placement that minimizes maximum cell movements fast and effectively based on a novel network-flow approach. The idea is inspired by path augmentation but with important differences. In contrast to the classical path augmentation approaches, we resolve bin overflows by finding several candidate paths that guarantee realizable (legal) flow solutions. In addition, we show how the proposed algorithm can be seamlessly extended to handle relevant cell edge spacing design rules. Our experimental results on the ISPD 2014 benchmarks illustrate that our proposed method yields 2.5x and 3.3x less maximum and average cell movement, respectively, and the runtime is significantly (18x) lower compared to best-in-class academic legalizers.","PeriodicalId":269197,"journal":{"name":"Proceedings of the 2017 ACM on International Symposium on Physical Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130091792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Biying Xu, Shaolan Li, Xiaoqing Xu, Nan Sun, D. Pan
High-performance analog integrated circuits usually require minimizing critical parasitic loading, which can be modeled by the critical net wire length in the layout stage. In order to reduce post-layout circuit performance degradation, critical net wire length minimization should be considered during placement, in addition to the conventional optimization objectives of total area and half perimeter wire length (HPWL). In this paper, we develop effective hierarchical and analytical techniques for high-performance analog circuits placement, which is a complex problem given its multi-objectives and constraints (e.g. hierarchical symmetric groups). The entire circuit is first partitioned hierarchically in a top-down, critical parasitics aware, hierarchical symmetric constraints and proximity constraints feasible manner, where the placement subproblem for each partition at each level can be solved in reasonable run-time. Then, different placement variants are generated for each partition from bottom up, taking advantage of the computation power of modern multi-core systems with parallelization. To assemble the placement variants of different subpartitions, a Mixed Integer Linear Programming (MILP) formulation is proposed which can simultaneously minimize critical parasitic loading, total area and HPWL, and handle hierarchical symmetric constraints, module variants selection and orientation. Experimental results demonstrate the effectiveness of the proposed techniques.
{"title":"Hierarchical and Analytical Placement Techniques for High-Performance Analog Circuits","authors":"Biying Xu, Shaolan Li, Xiaoqing Xu, Nan Sun, D. Pan","doi":"10.1145/3036669.3036678","DOIUrl":"https://doi.org/10.1145/3036669.3036678","url":null,"abstract":"High-performance analog integrated circuits usually require minimizing critical parasitic loading, which can be modeled by the critical net wire length in the layout stage. In order to reduce post-layout circuit performance degradation, critical net wire length minimization should be considered during placement, in addition to the conventional optimization objectives of total area and half perimeter wire length (HPWL). In this paper, we develop effective hierarchical and analytical techniques for high-performance analog circuits placement, which is a complex problem given its multi-objectives and constraints (e.g. hierarchical symmetric groups). The entire circuit is first partitioned hierarchically in a top-down, critical parasitics aware, hierarchical symmetric constraints and proximity constraints feasible manner, where the placement subproblem for each partition at each level can be solved in reasonable run-time. Then, different placement variants are generated for each partition from bottom up, taking advantage of the computation power of modern multi-core systems with parallelization. To assemble the placement variants of different subpartitions, a Mixed Integer Linear Programming (MILP) formulation is proposed which can simultaneously minimize critical parasitic loading, total area and HPWL, and handle hierarchical symmetric constraints, module variants selection and orientation. Experimental results demonstrate the effectiveness of the proposed techniques.","PeriodicalId":269197,"journal":{"name":"Proceedings of the 2017 ACM on International Symposium on Physical Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114466939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Fontana, R. Netto, Vinicius S. Livramento, C. Guth, S. Almeida, L. Pilla, José Luís Almada Güntzel
Similarly to game engines, physical design tools must handle huge amounts of data. Although the game industry has been employing modern software development concepts such as data-oriented design, most physical design tools still relies on object-oriented design. Differently from object-oriented design, data-oriented design focuses on how data is organized in memory and can be used to solve typical object-oriented design problems. However, its adoption is not trivial because most software developers are used to think about objects' relationships rather than data organization. The entity-component design pattern can be used as an efficient alternative. It consists in decomposing a problem into a set of entities and their components (properties). This paper discusses the main data-oriented design concepts, how they improve software quality and how they can be used in the context of physical design problems. In order to evaluate this programming model, we implemented an entity-component system using the open-source library Ophidian. Experimental results for two physical design tasks show that data-oriented design is much faster than object-oriented design for problems with good data locality, while been only sightly slower for other kinds of problems.
{"title":"How Game Engines Can Inspire EDA Tools Development: A use case for an open-source physical design library","authors":"T. Fontana, R. Netto, Vinicius S. Livramento, C. Guth, S. Almeida, L. Pilla, José Luís Almada Güntzel","doi":"10.1145/3036669.3038248","DOIUrl":"https://doi.org/10.1145/3036669.3038248","url":null,"abstract":"Similarly to game engines, physical design tools must handle huge amounts of data. Although the game industry has been employing modern software development concepts such as data-oriented design, most physical design tools still relies on object-oriented design. Differently from object-oriented design, data-oriented design focuses on how data is organized in memory and can be used to solve typical object-oriented design problems. However, its adoption is not trivial because most software developers are used to think about objects' relationships rather than data organization. The entity-component design pattern can be used as an efficient alternative. It consists in decomposing a problem into a set of entities and their components (properties). This paper discusses the main data-oriented design concepts, how they improve software quality and how they can be used in the context of physical design problems. In order to evaluate this programming model, we implemented an entity-component system using the open-source library Ophidian. Experimental results for two physical design tasks show that data-oriented design is much faster than object-oriented design for problems with good data locality, while been only sightly slower for other kinds of problems.","PeriodicalId":269197,"journal":{"name":"Proceedings of the 2017 ACM on International Symposium on Physical Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126294857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Proceedings of the 2017 ACM on International Symposium on Physical Design","authors":"","doi":"10.1145/3036669","DOIUrl":"https://doi.org/10.1145/3036669","url":null,"abstract":"","PeriodicalId":269197,"journal":{"name":"Proceedings of the 2017 ACM on International Symposium on Physical Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127510259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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