Pub Date : 2011-06-26DOI: 10.1109/NEWCAS.2011.5981270
M. Mailand, S. Getzlaff
Generally, there are two strategies to obtain a signal difference of two current sources: analog or digital subtraction. Digital subtraction limits the final resolution of the difference. Analog subtraction yields limitations in gain, range and sensitivity, respectively and may suffer from imperfections of the analog subtraction circuitry (e.g. matching, non-linearity, etc.). In this article, an approach is explained and demonstrated to maximize signal range, sensitivity and final resolution for the difference of two or more (sensor) input signals by utilizing integrating amplifiers with differential outputs. The correlated double-sampling concept is extended therefore. Signal properties and system constraints are explained. The applicability is demonstrated by a 0.6μm-CMOS implementation example for the subtraction of two photo-current input signals within a single transimpedance amplification stage.
{"title":"A transimpedance-amplifier-based subtraction principle for optimum signal resolution in mixed-signal current sensor systems","authors":"M. Mailand, S. Getzlaff","doi":"10.1109/NEWCAS.2011.5981270","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981270","url":null,"abstract":"Generally, there are two strategies to obtain a signal difference of two current sources: analog or digital subtraction. Digital subtraction limits the final resolution of the difference. Analog subtraction yields limitations in gain, range and sensitivity, respectively and may suffer from imperfections of the analog subtraction circuitry (e.g. matching, non-linearity, etc.). In this article, an approach is explained and demonstrated to maximize signal range, sensitivity and final resolution for the difference of two or more (sensor) input signals by utilizing integrating amplifiers with differential outputs. The correlated double-sampling concept is extended therefore. Signal properties and system constraints are explained. The applicability is demonstrated by a 0.6μm-CMOS implementation example for the subtraction of two photo-current input signals within a single transimpedance amplification stage.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116500087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-26DOI: 10.1109/NEWCAS.2011.5981319
A. Lesellier, O. Jamin, J. Bercher, O. Venard
We describe the design of an HFB-based ADC targeted towards the digitization of a very large band for Software Defined Radio applications. We present an original procedure for the optimization of the synthesis filters, when the front-end analysis filters use standard low-cost analog filters. We also address the calibration of the device, namely the identification of the actual analog filters, and highlight the impact of the identification and of measurement errors on the overall performances.
{"title":"Design, optimization and calibration of an HFB-based ADC","authors":"A. Lesellier, O. Jamin, J. Bercher, O. Venard","doi":"10.1109/NEWCAS.2011.5981319","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981319","url":null,"abstract":"We describe the design of an HFB-based ADC targeted towards the digitization of a very large band for Software Defined Radio applications. We present an original procedure for the optimization of the synthesis filters, when the front-end analysis filters use standard low-cost analog filters. We also address the calibration of the device, namely the identification of the actual analog filters, and highlight the impact of the identification and of measurement errors on the overall performances.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114875976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-26DOI: 10.1109/NEWCAS.2011.5981324
Zouha Cherif Jouini, J. Danger, L. Bossuet
This paper presents a novel approach to evaluate silicon Physically Unclonable Functions (PUFs) implemented in FPGAs and based on delay elements. The metrics studied to characterize the PUFs are Randomness, Uniqueness and Steadiness. They take advantage of the measured physical values of elementary component making up the PUF. The delay distributions provide the interest to quantify the PUF at the physical level rather than carrying out a lot of experiments to get the PUF IDs at logical level. An Arbiter PUF composed of identical chains has been considered as a test chip to evaluate the method with the proposed metrics. Experiments have been carried out on CYCLONE II FPGA and the corresponding results shows the intra-device performance of the studied PUF.
本文提出了一种评估fpga中基于延迟元件的硅物理不可克隆函数(puf)的新方法。研究表征puf的指标是随机性、唯一性和稳定性。它们利用了组成PUF的基本元件的测量物理值。延迟分布提供了在物理层上量化PUF的兴趣，而不是在逻辑层上进行大量的实验来获得PUF id。一个由相同链组成的仲裁者PUF被认为是一个测试芯片，用所提出的指标来评估该方法。在CYCLONE II FPGA上进行了实验，实验结果表明所研究的PUF器件内性能良好。
{"title":"Performance evaluation of Physically Unclonable Function by delay statistics","authors":"Zouha Cherif Jouini, J. Danger, L. Bossuet","doi":"10.1109/NEWCAS.2011.5981324","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981324","url":null,"abstract":"This paper presents a novel approach to evaluate silicon Physically Unclonable Functions (PUFs) implemented in FPGAs and based on delay elements. The metrics studied to characterize the PUFs are Randomness, Uniqueness and Steadiness. They take advantage of the measured physical values of elementary component making up the PUF. The delay distributions provide the interest to quantify the PUF at the physical level rather than carrying out a lot of experiments to get the PUF IDs at logical level. An Arbiter PUF composed of identical chains has been considered as a test chip to evaluate the method with the proposed metrics. Experiments have been carried out on CYCLONE II FPGA and the corresponding results shows the intra-device performance of the studied PUF.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122008663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-26DOI: 10.1109/NEWCAS.2011.5981307
M. Schlechtweg, A. Tessmann, I. Kallfass, A. Leuther, V. Hurm, H. Massler, M. Riessle, R. Losch, Oliver Ambacher
Metamorphic high electron mobility transistor (mHEMT) technologies with 100, 50, and 35 nm gate lengths have been developed at Fraunhofer IAF for operation in the millimeter-wave frequency range up to 500 GHz. Based on these technologies, a variety of millimeter-wave monolithic integrated circuits (MMICs) has been realized employing grounded coplanar waveguides (GCPWs). To demonstrate the potential of these technologies, this paper presents some examples of MMICs and modules developed for use in next generation remote sensing and communication systems. Two four-stage cascode amplifier circuits for operation in the frequency ranges 220–325 GHz (H-band) and 325–500 GHz (WR-2.2 waveguide band) were realized using the 50 and 35 nm mHEMT technology, respectively. Furthermore, a 200 GHz active subharmonically-pumped heterodyne receiver MMIC based on the 100 nm mHEMT technology was realized.
{"title":"Millimeter-wave circuits and modules up to 500 GHz based on metamorphic HEMT technology for remote sensing and wireless communication applications","authors":"M. Schlechtweg, A. Tessmann, I. Kallfass, A. Leuther, V. Hurm, H. Massler, M. Riessle, R. Losch, Oliver Ambacher","doi":"10.1109/NEWCAS.2011.5981307","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981307","url":null,"abstract":"Metamorphic high electron mobility transistor (mHEMT) technologies with 100, 50, and 35 nm gate lengths have been developed at Fraunhofer IAF for operation in the millimeter-wave frequency range up to 500 GHz. Based on these technologies, a variety of millimeter-wave monolithic integrated circuits (MMICs) has been realized employing grounded coplanar waveguides (GCPWs). To demonstrate the potential of these technologies, this paper presents some examples of MMICs and modules developed for use in next generation remote sensing and communication systems. Two four-stage cascode amplifier circuits for operation in the frequency ranges 220–325 GHz (H-band) and 325–500 GHz (WR-2.2 waveguide band) were realized using the 50 and 35 nm mHEMT technology, respectively. Furthermore, a 200 GHz active subharmonically-pumped heterodyne receiver MMIC based on the 100 nm mHEMT technology was realized.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132059519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-26DOI: 10.1109/NEWCAS.2011.5981266
P. Fiedorow, P. Maige, D. Subiela, T. Tixier, N. Abouchi
This paper shows the multipath frequency compensation in a general purpose operational amplifier. Firstly, it deals with the requirements of a general purpose opamp and introduces the need of the frequency compensation in the current circuits. Then, the rules to integrate multipath in an opamp are developed and the transfer function is presented and compared to the one of the nested miller compensation. Next, an implementation of the multipath nested miller compensation is described. Finally, simulation result which proves the efficiency of this compensation is given. The multipath compensation improves the classical compensation structure as it does not cutoff the initial unity gain frequency by four but only by two.
{"title":"Design and implementation of general purpose opamp using multipath frequency compensation","authors":"P. Fiedorow, P. Maige, D. Subiela, T. Tixier, N. Abouchi","doi":"10.1109/NEWCAS.2011.5981266","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981266","url":null,"abstract":"This paper shows the multipath frequency compensation in a general purpose operational amplifier. Firstly, it deals with the requirements of a general purpose opamp and introduces the need of the frequency compensation in the current circuits. Then, the rules to integrate multipath in an opamp are developed and the transfer function is presented and compared to the one of the nested miller compensation. Next, an implementation of the multipath nested miller compensation is described. Finally, simulation result which proves the efficiency of this compensation is given. The multipath compensation improves the classical compensation structure as it does not cutoff the initial unity gain frequency by four but only by two.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134409028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-26DOI: 10.1109/NEWCAS.2011.5981335
K. Baraka, E. Kerhervé, J. Pham, M. E. Hassan
This paper presents a method to reconfigure Bulk Acoustic Wave-Solidly Mounted Resonator (BAW-SMR) filters. It shows the effect of the gate voltage which controls the filter bandwidth with MOS transistors. This method is applied to filters operating in the W-CDMA (2.11–2.17 GHz) communication standard. Experimental results show a tuning range of 9MHz, whereas 12MHz of tuning range was achieved in the simulation.
{"title":"Co-design for tunability of a Bulk Acoustic Wave filters with 65nm CMOS switch","authors":"K. Baraka, E. Kerhervé, J. Pham, M. E. Hassan","doi":"10.1109/NEWCAS.2011.5981335","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981335","url":null,"abstract":"This paper presents a method to reconfigure Bulk Acoustic Wave-Solidly Mounted Resonator (BAW-SMR) filters. It shows the effect of the gate voltage which controls the filter bandwidth with MOS transistors. This method is applied to filters operating in the W-CDMA (2.11–2.17 GHz) communication standard. Experimental results show a tuning range of 9MHz, whereas 12MHz of tuning range was achieved in the simulation.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133299195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-26DOI: 10.1109/NEWCAS.2011.5981205
Teddy Borr, J. Juyon, É. Tournier
This paper introduces a new bipolar differential pair topology for both gaussian and sinusoidal signal shaping, to be used as a phase-to-amplitude converter alternative in low-power ultra-high-speed DDS. A DDS using this converter, with a 9-bit frequency resolution and an 8-bit amplitude resolution has been designed in a 0.13μm SiGe BiCMOS technology, with ft/fmax of 200/250GHz, and simulated up to a 20GHz operating clock frequency. It consumes 585mW under a 2.8V power supply. Simulated triangle shape allows an optimal SFDR of −44.5dBc in sinus mode and a SLRR of −43.5dBc in gaussian mode.
{"title":"A both Gaussian and sinusoidal phase-to-amplitude converter for low-power ultra-high-speed direct digital synthesizers","authors":"Teddy Borr, J. Juyon, É. Tournier","doi":"10.1109/NEWCAS.2011.5981205","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981205","url":null,"abstract":"This paper introduces a new bipolar differential pair topology for both gaussian and sinusoidal signal shaping, to be used as a phase-to-amplitude converter alternative in low-power ultra-high-speed DDS. A DDS using this converter, with a 9-bit frequency resolution and an 8-bit amplitude resolution has been designed in a 0.13μm SiGe BiCMOS technology, with ft/fmax of 200/250GHz, and simulated up to a 20GHz operating clock frequency. It consumes 585mW under a 2.8V power supply. Simulated triangle shape allows an optimal SFDR of −44.5dBc in sinus mode and a SLRR of −43.5dBc in gaussian mode.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117123970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-26DOI: 10.1109/NEWCAS.2011.5981211
M. Bahoura, Chan-Wang Park
In this paper, we propose an architecture for FPGA-implementation of neural adaptive neural network RF power behavioral modeling. The real-valued time-delay neural network (RVTDNN) and the backpropagation (BP) learning algorithm were implemented on FPGA using Xilinx System Generator for DSP and the Virtex-6 FPGA ML605 Evaluation Kit. Performances obtained with 16-QAM modulated test signal and material resource requirement are presented for a network of six hidden layer neurons.
本文提出了一种fpga实现的神经自适应神经网络射频功率行为建模体系结构。采用基于Xilinx System Generator的DSP和Virtex-6 FPGA ML605评估套件，在FPGA上实现了实值时滞神经网络(RVTDNN)和反向传播(BP)学习算法。给出了一个包含6个隐层神经元的网络，在16-QAM调制测试信号和材料资源需求下所获得的性能。
{"title":"FPGA-implementation of an adaptive neural network for RF power amplifier modeling","authors":"M. Bahoura, Chan-Wang Park","doi":"10.1109/NEWCAS.2011.5981211","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981211","url":null,"abstract":"In this paper, we propose an architecture for FPGA-implementation of neural adaptive neural network RF power behavioral modeling. The real-valued time-delay neural network (RVTDNN) and the backpropagation (BP) learning algorithm were implemented on FPGA using Xilinx System Generator for DSP and the Virtex-6 FPGA ML605 Evaluation Kit. Performances obtained with 16-QAM modulated test signal and material resource requirement are presented for a network of six hidden layer neurons.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116043159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-26DOI: 10.1109/NEWCAS.2011.5981333
Y. Kao, I-Jhih Wu
The cross-coupled pairs in CMOS are employed to the voltage controlled oscillator with surface acoustic wave (SAW) resonator. The problem of latch, which is not encounted in conventional LC oscillator, is essential in our case. With a careful design in bias this problem is solved. This oscillator has the advantage of inherent opposite polarity appeared on the terminals of SAW resonator, which leads to fast growing amplitude during transition. As compared to the well known Colpitts oscillator, the transition period is significantly shrinked. For completeness three kinds of oscillator with single ended, balanced Colpitts, and cross coupled one are compared in terms of figure of merit (FOM) under the same magnitude across the resonator. Also the power consumption and phase noise are indicated.
{"title":"Balanced SAW oscillators with cross-coupled CMOS pair","authors":"Y. Kao, I-Jhih Wu","doi":"10.1109/NEWCAS.2011.5981333","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981333","url":null,"abstract":"The cross-coupled pairs in CMOS are employed to the voltage controlled oscillator with surface acoustic wave (SAW) resonator. The problem of latch, which is not encounted in conventional LC oscillator, is essential in our case. With a careful design in bias this problem is solved. This oscillator has the advantage of inherent opposite polarity appeared on the terminals of SAW resonator, which leads to fast growing amplitude during transition. As compared to the well known Colpitts oscillator, the transition period is significantly shrinked. For completeness three kinds of oscillator with single ended, balanced Colpitts, and cross coupled one are compared in terms of figure of merit (FOM) under the same magnitude across the resonator. Also the power consumption and phase noise are indicated.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122181196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-26DOI: 10.1109/NEWCAS.2011.5981229
C. Yuan, Y. Y. Lam
This paper presents a novel charge-redistribution successive-approximation register (SAR) analog-to-digital converter (ADC). The proposed ADC is based on a novel capacitive DAC switching scheme which employs unit capacitors for voltage sampling and charge redistribution. Compared with published capacitive DAC which uses the same unit size capacitor, the proposed DAC needs only 33% of the total switches. The proposed 8-bit SAR-ADC is designed in Global foundries 65nm CMOS process. SPICE simulation results show that the average switching energy can be reduced by more than 60% compared with published design. The simulated power consumption of the capacitive DAC is about 110 nW at 1.0 V power supply and 100KS/s. The simulated average power consumption of the ADC is about 2.8 μW.
{"title":"A novel low-voltage low-power SAR ADC for biomedical applications","authors":"C. Yuan, Y. Y. Lam","doi":"10.1109/NEWCAS.2011.5981229","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981229","url":null,"abstract":"This paper presents a novel charge-redistribution successive-approximation register (SAR) analog-to-digital converter (ADC). The proposed ADC is based on a novel capacitive DAC switching scheme which employs unit capacitors for voltage sampling and charge redistribution. Compared with published capacitive DAC which uses the same unit size capacitor, the proposed DAC needs only 33% of the total switches. The proposed 8-bit SAR-ADC is designed in Global foundries 65nm CMOS process. SPICE simulation results show that the average switching energy can be reduced by more than 60% compared with published design. The simulated power consumption of the capacitive DAC is about 110 nW at 1.0 V power supply and 100KS/s. The simulated average power consumption of the ADC is about 2.8 μW.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128376654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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