Pub Date : 2011-06-26DOI: 10.1109/NEWCAS.2011.5981210
N. Yakymets, K. Jabeur, I. O’Connor, S. Le Beux
In this article, a new methodology for mapping applications onto matrix-based nanocomputer architectures is proposed. It takes into account the structural characteristics and connectivity restrictions of cell matrices and can be used (i) for the partitioning and mapping of applications, (ii) for the generation of alternative mapping configurations with required area, power and delay characteristics and (iii) for the comparison of different architectures and adjusting their parameters. The methodology shows significant improvement in routing area (∼36%) and wire width (∼33%) over existing mapping algorithms.
{"title":"Mapping methodology and analysis of matrix-based nanocomputer architectures","authors":"N. Yakymets, K. Jabeur, I. O’Connor, S. Le Beux","doi":"10.1109/NEWCAS.2011.5981210","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981210","url":null,"abstract":"In this article, a new methodology for mapping applications onto matrix-based nanocomputer architectures is proposed. It takes into account the structural characteristics and connectivity restrictions of cell matrices and can be used (i) for the partitioning and mapping of applications, (ii) for the generation of alternative mapping configurations with required area, power and delay characteristics and (iii) for the comparison of different architectures and adjusting their parameters. The methodology shows significant improvement in routing area (∼36%) and wire width (∼33%) over existing mapping algorithms.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128161216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-26DOI: 10.1109/NEWCAS.2011.5981268
Urs A. Muller, S. Tanner, P. Farine
In this paper, the design of a low-noise amplifier (LNA) for a 32×32 pixel microelectrode array (MEA) is presented. Its gain and noise amount to 50 dB and 10μVrms, respectively, at a bandwidth of 66kHz. The LNA consumes less than 85μW. The integrated offset compensation circuit makes the system less sensitive to mismatch and variations in the culture medium biasing voltage. A sample& hold (S&H) buffer stores the amplified input signals locally, thereby realising an electronic shutter function. This allows for simultaneous acquisition of all pixels. The on-chip logic permits individual selection of every single pixel at any time. As a result, regions of interest (ROIs) of any size can be defined. Accordingly, the entire cell culture or subregions can be observed at a high sampling rate. Moreover, each pixel is equipped with a stimulation circuitry. Centered around a programmable SRAM cell, it offers the creation of complex stimulation patterns on the MEA. The entire circuit has been layouted in 180 nm, 3.3V CMOS technology and covers an area of 60×60 μm2.
{"title":"Low-noise amplifier with sample & hold for high-density stimulation and recording of neural signals","authors":"Urs A. Muller, S. Tanner, P. Farine","doi":"10.1109/NEWCAS.2011.5981268","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981268","url":null,"abstract":"In this paper, the design of a low-noise amplifier (LNA) for a 32×32 pixel microelectrode array (MEA) is presented. Its gain and noise amount to 50 dB and 10μVrms, respectively, at a bandwidth of 66kHz. The LNA consumes less than 85μW. The integrated offset compensation circuit makes the system less sensitive to mismatch and variations in the culture medium biasing voltage. A sample& hold (S&H) buffer stores the amplified input signals locally, thereby realising an electronic shutter function. This allows for simultaneous acquisition of all pixels. The on-chip logic permits individual selection of every single pixel at any time. As a result, regions of interest (ROIs) of any size can be defined. Accordingly, the entire cell culture or subregions can be observed at a high sampling rate. Moreover, each pixel is equipped with a stimulation circuitry. Centered around a programmable SRAM cell, it offers the creation of complex stimulation patterns on the MEA. The entire circuit has been layouted in 180 nm, 3.3V CMOS technology and covers an area of 60×60 μm2.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122471897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A spread-spectrum clock generator (SSCG) with self-calibration circuit (SCC) is presented in this paper. By the use of self-calibration scheme, exploited the proposed linear circuit and a SCC, the gain of Kvco can be effectively reduced and the jitter performance is improved. Moreover, the proposed architecture provides an alternative technique for low Kvco instead of the commonly used methods for voltage-control oscillator (VCO) calibration. The SCC-based SSCG ensures phase locking under the process, voltage and temperature (PVT) variations. For spread-spectrum clocking, the digital MASH delta-sigma modulator and a 33-kHz triangular addressor is used. The proposed SSCG generates an output clock of 3 GHz and approximate 5000-ppm down spreading with a triangular-modulated shape. The SSCG has been designed in TSMC 0.18 μm CMOS technology. Operating at a 3-GHz clock rate, the peak-to-peak jitter of non spread-spectrum is 3.85 ps. The electromagnetic interference (EMI) reduction is larger than 20 dB with a triangular-modulated frequency of 3–2.985 GHz.
{"title":"A 3 GHz spread-spectrum clock generator with a self-calibration technique","authors":"Chi-Yang Chang, Cheng-Liang Hung, Yu-Chen Lin, Kuo-Hsing Cheng","doi":"10.1109/NEWCAS.2011.5981284","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981284","url":null,"abstract":"A spread-spectrum clock generator (SSCG) with self-calibration circuit (SCC) is presented in this paper. By the use of self-calibration scheme, exploited the proposed linear circuit and a SCC, the gain of Kvco can be effectively reduced and the jitter performance is improved. Moreover, the proposed architecture provides an alternative technique for low Kvco instead of the commonly used methods for voltage-control oscillator (VCO) calibration. The SCC-based SSCG ensures phase locking under the process, voltage and temperature (PVT) variations. For spread-spectrum clocking, the digital MASH delta-sigma modulator and a 33-kHz triangular addressor is used. The proposed SSCG generates an output clock of 3 GHz and approximate 5000-ppm down spreading with a triangular-modulated shape. The SSCG has been designed in TSMC 0.18 μm CMOS technology. Operating at a 3-GHz clock rate, the peak-to-peak jitter of non spread-spectrum is 3.85 ps. The electromagnetic interference (EMI) reduction is larger than 20 dB with a triangular-modulated frequency of 3–2.985 GHz.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122772313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-26DOI: 10.1109/NEWCAS.2011.5981299
Fu-Chiung Cheng, Chi Chen, Yu-Jai Wu
Quasi-Delay insensitive (QDI) circuits are the most robust and practical circuits that can be built and are resilient to process, temperature and voltage variations. However, QDI circuits suffer from high area overhead due to C-elements, used to prevent timing violation from internal unstable signals. A general optimization scheme to synthesize any Boolean function into our QDI model is proposed and illustrated. The experimental results in FPGAs indicate significant cost reduction over Balsa original design [5–7].
{"title":"An efficient and robust implementation of QDI datapath components","authors":"Fu-Chiung Cheng, Chi Chen, Yu-Jai Wu","doi":"10.1109/NEWCAS.2011.5981299","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981299","url":null,"abstract":"Quasi-Delay insensitive (QDI) circuits are the most robust and practical circuits that can be built and are resilient to process, temperature and voltage variations. However, QDI circuits suffer from high area overhead due to C-elements, used to prevent timing violation from internal unstable signals. A general optimization scheme to synthesize any Boolean function into our QDI model is proposed and illustrated. The experimental results in FPGAs indicate significant cost reduction over Balsa original design [5–7].","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132577308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-26DOI: 10.1109/NEWCAS.2011.5981336
Zhiqun Li, Yawei Jiang, Haiyong Shu, Ningbing Hou
A fully integrated integer-N frequency synthesizer has been designed and implemented in 0.18μm RF CMOS technology for low intermediate frequency (IF) ZigBee transceiver application. It incorporates an automatic frequency calibration (AFC) loop to extend frequency tuning range. In-phase and quadrature (IQ) signals are generated by a divide-by-two frequency divider at the output of PLL. It consumes 11mA at 1.8V. The measured phase noise is −118dBc/Hz and −135dBc/Hz at the offset of 1MHz and 3MHz from 2.405GHz carrier respectively. The measured reference-spur at 2MHz offset from 2.405GHz carrier is −64dBc.
{"title":"A 5-GHz frequency synthesizer with AFC for low IF ZigBee transceiver applications","authors":"Zhiqun Li, Yawei Jiang, Haiyong Shu, Ningbing Hou","doi":"10.1109/NEWCAS.2011.5981336","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981336","url":null,"abstract":"A fully integrated integer-N frequency synthesizer has been designed and implemented in 0.18μm RF CMOS technology for low intermediate frequency (IF) ZigBee transceiver application. It incorporates an automatic frequency calibration (AFC) loop to extend frequency tuning range. In-phase and quadrature (IQ) signals are generated by a divide-by-two frequency divider at the output of PLL. It consumes 11mA at 1.8V. The measured phase noise is −118dBc/Hz and −135dBc/Hz at the offset of 1MHz and 3MHz from 2.405GHz carrier respectively. The measured reference-spur at 2MHz offset from 2.405GHz carrier is −64dBc.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124293458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-26DOI: 10.1109/NEWCAS.2011.5981302
Jérémie Hamon, L. Fesquet
This paper presents the design of configurable digital oscillators based on Self-Timed Rings. The oscillation frequencies are easily programmable and the oscillation mode, which can be peculiar in such kind of oscillator, can be controlled. In addition, a method to enhance the robustness to process variability is proposed. A test chip has been designed in CMOS 130 nm technology and the experimental results validate the relevance of our approach.
{"title":"Robust and programmable Self-Timed Ring oscillators","authors":"Jérémie Hamon, L. Fesquet","doi":"10.1109/NEWCAS.2011.5981302","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981302","url":null,"abstract":"This paper presents the design of configurable digital oscillators based on Self-Timed Rings. The oscillation frequencies are easily programmable and the oscillation mode, which can be peculiar in such kind of oscillator, can be controlled. In addition, a method to enhance the robustness to process variability is proposed. A test chip has been designed in CMOS 130 nm technology and the experimental results validate the relevance of our approach.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124404621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-26DOI: 10.1109/NEWCAS.2011.5981249
F. Paugnat, K. Morin-Allory, L. Fesquet
Since the emergence of Systems on Chip (SoC), designing is more challenging, especially when the system integrates analog and digital parts. Codesigning is now a necessity to simulate and validate successfully a complex SoC. This paper describes a refinement process for top-down analog and mixed-signal designs. The most abstracted levels are required to have a coherent codesign at the system level, but they are still missing in the current analog design-flows. The refinement steps from the high level down to the hardware implementation levels are described in the SystemC framework and illustrated by an example that exploits the cosimulation capabilities of SystemC-AMS.
{"title":"A refinement process for top-down mixed-signal designs thanks to SystemC-AMS","authors":"F. Paugnat, K. Morin-Allory, L. Fesquet","doi":"10.1109/NEWCAS.2011.5981249","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981249","url":null,"abstract":"Since the emergence of Systems on Chip (SoC), designing is more challenging, especially when the system integrates analog and digital parts. Codesigning is now a necessity to simulate and validate successfully a complex SoC. This paper describes a refinement process for top-down analog and mixed-signal designs. The most abstracted levels are required to have a coherent codesign at the system level, but they are still missing in the current analog design-flows. The refinement steps from the high level down to the hardware implementation levels are described in the SystemC framework and illustrated by an example that exploits the cosimulation capabilities of SystemC-AMS.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133457913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-26DOI: 10.1109/NEWCAS.2011.5981220
Martin Dubois, M. Boukadoum
With the advent of increasingly higher numbers of processors on-chip, task scheduling has become an important concern in system design, and research in this area has produced substantial and diversified knowledge. As a result, the efficient management and taping of this knowledge has become a concern in itself. This paper addresses the issue of how to effectively extract performance information about a scheduling algorithm in the context of a set of applications, by learning the association rules between the applications' attributes and the algorithms' performance metrics. The new methodology that is presented serves to both increase the designer's knowledge about a particular scheduling algorithm and compare algorithms.
{"title":"Association rules learning technique for knowledge mining about scheduling algorithm performance","authors":"Martin Dubois, M. Boukadoum","doi":"10.1109/NEWCAS.2011.5981220","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981220","url":null,"abstract":"With the advent of increasingly higher numbers of processors on-chip, task scheduling has become an important concern in system design, and research in this area has produced substantial and diversified knowledge. As a result, the efficient management and taping of this knowledge has become a concern in itself. This paper addresses the issue of how to effectively extract performance information about a scheduling algorithm in the context of a set of applications, by learning the association rules between the applications' attributes and the algorithms' performance metrics. The new methodology that is presented serves to both increase the designer's knowledge about a particular scheduling algorithm and compare algorithms.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"193 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116668913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-26DOI: 10.1109/NEWCAS.2011.5981330
M. Bounouar, F. Calmon, A. Beaumont, M. Guilmain, W. Xuan, S. Ecoffey, D. Drouin
A novel analytical and compact model of Single Electron Transistor (SET) is developed and implemented in Verilog-A language for use in hybrid SET-CMOS logic circuit design. The model is based on the steady state Master-Equation (ME). The implementation of this original and simple model, taking into account physical characteristics of tunnel junctions and the thermionic emission, has faithfully reproduced the behavior of metallic SET operating at room temperature. The hybrid SET-CMOS universal logic gate cell is analyzed to illustrate the efficiency of this compact SET model.
{"title":"Single Electron Transistor analytical model for hybrid circuit design","authors":"M. Bounouar, F. Calmon, A. Beaumont, M. Guilmain, W. Xuan, S. Ecoffey, D. Drouin","doi":"10.1109/NEWCAS.2011.5981330","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981330","url":null,"abstract":"A novel analytical and compact model of Single Electron Transistor (SET) is developed and implemented in Verilog-A language for use in hybrid SET-CMOS logic circuit design. The model is based on the steady state Master-Equation (ME). The implementation of this original and simple model, taking into account physical characteristics of tunnel junctions and the thermionic emission, has faithfully reproduced the behavior of metallic SET operating at room temperature. The hybrid SET-CMOS universal logic gate cell is analyzed to illustrate the efficiency of this compact SET model.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114992897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-26DOI: 10.1109/NEWCAS.2011.5981202
M. Melzi, A. Ouldali
The probability hypothesis density (PHD) is the first order statistical moment of the multiple target posterior density; the PHD recursion involves multiple integrals that generally have no closed form solutions. A SMC implementation of the PHD filter has been proposed to tackle the issue of joint estimating the number of targets and their states. However, because the state transition does not take into account the most recent observation, the particles drawn from prior transition may have very low likelihood and their contributions to the posterior estimation become negligible. In this paper, we propose a novel algorithm named Unscented Kalman Particle PHD filter (UK-P-PHD). It consists of a P-PHD filter that uses an Unscented Kalman filter to generate the importance proposal distribution; the UKF allows the P-PHD filter to incorporate the latest observations into a prior updating routine and thus, generates proposal distributions that match the true posterior more closely. Simulation shows that the proposed filter outperforms the P-PHD filter.
{"title":"Joint multiple target tracking and classification using the Unscented Kalman Particle PHD filter","authors":"M. Melzi, A. Ouldali","doi":"10.1109/NEWCAS.2011.5981202","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981202","url":null,"abstract":"The probability hypothesis density (PHD) is the first order statistical moment of the multiple target posterior density; the PHD recursion involves multiple integrals that generally have no closed form solutions. A SMC implementation of the PHD filter has been proposed to tackle the issue of joint estimating the number of targets and their states. However, because the state transition does not take into account the most recent observation, the particles drawn from prior transition may have very low likelihood and their contributions to the posterior estimation become negligible. In this paper, we propose a novel algorithm named Unscented Kalman Particle PHD filter (UK-P-PHD). It consists of a P-PHD filter that uses an Unscented Kalman filter to generate the importance proposal distribution; the UKF allows the P-PHD filter to incorporate the latest observations into a prior updating routine and thus, generates proposal distributions that match the true posterior more closely. Simulation shows that the proposed filter outperforms the P-PHD filter.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124477513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：