In this paper, we propose an FPGA implementation of a genetic algorithm (GA) for linear and nonlinear auto regressive moving average (ARMA) model parameters identification. The GA features specifically designed genetic operators for adaptive filtering applications. The design was implemented using very low bit-wordlength fixed-point representation, where only 6-bit wordlength arithmetic was used. The implementation experiments show high parameters identification capabilities and low footprint.
{"title":"FPGA based implementation of a genetic algorithm for ARMA model parameters identification","authors":"H. Merabti, D. Massicotte","doi":"10.1145/2591513.2591579","DOIUrl":"https://doi.org/10.1145/2591513.2591579","url":null,"abstract":"In this paper, we propose an FPGA implementation of a genetic algorithm (GA) for linear and nonlinear auto regressive moving average (ARMA) model parameters identification. The GA features specifically designed genetic operators for adaptive filtering applications. The design was implemented using very low bit-wordlength fixed-point representation, where only 6-bit wordlength arithmetic was used. The implementation experiments show high parameters identification capabilities and low footprint.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124534332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Wire sizing can be used to reduce the delays of critical nets. However, because of the forbidden pitch issue in sub-20nm designs, wide wires may no longer be an attractive solution because of the restrictive wire spacing requirement from advanced lithography. In this work, we investigate the suitability of the parallel wiring technique, in which multiple parallel wires are used to route the same net, as an alternative to routing a net using a single wide wire. In particular, we study the trade offs between parasitics, timing, power, and routing resources. Our study reveals that wire sizing using both parallel wires and wide wires can be advantageous. Moreover, if high layout densities are required, parallel wiring can be a viable approach in solving timing problems for sub-20nm designs.
{"title":"A study on the use of parallel wiring techniques for sub-20nm designs","authors":"Rickard Ewetz, Wen-Hao Liu, Kai-Yuan Chao, Ting-Chi Wang, Cheng-Kok Koh","doi":"10.1145/2591513.2591588","DOIUrl":"https://doi.org/10.1145/2591513.2591588","url":null,"abstract":"Wire sizing can be used to reduce the delays of critical nets. However, because of the forbidden pitch issue in sub-20nm designs, wide wires may no longer be an attractive solution because of the restrictive wire spacing requirement from advanced lithography. In this work, we investigate the suitability of the parallel wiring technique, in which multiple parallel wires are used to route the same net, as an alternative to routing a net using a single wide wire. In particular, we study the trade offs between parasitics, timing, power, and routing resources. Our study reveals that wire sizing using both parallel wires and wide wires can be advantageous. Moreover, if high layout densities are required, parallel wiring can be a viable approach in solving timing problems for sub-20nm designs.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132923898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Moriwaki, H. Maekawa, A. Ogiwara, Minoru Watanabe
Optically reconfigurable gate arrays (ORGAs) have been developed to achieve a high-performance FPGA with numerous configuration contexts. In the architecture, an optical memory technology or a holographic memory technology has been introduced so that the architecture can have numerous configuration contexts and high-speed reconfiguration capability. Results show that the architecture can achieve a large virtual gate count that is much larger than those of currently available VLSIs. To date, ORGAs with a spatially multiplex holographic memory have been reported. However, the spatially multiplexed holographic memory can only have a small number of configuration contexts, which are limited to about 256 configuration contexts. To implement more than a million configuration contexts, an angle-multiplex holographic memory must be used. However, no ORGA with an angle multiplex holographic memory that can sufficiently exploit the huge storage capacity of a holographic memory has ever been reported. Therefore, this paper presents a proposal of a novel ORGA with an angle-multiplexed holographic memory. The architecture can open the possibility of providing a million configuration contexts for a multi-context FPGA.
{"title":"Optically reconfigurable gate array with an angle-multiplexed holographic memory","authors":"R. Moriwaki, H. Maekawa, A. Ogiwara, Minoru Watanabe","doi":"10.1145/2591513.2591597","DOIUrl":"https://doi.org/10.1145/2591513.2591597","url":null,"abstract":"Optically reconfigurable gate arrays (ORGAs) have been developed to achieve a high-performance FPGA with numerous configuration contexts. In the architecture, an optical memory technology or a holographic memory technology has been introduced so that the architecture can have numerous configuration contexts and high-speed reconfiguration capability. Results show that the architecture can achieve a large virtual gate count that is much larger than those of currently available VLSIs. To date, ORGAs with a spatially multiplex holographic memory have been reported. However, the spatially multiplexed holographic memory can only have a small number of configuration contexts, which are limited to about 256 configuration contexts. To implement more than a million configuration contexts, an angle-multiplex holographic memory must be used. However, no ORGA with an angle multiplex holographic memory that can sufficiently exploit the huge storage capacity of a holographic memory has ever been reported. Therefore, this paper presents a proposal of a novel ORGA with an angle-multiplexed holographic memory. The architecture can open the possibility of providing a million configuration contexts for a multi-context FPGA.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"28 13","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131639131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With reduction of minimum feature size, the minimum implant area (MinIA) constraint is emerging as a new challenge for the physical implementation flow in sub-22nm technology. In particular, the MinIA constraint induces a new problem formulation wherein gate sizing and V_t-swapping must now be linked closely with detailed placement changes. To solve this new problem, we propose heuristic methods that fix MinIA violations and reduce power with gate sizing while minimizing placement perturbation to avoid creating extra timing violations. Compared to recent versions of commercial P&R tools, our methodologies achieve significant reductions (up to 100%) in the number of MinIA violations under timing/power constraints.
{"title":"Minimum implant area-aware gate sizing and placement","authors":"A. Kahng, Hyein Lee","doi":"10.1145/2591513.2591542","DOIUrl":"https://doi.org/10.1145/2591513.2591542","url":null,"abstract":"With reduction of minimum feature size, the minimum implant area (MinIA) constraint is emerging as a new challenge for the physical implementation flow in sub-22nm technology. In particular, the MinIA constraint induces a new problem formulation wherein gate sizing and V_t-swapping must now be linked closely with detailed placement changes. To solve this new problem, we propose heuristic methods that fix MinIA violations and reduce power with gate sizing while minimizing placement perturbation to avoid creating extra timing violations. Compared to recent versions of commercial P&R tools, our methodologies achieve significant reductions (up to 100%) in the number of MinIA violations under timing/power constraints.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123311097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Multiprocessor System-on-Chip (MPSoC) platforms face some of the most demanding security concerns, as they process, store, and communicate sensitive information using third-party intellectual property (3PIP) cores. The trend of outsourcing design and fabrication strongly questions the assumption of 3PIP components being trustworthy. While existing research focuses on addressing hardware trojans in individual IPs, this paper improves MPSoC security from another perspective. Specifically, our goal is to prevent trojans in malicious IPs from triggering each other and leading to severe system-wide degradation in security and reliability. We propose to impose trojan isolation constraints during static task scheduling, ensuring that all legal communications on the target MPSoC are between IPs of different types. This in turn enables the runtime system to monitor and detect undesired communication paths, if any. We furthermore pose the security-constrained MPSoC task scheduling as a multi-dimensional optimization problem, and solve it through Integer Linear Programming (ILP), thus minimizing the associated performance, power, and hardware overhead. The results show that trojan isolation can be achieved within one extra vendor and nearly no performance overhead.
{"title":"Exploiting heterogeneity in MPSoCs to prevent potential trojan propagation across malicious IPs","authors":"Chen Liu, Chengmo Yang","doi":"10.1145/2591513.2591595","DOIUrl":"https://doi.org/10.1145/2591513.2591595","url":null,"abstract":"Multiprocessor System-on-Chip (MPSoC) platforms face some of the most demanding security concerns, as they process, store, and communicate sensitive information using third-party intellectual property (3PIP) cores. The trend of outsourcing design and fabrication strongly questions the assumption of 3PIP components being trustworthy. While existing research focuses on addressing hardware trojans in individual IPs, this paper improves MPSoC security from another perspective. Specifically, our goal is to prevent trojans in malicious IPs from triggering each other and leading to severe system-wide degradation in security and reliability. We propose to impose trojan isolation constraints during static task scheduling, ensuring that all legal communications on the target MPSoC are between IPs of different types. This in turn enables the runtime system to monitor and detect undesired communication paths, if any. We furthermore pose the security-constrained MPSoC task scheduling as a multi-dimensional optimization problem, and solve it through Integer Linear Programming (ILP), thus minimizing the associated performance, power, and hardware overhead. The results show that trojan isolation can be achieved within one extra vendor and nearly no performance overhead.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115822602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ubiquitous access to computers, cell phones, internet, personal digital devices, cameras and TV can be attributed to advances in the very large scale integration (VLSI) technology and the advances in circuit design to operate circuits at Gigahertz rates. One of the mysteries that we have not been able to unravel is the understanding of how the brain works from different perspectives. Reverse engineering the brain has been identified as one of the grand challenge problems by the National Academies. Advances in sensor technologies and imaging modalities such as electroencephalogram (EEG), intra-cranial electroencephalogram (iEEG), magnetoencephalogram (MEG), and magnetic resonance imaging (MRI) allow us to collect data from hundreds of electrodes from the brain at sample rates ranging from 256 Hz to 15kHz. These data can be key to not only understanding brain functioning and brain connectivity at macro and micro levels in healthy subjects but also in identifying patients with neurological and mental disorder. Extracting the appropriate biomarkers using spectral-temporal-spatial signal processing approaches and classifying states using machine learning approaches can assist clinicians in predicting and detecting seizures in epileptic patients, and in identifying patients with mental disorder such as schizophrenia, depression and personality disorder. The biomarkers can be tracked to design personalized therapy and effectiveness of therapy by closed loop drug delivery or closed loop neuromodulation, i.e., brain stimulation either by invasive or non-invasive means using electrical or magnetic stimulation. High-performance VLSI system design is critical to not-only increasing battery life of VLSI chips for neuromodulation but also for reducing computation time by orders of magnitude in analyzing MRI signals. Another grand challenge problem identified by the National Academies is Advanced Health Informatics. Analysis of health data is key to monitoring biomarkers and delivering drugs as needed. VLSI system design of biomarkers and disease state classification is again critical in improving the health and quality of life of human beings. In this talk, I will highlight the emerging opportunities in high-performance low-power VLSI system design for neurocomputing and health informatics at various scales. At macroscale, the goal is to design small low-power implantable or wearable devices that can be used to monitor biomarkers and trigger an alarm signal to alert an abnormal state of the brain such as an impending seizure. At microscale, extracting thousands of connections from structural and functional MRI can require many hours or even a day for one subject and one set of parameters using parallel computers. The challenge here is to design parallel multicore computer architectures and compiler tools that can reduce the time for microscale analysis of MRI to an hour or less. I will describe research in my group in use of signal processing and machine lea
{"title":"VLSI systems for neurocomputing and health informatics","authors":"K. Parhi","doi":"10.1145/2591513.2597168","DOIUrl":"https://doi.org/10.1145/2591513.2597168","url":null,"abstract":"Ubiquitous access to computers, cell phones, internet, personal digital devices, cameras and TV can be attributed to advances in the very large scale integration (VLSI) technology and the advances in circuit design to operate circuits at Gigahertz rates. One of the mysteries that we have not been able to unravel is the understanding of how the brain works from different perspectives. Reverse engineering the brain has been identified as one of the grand challenge problems by the National Academies. Advances in sensor technologies and imaging modalities such as electroencephalogram (EEG), intra-cranial electroencephalogram (iEEG), magnetoencephalogram (MEG), and magnetic resonance imaging (MRI) allow us to collect data from hundreds of electrodes from the brain at sample rates ranging from 256 Hz to 15kHz. These data can be key to not only understanding brain functioning and brain connectivity at macro and micro levels in healthy subjects but also in identifying patients with neurological and mental disorder. Extracting the appropriate biomarkers using spectral-temporal-spatial signal processing approaches and classifying states using machine learning approaches can assist clinicians in predicting and detecting seizures in epileptic patients, and in identifying patients with mental disorder such as schizophrenia, depression and personality disorder. The biomarkers can be tracked to design personalized therapy and effectiveness of therapy by closed loop drug delivery or closed loop neuromodulation, i.e., brain stimulation either by invasive or non-invasive means using electrical or magnetic stimulation. High-performance VLSI system design is critical to not-only increasing battery life of VLSI chips for neuromodulation but also for reducing computation time by orders of magnitude in analyzing MRI signals. Another grand challenge problem identified by the National Academies is Advanced Health Informatics. Analysis of health data is key to monitoring biomarkers and delivering drugs as needed. VLSI system design of biomarkers and disease state classification is again critical in improving the health and quality of life of human beings. In this talk, I will highlight the emerging opportunities in high-performance low-power VLSI system design for neurocomputing and health informatics at various scales. At macroscale, the goal is to design small low-power implantable or wearable devices that can be used to monitor biomarkers and trigger an alarm signal to alert an abnormal state of the brain such as an impending seizure. At microscale, extracting thousands of connections from structural and functional MRI can require many hours or even a day for one subject and one set of parameters using parallel computers. The challenge here is to design parallel multicore computer architectures and compiler tools that can reduce the time for microscale analysis of MRI to an hour or less. I will describe research in my group in use of signal processing and machine lea","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115644522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Driven by the trends of increasing core-count and bandwidth-wall problem, the size of last level caches (LLCs) has greatly increased. Since SRAM consumes high leakage power, researchers have explored use of non-volatile memories (NVMs) for designing caches as they provide high density and consume low leakage power. However, since NVMs have low write-endurance and the existing cache management policies are write variation-unaware, effective wear-leveling techniques are required for achieving reasonable cache lifetimes using NVMs. We present WriteSmoothing, a technique for mitigating intra-set write variation in NVM caches. WriteSmoothing logically divides the cache-sets into multiple modules. For each module, WriteSmoothing collectively records number of writes in each way for any of the sets. It then periodically makes most frequently written ways in a module unavailable to shift the write-pressure to other ways in the sets of the module. Extensive simulation results have shown that on average, for single and dual-core system configurations, WriteSmoothing improves cache lifetime by 2.17X and 2.75X, respectively. Also, its implementation overhead is small and it works well for a wide range of algorithm and system parameters.
{"title":"WriteSmoothing: improving lifetime of non-volatile caches using intra-set wear-leveling","authors":"Sparsh Mittal, J. Vetter, Dong Li","doi":"10.1145/2591513.2591525","DOIUrl":"https://doi.org/10.1145/2591513.2591525","url":null,"abstract":"Driven by the trends of increasing core-count and bandwidth-wall problem, the size of last level caches (LLCs) has greatly increased. Since SRAM consumes high leakage power, researchers have explored use of non-volatile memories (NVMs) for designing caches as they provide high density and consume low leakage power. However, since NVMs have low write-endurance and the existing cache management policies are write variation-unaware, effective wear-leveling techniques are required for achieving reasonable cache lifetimes using NVMs. We present WriteSmoothing, a technique for mitigating intra-set write variation in NVM caches. WriteSmoothing logically divides the cache-sets into multiple modules. For each module, WriteSmoothing collectively records number of writes in each way for any of the sets. It then periodically makes most frequently written ways in a module unavailable to shift the write-pressure to other ways in the sets of the module. Extensive simulation results have shown that on average, for single and dual-core system configurations, WriteSmoothing improves cache lifetime by 2.17X and 2.75X, respectively. Also, its implementation overhead is small and it works well for a wide range of algorithm and system parameters.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127178136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we propose a novel hybrid design-time and run-time framework for allocating and scheduling applications in multi-core embedded systems with solar energy harvesting. Due to limited energy availability at run-time, our framework offloads scheduling complexity to design time by creating energy-efficient schedule templates for varying energy budget levels, which are selected at run-time in a manner that is contingent on the available harvested energy and executed with a lightweight slack reclamation scheme that extracts additional energy savings. Our experimental results show that the proposed framework produces energy-efficient and dependency-aware schedules to execute applications under varying and stringent energy constraints, with 23-40% lower miss rates than in prior works on harvesting energy-aware scheduling.
{"title":"A hybrid framework for application allocation and scheduling in multicore systems with energy harvesting","authors":"Yi Xiang, S. Pasricha","doi":"10.1145/2591513.2591527","DOIUrl":"https://doi.org/10.1145/2591513.2591527","url":null,"abstract":"In this paper, we propose a novel hybrid design-time and run-time framework for allocating and scheduling applications in multi-core embedded systems with solar energy harvesting. Due to limited energy availability at run-time, our framework offloads scheduling complexity to design time by creating energy-efficient schedule templates for varying energy budget levels, which are selected at run-time in a manner that is contingent on the available harvested energy and executed with a lightweight slack reclamation scheme that extracts additional energy savings. Our experimental results show that the proposed framework produces energy-efficient and dependency-aware schedules to execute applications under varying and stringent energy constraints, with 23-40% lower miss rates than in prior works on harvesting energy-aware scheduling.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123216501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Embedded systems often implement safety critical applications making security a more and more important aspect in their design. Control-Flow Integrity (CFI) attacks are used to modify program behavior and can lead to learn valuable information directly or indirectly by perturbing a system and creating failures. Although CFI attacks are well-known in computer systems, they have been recently shown to be practical and feasible on embedded systems as well. In this context, CFI checks are mainly used to detect unintended software behaviors while very few works address non programmable hardware component monitoring. In this paper, we present a hardware-assisted paradigm to enhance embedded system security by detecting and preventing unintended hardware behavior. We propose a design approach that designs on-chip monitors (OCM) during High-Level Synthesis (HLS) of hardware accelerators (HWacc). Synthesis of OCM is introduced as a set of steps realized concurrently to the HLS flow of HWacc. Automatically generated OCM checks at runtime both the input/output timing behavior and the control flow of the monitored HWacc. Experimental results show the interest of the proposed approach: the error coverage on the control flow ranges from 99.75% to 100% while in average the OCM area overhead is less than 10%, the clock period overhead is at worst less than 5% and impact on the synthesis time is negligible.
{"title":"A design approach to automatically generate on-chip monitors during high-level synthesis of hardware accelerator","authors":"M. B. Hammouda, P. Coussy, Loïc Lagadec","doi":"10.1145/2591513.2591521","DOIUrl":"https://doi.org/10.1145/2591513.2591521","url":null,"abstract":"Embedded systems often implement safety critical applications making security a more and more important aspect in their design. Control-Flow Integrity (CFI) attacks are used to modify program behavior and can lead to learn valuable information directly or indirectly by perturbing a system and creating failures. Although CFI attacks are well-known in computer systems, they have been recently shown to be practical and feasible on embedded systems as well. In this context, CFI checks are mainly used to detect unintended software behaviors while very few works address non programmable hardware component monitoring. In this paper, we present a hardware-assisted paradigm to enhance embedded system security by detecting and preventing unintended hardware behavior. We propose a design approach that designs on-chip monitors (OCM) during High-Level Synthesis (HLS) of hardware accelerators (HWacc). Synthesis of OCM is introduced as a set of steps realized concurrently to the HLS flow of HWacc. Automatically generated OCM checks at runtime both the input/output timing behavior and the control flow of the monitored HWacc. Experimental results show the interest of the proposed approach: the error coverage on the control flow ranges from 99.75% to 100% while in average the OCM area overhead is less than 10%, the clock period overhead is at worst less than 5% and impact on the synthesis time is negligible.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114342005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper a design optimization flow is proposed for memristor-based oscillators using the Gravitational Search Algorithm. This paper presents for the first time a memristor behavioral model in the Simscape physical modeling language. Using this model, a memristor based Wien oscillator is characterized within the Simscape framework. The oscillation frequency and power consumption of the oscillator for different configurations are explored.
{"title":"Simscape design flow for memristor based programmable oscillators","authors":"E. Agu, S. Mohanty, E. Kougianos, M. Gautam","doi":"10.1145/2591513.2591545","DOIUrl":"https://doi.org/10.1145/2591513.2591545","url":null,"abstract":"In this paper a design optimization flow is proposed for memristor-based oscillators using the Gravitational Search Algorithm. This paper presents for the first time a memristor behavioral model in the Simscape physical modeling language. Using this model, a memristor based Wien oscillator is characterized within the Simscape framework. The oscillation frequency and power consumption of the oscillator for different configurations are explored.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"192 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132664918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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