Reliability issue, especially from transient errors due to scaling IC technology, low voltage supply, high frequency and heavy thermal effects, particles emission etc, has become a challenge for NoC design. Focus on this problem, an effective Reliability-Aware Arbitration Strategy simplified as RAPA, is proposed in this paper to decide which flits should be prioritized in the network transmission for higher application-level reliability. Different from pervious performance-oriented arbitration strategies, it includes the application-level reliability requirement to determine the reliability priority ranking. Flits patching mechanism is also used for avoiding starvation. The evaluation metric is redefined to emphasizing application-level reliability. Finally, we verify the reliability based prioritization policy on cycle accurate platform. And the simulation results show that the averaged successful delivery rate is upgraded from three nine of round robin (RR), old age based arbitration(OA) to five nine of our method RAPA. Especially, 67.15%, 41.83% reliability improvement in rest unreliable space on average are obtained over typical RR policy and OA based arbitration policy respectively with guaranteed performance.
{"title":"RAPA: reliability-aware priority arbitration strategy for network on chip","authors":"Jiajia Jiao, Yuzhuo Fu","doi":"10.1145/2206781.2206807","DOIUrl":"https://doi.org/10.1145/2206781.2206807","url":null,"abstract":"Reliability issue, especially from transient errors due to scaling IC technology, low voltage supply, high frequency and heavy thermal effects, particles emission etc, has become a challenge for NoC design. Focus on this problem, an effective Reliability-Aware Arbitration Strategy simplified as RAPA, is proposed in this paper to decide which flits should be prioritized in the network transmission for higher application-level reliability. Different from pervious performance-oriented arbitration strategies, it includes the application-level reliability requirement to determine the reliability priority ranking. Flits patching mechanism is also used for avoiding starvation. The evaluation metric is redefined to emphasizing application-level reliability. Finally, we verify the reliability based prioritization policy on cycle accurate platform. And the simulation results show that the averaged successful delivery rate is upgraded from three nine of round robin (RR), old age based arbitration(OA) to five nine of our method RAPA. Especially, 67.15%, 41.83% reliability improvement in rest unreliable space on average are obtained over typical RR policy and OA based arbitration policy respectively with guaranteed performance.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114095763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents techniques to determine the optimal reverse body bias (RBB) voltage to minimize leakage currents in modern nanoscale CMOS technology. The proposed self-adaptive RBB system finds the optimum reverse body bias voltage for minimal leakage power adaptively by comparing subthreshold leakage current (ISUBTH), gate tunneling leakage (IGATE), and band-to-band tunneling leakage currents (IBTBT) in standby mode. The proposed circuit has been designed and tested using 65nm bulk CMOS technology at 25ºC under a supply voltage of less than 1V. The optimal RBB was achieved at -0.372V with 1.2% error in the test case of the paper, and the simulation result shows that it is possible to reduce the total leakage current significantly as much as 86% of the total leakage using the proposed circuit techniques.
{"title":"Self adaptive body biasing scheme for leakage power reduction in nanoscale CMOS circuit","authors":"Jing Yang, Yong-Bin Kim","doi":"10.1145/2206781.2206811","DOIUrl":"https://doi.org/10.1145/2206781.2206811","url":null,"abstract":"This paper presents techniques to determine the optimal reverse body bias (RBB) voltage to minimize leakage currents in modern nanoscale CMOS technology. The proposed self-adaptive RBB system finds the optimum reverse body bias voltage for minimal leakage power adaptively by comparing subthreshold leakage current (ISUBTH), gate tunneling leakage (IGATE), and band-to-band tunneling leakage currents (IBTBT) in standby mode. The proposed circuit has been designed and tested using 65nm bulk CMOS technology at 25ºC under a supply voltage of less than 1V. The optimal RBB was achieved at -0.372V with 1.2% error in the test case of the paper, and the simulation result shows that it is possible to reduce the total leakage current significantly as much as 86% of the total leakage using the proposed circuit techniques.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121178995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Wireless Network-on-Chip (NoC) architectures have emerged as an enabling solution to design scalable NoC fabrics for massive many-core chips. However, such massive levels of integration of Intellectual Property (IP) cores make the chips vulnerable to malicious intrusions from untrustworthy processes or vendors. Hence, resilience to various types of hardware security threats is imperative in future many-core chips. In this paper we develop a design methodology to increase the resilience of a wireless NoC to Denial-of-Service (DoS) attacks. We demonstrate that the proposed architecture can sustain higher data transfer rates at lower energy dissipation with the spread of DoS attacks compared to conventional mesh based NoCs.
{"title":"A denial-of-service resilient wireless NoC architecture","authors":"A. Ganguly, M. Y. Ahmed, Anuroop Vidapalapati","doi":"10.1145/2206781.2206844","DOIUrl":"https://doi.org/10.1145/2206781.2206844","url":null,"abstract":"Wireless Network-on-Chip (NoC) architectures have emerged as an enabling solution to design scalable NoC fabrics for massive many-core chips. However, such massive levels of integration of Intellectual Property (IP) cores make the chips vulnerable to malicious intrusions from untrustworthy processes or vendors. Hence, resilience to various types of hardware security threats is imperative in future many-core chips. In this paper we develop a design methodology to increase the resilience of a wireless NoC to Denial-of-Service (DoS) attacks. We demonstrate that the proposed architecture can sustain higher data transfer rates at lower energy dissipation with the spread of DoS attacks compared to conventional mesh based NoCs.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131386426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Current commercial systems on chip (SoC) designs integrate an increasingly large number of pre-designed cores and their number is predicted to increase significantly in the near future. Specifically, molecular-scale computing will allow single or even multiple order-of-magnitude improvements in device densities. In the design of high-performance massive multi-core chips, power and temperature have become dominant constraints. Increased power consumption can raise chip temperature,which in turn can decrease chip reliability and performance and increase cooling costs.The new, ensuing possibilities in terms of single chip integration call for new paradigms, architectures, and infrastructures for high bandwidth and low-power interconnects. In this paper we demonstrate how small-world Network-on-Chip (NoC) architectures with long-range wireless links enable design of energy and thermally efficient sustainable multi-core platforms.
{"title":"Sustainable multi-core architecture with on-chip wireless links","authors":"Jacob Murray, John Klingner, P. Pande, B. Shirazi","doi":"10.1145/2206781.2206845","DOIUrl":"https://doi.org/10.1145/2206781.2206845","url":null,"abstract":"Current commercial systems on chip (SoC) designs integrate an increasingly large number of pre-designed cores and their number is predicted to increase significantly in the near future. Specifically, molecular-scale computing will allow single or even multiple order-of-magnitude improvements in device densities. In the design of high-performance massive multi-core chips, power and temperature have become dominant constraints. Increased power consumption can raise chip temperature,which in turn can decrease chip reliability and performance and increase cooling costs.The new, ensuing possibilities in terms of single chip integration call for new paradigms, architectures, and infrastructures for high bandwidth and low-power interconnects. In this paper we demonstrate how small-world Network-on-Chip (NoC) architectures with long-range wireless links enable design of energy and thermally efficient sustainable multi-core platforms.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131640184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Nicholas Tuzzio, K. Xiao, Xuehui Zhang, M. Tehranipoor
The counterfeiting of integrated circuits (ICs) has become a major issue for the electronics industry. Counterfeit ICs that find their way into the supply chains of critical applications can have a major impact on the security and reliability of those systems. This paper presents a new method for uniquely identifying ICs through path delay analysis. There is no overhead in terms of area, timing, or power for this method, since it extracts the intrinsic path delay variation information of the IC. Simulation results from 90nm technology and experimental results from 90nm FPGAs demonstrate the effectiveness of our technique.
{"title":"A zero-overhead IC identification technique using clock sweeping and path delay analysis","authors":"Nicholas Tuzzio, K. Xiao, Xuehui Zhang, M. Tehranipoor","doi":"10.1145/2206781.2206806","DOIUrl":"https://doi.org/10.1145/2206781.2206806","url":null,"abstract":"The counterfeiting of integrated circuits (ICs) has become a major issue for the electronics industry. Counterfeit ICs that find their way into the supply chains of critical applications can have a major impact on the security and reliability of those systems. This paper presents a new method for uniquely identifying ICs through path delay analysis. There is no overhead in terms of area, timing, or power for this method, since it extracts the intrinsic path delay variation information of the IC. Simulation results from 90nm technology and experimental results from 90nm FPGAs demonstrate the effectiveness of our technique.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125063737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Donato, Fabio Cremona, Warren Jin, R. I. Bahar, W. Patterson, A. Zaslavsky, J. Mundy
Nanoscale circuits operating at sub-threshold voltages are affected by growing impact of random telegraph signal (RTS) and thermal noise. Given the low operational voltages and subsequently lower noise margins, these noise phenomena are capable of changing the value of some of the nodes in the circuit, compromising the reliability of the computation. We propose a method for improving noise-tolerance by selectively applying feed-forward reinforcement to circuits based on use of existing invariant relationships. As reinforcement mechanism, we used a modification of the standard CMOS gates based on the Schmitt trigger circuit. SPICE simulations show our solution offers better noise immunity than both standard CMOS and fully reinforced circuits, with limited area and power overhead.
{"title":"A noise-immune sub-threshold circuit design based on selective use of Schmitt-trigger logic","authors":"M. Donato, Fabio Cremona, Warren Jin, R. I. Bahar, W. Patterson, A. Zaslavsky, J. Mundy","doi":"10.1145/2206781.2206792","DOIUrl":"https://doi.org/10.1145/2206781.2206792","url":null,"abstract":"Nanoscale circuits operating at sub-threshold voltages are affected by growing impact of random telegraph signal (RTS) and thermal noise. Given the low operational voltages and subsequently lower noise margins, these noise phenomena are capable of changing the value of some of the nodes in the circuit, compromising the reliability of the computation. We propose a method for improving noise-tolerance by selectively applying feed-forward reinforcement to circuits based on use of existing invariant relationships. As reinforcement mechanism, we used a modification of the standard CMOS gates based on the Schmitt trigger circuit. SPICE simulations show our solution offers better noise immunity than both standard CMOS and fully reinforced circuits, with limited area and power overhead.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"558 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131738575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes a unified modeling framework for timing verification of IC designs that, through an elegant SMT-based formulation, seamlessly integrates functional timing analysis and parametric delay modeling. Such framework enables accurate timing verification by simultaneously ignoring false paths and accounting for process variability. By casting the timing verification problem as a general SMT instance it is possible to benefit from the continuous advances in performance and robustness of modern SMT engines. The proposed framework is validated for a representative set of benchmarks, using Microsoft's Z3 SMT solver.
{"title":"Unifying functional and parametric timing verification","authors":"L. G. Silva","doi":"10.1145/2206781.2206816","DOIUrl":"https://doi.org/10.1145/2206781.2206816","url":null,"abstract":"This paper proposes a unified modeling framework for timing verification of IC designs that, through an elegant SMT-based formulation, seamlessly integrates functional timing analysis and parametric delay modeling. Such framework enables accurate timing verification by simultaneously ignoring false paths and accounting for process variability. By casting the timing verification problem as a general SMT instance it is possible to benefit from the continuous advances in performance and robustness of modern SMT engines. The proposed framework is validated for a representative set of benchmarks, using Microsoft's Z3 SMT solver.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122214759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A scalable synthesis method for large input threshold logic circuits using Zero Suppressed Binary Decision Diagrams is introduced. Existing synthesis methods require that a large input function must be initially decomposed using small input functions and this impacts the synthesis cost. The presented approach in this paper does not consider such restrictions. It is experimentally shown that the proposed method can synthesize the primary outputs of existing benchmarks without consulting the net-list, and the synthesis cost is significantly reduced over the existing methods.
{"title":"A scalable threshold logic synthesis method using ZBDDs","authors":"Ashok Kumar Palaniswamy, S. Tragoudas","doi":"10.1145/2206781.2206856","DOIUrl":"https://doi.org/10.1145/2206781.2206856","url":null,"abstract":"A scalable synthesis method for large input threshold logic circuits using Zero Suppressed Binary Decision Diagrams is introduced. Existing synthesis methods require that a large input function must be initially decomposed using small input functions and this impacts the synthesis cost. The presented approach in this paper does not consider such restrictions. It is experimentally shown that the proposed method can synthesize the primary outputs of existing benchmarks without consulting the net-list, and the synthesis cost is significantly reduced over the existing methods.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124404426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a novel start-up circuit with a simple topology and low stand-by power during under voltage lockout (UVLO) mode is proposed for SMPS (switching mode power supplies) application. The proposed start-up circuit is designed using only a few MOSFETs, LDMOSs, and one JFET based on the analysis of the existing start-up circuits to address the power consumption and input voltage range issues of the conventional start-up. Simulated results using 0.35um BCDMOS process demonstrate that the leakage current of the proposed circuit is less than 1uA after UVLO signal turns on. Setting time is less than 1ms when the load current changes from 10mA to 20mA and vice versa
{"title":"A low stand-by power start-up circuit for SMPS PWM controller","authors":"In-Seok Jung, Yong-Bin Kim","doi":"10.1145/2206781.2206841","DOIUrl":"https://doi.org/10.1145/2206781.2206841","url":null,"abstract":"In this paper, a novel start-up circuit with a simple topology and low stand-by power during under voltage lockout (UVLO) mode is proposed for SMPS (switching mode power supplies) application. The proposed start-up circuit is designed using only a few MOSFETs, LDMOSs, and one JFET based on the analysis of the existing start-up circuits to address the power consumption and input voltage range issues of the conventional start-up. Simulated results using 0.35um BCDMOS process demonstrate that the leakage current of the proposed circuit is less than 1uA after UVLO signal turns on. Setting time is less than 1ms when the load current changes from 10mA to 20mA and vice versa","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128166811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present in this paper a circuit design approach to achieve compact logic circuits with ambipolar double-gate devices, using the in-field controllability of such devices. The approach is demonstrated for complementary static logic design style. We apply this approach in a case study focused on Double Gate Carbon Nanotube FET (DG-CNTFET) technology and show that, with respect to conventional CMOS-like static logic structures and for comparable power consumption, time delay and integration density can both be improved by a factor of 1.5x and 2x, respectively. Compared with a predictive model for 16nm CMOS technology, the gates built according to the design approach described in this work and based on DG-CNTFET offer a gain of 30% concerning Power-Delay-Product (PDP).
{"title":"Ambipolar double-gate FETs for the design of compact logic structures","authors":"K. Jabeur, I. O’Connor, N. Yakymets, S. L. Beux","doi":"10.1145/2206781.2206785","DOIUrl":"https://doi.org/10.1145/2206781.2206785","url":null,"abstract":"We present in this paper a circuit design approach to achieve compact logic circuits with ambipolar double-gate devices, using the in-field controllability of such devices. The approach is demonstrated for complementary static logic design style. We apply this approach in a case study focused on Double Gate Carbon Nanotube FET (DG-CNTFET) technology and show that, with respect to conventional CMOS-like static logic structures and for comparable power consumption, time delay and integration density can both be improved by a factor of 1.5x and 2x, respectively. Compared with a predictive model for 16nm CMOS technology, the gates built according to the design approach described in this work and based on DG-CNTFET offer a gain of 30% concerning Power-Delay-Product (PDP).","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128282257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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