Reliability issue, especially from transient errors due to scaling IC technology, low voltage supply, high frequency and heavy thermal effects, particles emission etc, has become a challenge for NoC design. Focus on this problem, an effective Reliability-Aware Arbitration Strategy simplified as RAPA, is proposed in this paper to decide which flits should be prioritized in the network transmission for higher application-level reliability. Different from pervious performance-oriented arbitration strategies, it includes the application-level reliability requirement to determine the reliability priority ranking. Flits patching mechanism is also used for avoiding starvation. The evaluation metric is redefined to emphasizing application-level reliability. Finally, we verify the reliability based prioritization policy on cycle accurate platform. And the simulation results show that the averaged successful delivery rate is upgraded from three nine of round robin (RR), old age based arbitration(OA) to five nine of our method RAPA. Especially, 67.15%, 41.83% reliability improvement in rest unreliable space on average are obtained over typical RR policy and OA based arbitration policy respectively with guaranteed performance.
{"title":"RAPA: reliability-aware priority arbitration strategy for network on chip","authors":"Jiajia Jiao, Yuzhuo Fu","doi":"10.1145/2206781.2206807","DOIUrl":"https://doi.org/10.1145/2206781.2206807","url":null,"abstract":"Reliability issue, especially from transient errors due to scaling IC technology, low voltage supply, high frequency and heavy thermal effects, particles emission etc, has become a challenge for NoC design. Focus on this problem, an effective Reliability-Aware Arbitration Strategy simplified as RAPA, is proposed in this paper to decide which flits should be prioritized in the network transmission for higher application-level reliability. Different from pervious performance-oriented arbitration strategies, it includes the application-level reliability requirement to determine the reliability priority ranking. Flits patching mechanism is also used for avoiding starvation. The evaluation metric is redefined to emphasizing application-level reliability. Finally, we verify the reliability based prioritization policy on cycle accurate platform. And the simulation results show that the averaged successful delivery rate is upgraded from three nine of round robin (RR), old age based arbitration(OA) to five nine of our method RAPA. Especially, 67.15%, 41.83% reliability improvement in rest unreliable space on average are obtained over typical RR policy and OA based arbitration policy respectively with guaranteed performance.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114095763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents techniques to determine the optimal reverse body bias (RBB) voltage to minimize leakage currents in modern nanoscale CMOS technology. The proposed self-adaptive RBB system finds the optimum reverse body bias voltage for minimal leakage power adaptively by comparing subthreshold leakage current (ISUBTH), gate tunneling leakage (IGATE), and band-to-band tunneling leakage currents (IBTBT) in standby mode. The proposed circuit has been designed and tested using 65nm bulk CMOS technology at 25ºC under a supply voltage of less than 1V. The optimal RBB was achieved at -0.372V with 1.2% error in the test case of the paper, and the simulation result shows that it is possible to reduce the total leakage current significantly as much as 86% of the total leakage using the proposed circuit techniques.
{"title":"Self adaptive body biasing scheme for leakage power reduction in nanoscale CMOS circuit","authors":"Jing Yang, Yong-Bin Kim","doi":"10.1145/2206781.2206811","DOIUrl":"https://doi.org/10.1145/2206781.2206811","url":null,"abstract":"This paper presents techniques to determine the optimal reverse body bias (RBB) voltage to minimize leakage currents in modern nanoscale CMOS technology. The proposed self-adaptive RBB system finds the optimum reverse body bias voltage for minimal leakage power adaptively by comparing subthreshold leakage current (ISUBTH), gate tunneling leakage (IGATE), and band-to-band tunneling leakage currents (IBTBT) in standby mode. The proposed circuit has been designed and tested using 65nm bulk CMOS technology at 25ºC under a supply voltage of less than 1V. The optimal RBB was achieved at -0.372V with 1.2% error in the test case of the paper, and the simulation result shows that it is possible to reduce the total leakage current significantly as much as 86% of the total leakage using the proposed circuit techniques.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121178995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Wireless Network-on-Chip (NoC) architectures have emerged as an enabling solution to design scalable NoC fabrics for massive many-core chips. However, such massive levels of integration of Intellectual Property (IP) cores make the chips vulnerable to malicious intrusions from untrustworthy processes or vendors. Hence, resilience to various types of hardware security threats is imperative in future many-core chips. In this paper we develop a design methodology to increase the resilience of a wireless NoC to Denial-of-Service (DoS) attacks. We demonstrate that the proposed architecture can sustain higher data transfer rates at lower energy dissipation with the spread of DoS attacks compared to conventional mesh based NoCs.
{"title":"A denial-of-service resilient wireless NoC architecture","authors":"A. Ganguly, M. Y. Ahmed, Anuroop Vidapalapati","doi":"10.1145/2206781.2206844","DOIUrl":"https://doi.org/10.1145/2206781.2206844","url":null,"abstract":"Wireless Network-on-Chip (NoC) architectures have emerged as an enabling solution to design scalable NoC fabrics for massive many-core chips. However, such massive levels of integration of Intellectual Property (IP) cores make the chips vulnerable to malicious intrusions from untrustworthy processes or vendors. Hence, resilience to various types of hardware security threats is imperative in future many-core chips. In this paper we develop a design methodology to increase the resilience of a wireless NoC to Denial-of-Service (DoS) attacks. We demonstrate that the proposed architecture can sustain higher data transfer rates at lower energy dissipation with the spread of DoS attacks compared to conventional mesh based NoCs.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131386426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Current commercial systems on chip (SoC) designs integrate an increasingly large number of pre-designed cores and their number is predicted to increase significantly in the near future. Specifically, molecular-scale computing will allow single or even multiple order-of-magnitude improvements in device densities. In the design of high-performance massive multi-core chips, power and temperature have become dominant constraints. Increased power consumption can raise chip temperature,which in turn can decrease chip reliability and performance and increase cooling costs.The new, ensuing possibilities in terms of single chip integration call for new paradigms, architectures, and infrastructures for high bandwidth and low-power interconnects. In this paper we demonstrate how small-world Network-on-Chip (NoC) architectures with long-range wireless links enable design of energy and thermally efficient sustainable multi-core platforms.
{"title":"Sustainable multi-core architecture with on-chip wireless links","authors":"Jacob Murray, John Klingner, P. Pande, B. Shirazi","doi":"10.1145/2206781.2206845","DOIUrl":"https://doi.org/10.1145/2206781.2206845","url":null,"abstract":"Current commercial systems on chip (SoC) designs integrate an increasingly large number of pre-designed cores and their number is predicted to increase significantly in the near future. Specifically, molecular-scale computing will allow single or even multiple order-of-magnitude improvements in device densities. In the design of high-performance massive multi-core chips, power and temperature have become dominant constraints. Increased power consumption can raise chip temperature,which in turn can decrease chip reliability and performance and increase cooling costs.The new, ensuing possibilities in terms of single chip integration call for new paradigms, architectures, and infrastructures for high bandwidth and low-power interconnects. In this paper we demonstrate how small-world Network-on-Chip (NoC) architectures with long-range wireless links enable design of energy and thermally efficient sustainable multi-core platforms.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131640184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we propose a multiplexed 3D-switch box architecture that decreases the number of TSVs required for routing with a slight overhead in total wirelength. Our experimental results show that the presented architecture reduces the number of routing TSVs by about 48% in cost of less than 2% wirelength overhead.
{"title":"Multiplexed switch box architecture in three-dimensional FPGAs to reduce silicon area and improve TSV usage","authors":"Marzieh Morshedzadeh, A. Jahanian","doi":"10.1145/2206781.2206855","DOIUrl":"https://doi.org/10.1145/2206781.2206855","url":null,"abstract":"In this paper, we propose a multiplexed 3D-switch box architecture that decreases the number of TSVs required for routing with a slight overhead in total wirelength. Our experimental results show that the presented architecture reduces the number of routing TSVs by about 48% in cost of less than 2% wirelength overhead.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114173512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Detecting the symmetries of a Boolean function can lead to simpler implementations both at the hardware and software level. Large clusters of mutually symmetric variables are more advantageous than small clusters. One way to extend the symmetry of a function is to detect abstract two-cofactor relations in addition to ordinary symmetric relations. Unfortunately, ordinary symmetries are simply transitive but more complex types of relations are not. This paper shows how to convert the more complex relations into ordinary symmetries, allowing them to be used to form large clusters of symmetric variables, larger than would be possible using ordinary symmetries.
{"title":"Extending symmetric variable-pair transitivities using state-space transformations","authors":"P. Maurer","doi":"10.1145/2206781.2206859","DOIUrl":"https://doi.org/10.1145/2206781.2206859","url":null,"abstract":"Detecting the symmetries of a Boolean function can lead to simpler implementations both at the hardware and software level. Large clusters of mutually symmetric variables are more advantageous than small clusters. One way to extend the symmetry of a function is to detect abstract two-cofactor relations in addition to ordinary symmetric relations. Unfortunately, ordinary symmetries are simply transitive but more complex types of relations are not. This paper shows how to convert the more complex relations into ordinary symmetries, allowing them to be used to form large clusters of symmetric variables, larger than would be possible using ordinary symmetries.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114343580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Nicholas Tuzzio, K. Xiao, Xuehui Zhang, M. Tehranipoor
The counterfeiting of integrated circuits (ICs) has become a major issue for the electronics industry. Counterfeit ICs that find their way into the supply chains of critical applications can have a major impact on the security and reliability of those systems. This paper presents a new method for uniquely identifying ICs through path delay analysis. There is no overhead in terms of area, timing, or power for this method, since it extracts the intrinsic path delay variation information of the IC. Simulation results from 90nm technology and experimental results from 90nm FPGAs demonstrate the effectiveness of our technique.
{"title":"A zero-overhead IC identification technique using clock sweeping and path delay analysis","authors":"Nicholas Tuzzio, K. Xiao, Xuehui Zhang, M. Tehranipoor","doi":"10.1145/2206781.2206806","DOIUrl":"https://doi.org/10.1145/2206781.2206806","url":null,"abstract":"The counterfeiting of integrated circuits (ICs) has become a major issue for the electronics industry. Counterfeit ICs that find their way into the supply chains of critical applications can have a major impact on the security and reliability of those systems. This paper presents a new method for uniquely identifying ICs through path delay analysis. There is no overhead in terms of area, timing, or power for this method, since it extracts the intrinsic path delay variation information of the IC. Simulation results from 90nm technology and experimental results from 90nm FPGAs demonstrate the effectiveness of our technique.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125063737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
3D-ICs hold significant promise for future generation multi processor systems-on-chip due to their potential for increased performance, decreased power, heterogeneous integration, and reduced cost over planar ICs. However, the vertical integration of these structures exacerbates the heat dissipation and run-time thermal management issues. There have been a number of design- and run-time thermal management policies proposed, but few focus on examining overall system performance. Additionally, the heterogeneity of 3D-ICs allows for the integration of novel technologies, such as resistive random access memories (RRAMs), which offer higher density and lower power than traditional CMOS memory technologies. Our work presents a flexible design-time simulation framework to evaluate system performance and thermal profiles of 3D MPSoCs. We utilize this framework to study the effect of three dynamic thermal management policies (air-cooled load balancing, liquid-cooled load balancing, and air-cooled DVFS) on system performance and die temperature for multi-tiered 3D MPSoCs utilizing SRAM and RRAM-based L2 caches. We find that RRAM-based caches lower overall average maximum temperatures by 120 K and 24 K for air and liquid cooling systems, respectively (when compared to SRAM-based caches), at a worst-case performance delay of 47% and best-case delay of 13% for the parallel shared-memory benchmarks studied.
{"title":"Design-time performance evaluation of thermal management policies for SRAM and RRAM based 3D MPSoCs","authors":"D. Brenner, Cory E. Merkel, D. Kudithipudi","doi":"10.1145/2206781.2206824","DOIUrl":"https://doi.org/10.1145/2206781.2206824","url":null,"abstract":"3D-ICs hold significant promise for future generation multi processor systems-on-chip due to their potential for increased performance, decreased power, heterogeneous integration, and reduced cost over planar ICs. However, the vertical integration of these structures exacerbates the heat dissipation and run-time thermal management issues. There have been a number of design- and run-time thermal management policies proposed, but few focus on examining overall system performance. Additionally, the heterogeneity of 3D-ICs allows for the integration of novel technologies, such as resistive random access memories (RRAMs), which offer higher density and lower power than traditional CMOS memory technologies. Our work presents a flexible design-time simulation framework to evaluate system performance and thermal profiles of 3D MPSoCs. We utilize this framework to study the effect of three dynamic thermal management policies (air-cooled load balancing, liquid-cooled load balancing, and air-cooled DVFS) on system performance and die temperature for multi-tiered 3D MPSoCs utilizing SRAM and RRAM-based L2 caches. We find that RRAM-based caches lower overall average maximum temperatures by 120 K and 24 K for air and liquid cooling systems, respectively (when compared to SRAM-based caches), at a worst-case performance delay of 47% and best-case delay of 13% for the parallel shared-memory benchmarks studied.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121070919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Negative Bias Temperature Instability (NBTI) causes the threshold voltage of PMOS devices to degrade with time, resulting in a reduced lifetime of a CMOS IC. In this paper, we present an approach to mitigate the degradation due to NBTI for off-chip output drivers. Our approach is based on forcibly inducing relaxation in the individual fingers of the output driver (which is typically implemented in a multi-fingered fashion). The individual fingers are relaxed in a round-robin manner, such that at any given time, k out of n fingers of the driver are being relaxed. Our results show that the proposed approach significantly extends the lifetime of the output driver.
{"title":"Alleviating NBTI-induced failure in off-chip output drivers","authors":"Bhavitavya Bhadviya, Ayan Mandal, S. Khatri","doi":"10.1145/2206781.2206853","DOIUrl":"https://doi.org/10.1145/2206781.2206853","url":null,"abstract":"Negative Bias Temperature Instability (NBTI) causes the threshold voltage of PMOS devices to degrade with time, resulting in a reduced lifetime of a CMOS IC. In this paper, we present an approach to mitigate the degradation due to NBTI for off-chip output drivers. Our approach is based on forcibly inducing relaxation in the individual fingers of the output driver (which is typically implemented in a multi-fingered fashion). The individual fingers are relaxed in a round-robin manner, such that at any given time, k out of n fingers of the driver are being relaxed. Our results show that the proposed approach significantly extends the lifetime of the output driver.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126090082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A scalable synthesis method for large input threshold logic circuits using Zero Suppressed Binary Decision Diagrams is introduced. Existing synthesis methods require that a large input function must be initially decomposed using small input functions and this impacts the synthesis cost. The presented approach in this paper does not consider such restrictions. It is experimentally shown that the proposed method can synthesize the primary outputs of existing benchmarks without consulting the net-list, and the synthesis cost is significantly reduced over the existing methods.
{"title":"A scalable threshold logic synthesis method using ZBDDs","authors":"Ashok Kumar Palaniswamy, S. Tragoudas","doi":"10.1145/2206781.2206856","DOIUrl":"https://doi.org/10.1145/2206781.2206856","url":null,"abstract":"A scalable synthesis method for large input threshold logic circuits using Zero Suppressed Binary Decision Diagrams is introduced. Existing synthesis methods require that a large input function must be initially decomposed using small input functions and this impacts the synthesis cost. The presented approach in this paper does not consider such restrictions. It is experimentally shown that the proposed method can synthesize the primary outputs of existing benchmarks without consulting the net-list, and the synthesis cost is significantly reduced over the existing methods.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124404426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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