D. Ghai, S. Mohanty, G. Thakral, Oghenekarho Okobiah
With the technology trend moving towards smaller geometries and improved circuit performances, multigate transistors are expected to replace the traditional bulk devices. The double-gate FinFET lends itself to a rich design space using various configurations of the two gates. Accurate current mirroring is a critical analog design requirement in many applications. Current mirror is an essential component in analog design for biasing and constant current generation. This paper presents the exploration of different configurations of a double gate fully depleted SOI based FinFETs for efficient design of current mirror designs. In particular, comparison among the important Figures-of-Merit (FoMs) current mirror designs including mismatch, variability, output resistance ($r_0$), compliance voltage ($V_{CV}$) is presented for: (1) shorted-gate (SG), (2) independent-gate (IG), and (3) low-power (LP) configurations. Based on the results obtained, guidelines are presented for the designer for current mirror design using FinFET.
{"title":"Variability-aware design of double gate FinFET-based current mirrors","authors":"D. Ghai, S. Mohanty, G. Thakral, Oghenekarho Okobiah","doi":"10.1145/2591513.2591583","DOIUrl":"https://doi.org/10.1145/2591513.2591583","url":null,"abstract":"With the technology trend moving towards smaller geometries and improved circuit performances, multigate transistors are expected to replace the traditional bulk devices. The double-gate FinFET lends itself to a rich design space using various configurations of the two gates. Accurate current mirroring is a critical analog design requirement in many applications. Current mirror is an essential component in analog design for biasing and constant current generation. This paper presents the exploration of different configurations of a double gate fully depleted SOI based FinFETs for efficient design of current mirror designs. In particular, comparison among the important Figures-of-Merit (FoMs) current mirror designs including mismatch, variability, output resistance ($r_0$), compliance voltage ($V_{CV}$) is presented for: (1) shorted-gate (SG), (2) independent-gate (IG), and (3) low-power (LP) configurations. Based on the results obtained, guidelines are presented for the designer for current mirror design using FinFET.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123768386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Asynchronous networks on chip (NoCs) are promising candidates for supporting the enormous communication needed by future many-core systems due to their low-energy and high-speed. Similar to synchronous NoCs, asynchronous NoCs are vulnerable to faults but their fault-tolerance is not studied adequately, especially the quasi-delay insensitive (QDI) NoCs. One of the key issues neglected by most designers is that permanent faults in QDI NoCs cause deadlocks, which cripples the traditional fault-tolerant techniques using redundant codes. A novel detection method has been proposed to locate the faulty link in a QDI NoC according to a common pattern shared by all fault-related deadlocks. It is shown that this method introduces low hardware overhead and reports permanently faulty links with a short delay and guaranteed accuracy.
{"title":"On-line detection of the deadlocks caused by permanently faulty links in quasi-delay insensitive networks on chip","authors":"Wei Song, Guangda Zhang, J. Garside","doi":"10.1145/2591513.2591518","DOIUrl":"https://doi.org/10.1145/2591513.2591518","url":null,"abstract":"Asynchronous networks on chip (NoCs) are promising candidates for supporting the enormous communication needed by future many-core systems due to their low-energy and high-speed. Similar to synchronous NoCs, asynchronous NoCs are vulnerable to faults but their fault-tolerance is not studied adequately, especially the quasi-delay insensitive (QDI) NoCs. One of the key issues neglected by most designers is that permanent faults in QDI NoCs cause deadlocks, which cripples the traditional fault-tolerant techniques using redundant codes. A novel detection method has been proposed to locate the faulty link in a QDI NoC according to a common pattern shared by all fault-related deadlocks. It is shown that this method introduces low hardware overhead and reports permanently faulty links with a short delay and guaranteed accuracy.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130899829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The generation of fast models for device level circuit descriptions is a very active area of research. Model order reduction is an attractive technique for dynamical models size reduction. In this paper, we propose an approach based on clustering, curve-fitting, linearization and Krylov space projection to build reduced models for nonlinear analog circuits. We demonstrate our model order reduction method for three nonlinear circuits: a voltage controlled oscillator, an operational amplifier and a digital frequency divider. Our experimental results show that the reduced models lead to an improvement in simulation speed while guaranteeing the representation of the behavior of the original circuit design.
{"title":"Generation of reduced analog circuit models using transient simulation traces","authors":"P. Winkler, Henda Aridhi, M. Zaki, S. Tahar","doi":"10.1145/2591513.2591530","DOIUrl":"https://doi.org/10.1145/2591513.2591530","url":null,"abstract":"The generation of fast models for device level circuit descriptions is a very active area of research. Model order reduction is an attractive technique for dynamical models size reduction. In this paper, we propose an approach based on clustering, curve-fitting, linearization and Krylov space projection to build reduced models for nonlinear analog circuits. We demonstrate our model order reduction method for three nonlinear circuits: a voltage controlled oscillator, an operational amplifier and a digital frequency divider. Our experimental results show that the reduced models lead to an improvement in simulation speed while guaranteeing the representation of the behavior of the original circuit design.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124020339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Both asynchronous and reconfigurable techniques are likely to become increasingly important in the future due to greater device unreliability and variability at nano-scale dimensions. One promising asynchronous technique, Null Convention Logic (NCL) is a symbolically complete quasi-delay insensitive logic system that is inherently self-determined, locally autonomous and self-synchronizing. As current FPGA devices are set up for clocked synchronous logic they are not well suited to reconfigurable asynchronous systems. A reconfigurable block supporting NCL that is intended to form one component of a FPGA organization is proposed and analyzed. Both single-rail and dual-rail LUTs are described. The block design and layout is described and analyzed using an advanced 45nm bulk CMOS fabrication process.
{"title":"A dual-rail LUT for reconfigurable logic using null convention logic","authors":"Jing Yu, P. Beckett","doi":"10.1145/2591513.2591589","DOIUrl":"https://doi.org/10.1145/2591513.2591589","url":null,"abstract":"Both asynchronous and reconfigurable techniques are likely to become increasingly important in the future due to greater device unreliability and variability at nano-scale dimensions. One promising asynchronous technique, Null Convention Logic (NCL) is a symbolically complete quasi-delay insensitive logic system that is inherently self-determined, locally autonomous and self-synchronizing. As current FPGA devices are set up for clocked synchronous logic they are not well suited to reconfigurable asynchronous systems. A reconfigurable block supporting NCL that is intended to form one component of a FPGA organization is proposed and analyzed. Both single-rail and dual-rail LUTs are described. The block design and layout is described and analyzed using an advanced 45nm bulk CMOS fabrication process.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"171 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116015135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Ziesemer, R. Reis, Matheus T. Moreira, Michel Evandro Arendt, Ney Laert Vilar Calazans
As the foundries update their advanced processes with new complex design rules and cell libraries grow in size and complexity, the cost of library development become increasingly higher. In this work we present the methodology used in ASTRAN to allow automatic layout generation of cell libraries for technologies down to 45nm from its transistor level netlist description in SPICE format. It supports non-complementary logic cells, allowing generation of any kind of transistor networks, and continuous transistor sizing. We describe our new generation flow which is currently being used to generate a library with more than 500 asynchronous cells in a 65nm process.
{"title":"A design flow for physical synthesis of digital cells with ASTRAN","authors":"A. Ziesemer, R. Reis, Matheus T. Moreira, Michel Evandro Arendt, Ney Laert Vilar Calazans","doi":"10.1145/2591513.2591577","DOIUrl":"https://doi.org/10.1145/2591513.2591577","url":null,"abstract":"As the foundries update their advanced processes with new complex design rules and cell libraries grow in size and complexity, the cost of library development become increasingly higher. In this work we present the methodology used in ASTRAN to allow automatic layout generation of cell libraries for technologies down to 45nm from its transistor level netlist description in SPICE format. It supports non-complementary logic cells, allowing generation of any kind of transistor networks, and continuous transistor sizing. We describe our new generation flow which is currently being used to generate a library with more than 500 asynchronous cells in a 65nm process.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126734076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sajib Kumar Mitra, Lafifa Jamal, M. Kaneko, H. M. H. Babu
Reversible computing dissipates zero energy in terms of information loss at input and also it can detect error of circuit by keeping unique input-output mapping. In this paper, we have proposed a cost effective design of Reversible Programmable Logic Arrays (RPLAs) which is able to realize multi-output ESOP (Exclusive-OR Sum-Of-Product) functions by using a cost effective 3x3 reversible gate, called MG (MUX Gate). Also a new algorithm has been proposed for the calculation of critical path delay of reversible PLAs. The minimization processes consist of algorithms for ordering of output functions followed by the ordering of products. Five lower bounds on the numbers of gates, garbages and quantum costs of reversible PLAs are also proposed. Finally, we have compared the efficiency of proposed design with the existing one by providing benchmark functions analysis. The experimental results show that the proposed design outperforms the existing one in terms of numbers of gates, garbages, quantum costs and delay.
{"title":"An efficient approach for designing and minimizing reversible programmable logic arrays","authors":"Sajib Kumar Mitra, Lafifa Jamal, M. Kaneko, H. M. H. Babu","doi":"10.1145/2206781.2206834","DOIUrl":"https://doi.org/10.1145/2206781.2206834","url":null,"abstract":"Reversible computing dissipates zero energy in terms of information loss at input and also it can detect error of circuit by keeping unique input-output mapping. In this paper, we have proposed a cost effective design of Reversible Programmable Logic Arrays (RPLAs) which is able to realize multi-output ESOP (Exclusive-OR Sum-Of-Product) functions by using a cost effective 3x3 reversible gate, called MG (MUX Gate). Also a new algorithm has been proposed for the calculation of critical path delay of reversible PLAs. The minimization processes consist of algorithms for ordering of output functions followed by the ordering of products. Five lower bounds on the numbers of gates, garbages and quantum costs of reversible PLAs are also proposed. Finally, we have compared the efficiency of proposed design with the existing one by providing benchmark functions analysis. The experimental results show that the proposed design outperforms the existing one in terms of numbers of gates, garbages, quantum costs and delay.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124887923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Electronic computing relies on systematically controlling the flow of electrons to perform logical functions. Various technologies and logic families are used in modern computing, each with its own tradeoffs. In particular, diode logic allows for the execution of logic with many fewer devices than complementary metal-oxide-semiconductor (CMOS) architectures, which implies the potential to be faster, cheaper, and dissipate less power. It has heretofore been impossible to fully utilize diode logic, however, as standard diodes lack the capability of performing signal inversion. Here we create a binary logic family based on high and low current states in which the InMnAs magnetoresistive semiconductor heterojunction diodes implement the first complete logic family based solely on diodes. The diodes are used as switches by manipulating the magnetoresistance with control currents that generate magnetic fields through the junction. With this device structure, we present basis logic elements and complex circuits consisting of as few as 10% of the devices required in their conventional CMOS counterparts. These circuits are evaluated based on InMnAs experimental data, and design techniques are discussed. As Si scaling reaches its inherent limits, this spin-diode logic family is an intriguing potential replacement for CMOS technology due to its material characteristics and compact circuits.
{"title":"InMnAs magnetoresistive spin-diode logic","authors":"J. Friedman, N. Rangaraju, Y. Ismail, B. Wessels","doi":"10.1145/2206781.2206833","DOIUrl":"https://doi.org/10.1145/2206781.2206833","url":null,"abstract":"Electronic computing relies on systematically controlling the flow of electrons to perform logical functions. Various technologies and logic families are used in modern computing, each with its own tradeoffs. In particular, diode logic allows for the execution of logic with many fewer devices than complementary metal-oxide-semiconductor (CMOS) architectures, which implies the potential to be faster, cheaper, and dissipate less power. It has heretofore been impossible to fully utilize diode logic, however, as standard diodes lack the capability of performing signal inversion. Here we create a binary logic family based on high and low current states in which the InMnAs magnetoresistive semiconductor heterojunction diodes implement the first complete logic family based solely on diodes. The diodes are used as switches by manipulating the magnetoresistance with control currents that generate magnetic fields through the junction. With this device structure, we present basis logic elements and complex circuits consisting of as few as 10% of the devices required in their conventional CMOS counterparts. These circuits are evaluated based on InMnAs experimental data, and design techniques are discussed. As Si scaling reaches its inherent limits, this spin-diode logic family is an intriguing potential replacement for CMOS technology due to its material characteristics and compact circuits.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125439744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sujay Deb, Kevin Chang, Miralem Cosic, A. Ganguly, P. Pande, D. Heo, B. Belzer
Traditional many-core designs based on the Network-on-Chip (NoC) paradigm suffer from high latency and power dissipation as the system size scales up due to their inherent multi-hop communication. NoC performance can be significantly enhanced by introducing long-range, low power, and high-bandwidth single-hop wireless links between far apart cores. This paper presents a design methodology and performance evaluation for a hierarchical small-world NoC with CMOS compatible on-chip millimeter (mm)-wave wireless long-range communication links. The proposed wireless NoC offers significantly higher bandwidth and lower energy dissipation compared to its conventional non-hierarchical wired counterpart in presence of both uniform and non-uniform traffic patterns. The performance improvement is achieved through efficient data routing and optimum placement of wireless hubs. Multiple wireless shortcuts operating simultaneously provide an energy efficient solution for design of many-core communication infrastructures.
{"title":"CMOS compatible many-core noc architectures with multi-channel millimeter-wave wireless links","authors":"Sujay Deb, Kevin Chang, Miralem Cosic, A. Ganguly, P. Pande, D. Heo, B. Belzer","doi":"10.1145/2206781.2206822","DOIUrl":"https://doi.org/10.1145/2206781.2206822","url":null,"abstract":"Traditional many-core designs based on the Network-on-Chip (NoC) paradigm suffer from high latency and power dissipation as the system size scales up due to their inherent multi-hop communication. NoC performance can be significantly enhanced by introducing long-range, low power, and high-bandwidth single-hop wireless links between far apart cores. This paper presents a design methodology and performance evaluation for a hierarchical small-world NoC with CMOS compatible on-chip millimeter (mm)-wave wireless long-range communication links. The proposed wireless NoC offers significantly higher bandwidth and lower energy dissipation compared to its conventional non-hierarchical wired counterpart in presence of both uniform and non-uniform traffic patterns. The performance improvement is achieved through efficient data routing and optimum placement of wireless hubs. Multiple wireless shortcuts operating simultaneously provide an energy efficient solution for design of many-core communication infrastructures.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130566762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a fully integrated on-chip switched-capacitor (SC) DC-DC converter that supports two regulated power supply voltages of 2.2V and 3.2V from 5V input supply and delivers the maximum load currents up to 8mA at both of the outputs. The entire converter system uses two 2-to-1 converter blocks. The upper output voltage (3.2V) is generated from the 2-to-1_up converter by means of averaging the 5V input and the generated lower output voltage (2.2V), which is generated from 2-to-1_dw converter. Since 2-to-1_up converter is less sensitive to the bottom-plate parasitic capacitance loss, they are implemented with MOS capacitors, which show higher capacitance density (2.7fF/μm2, α=6.5%) than MIM capacitors (1fF/μm2, α=2.5%) while they have bigger bottom-plate parasitic capacitance ratio (α). The proposed implementation saves the area and quiescent currents for the control blocks since each block shares required analog and digital control blocks. The proposed converter is designed using high-voltage 0.35μm BCDMOS technology. Both output voltages are regulated by means of pulse frequency modulation (PFM) technique using 18-bit shift registers and digitally controlled oscillators (DCOs). Over the wide output power ranges from 5.4mW to 43.2mW, the converter achieves the average efficiency of 70.0% and the peak efficiency of 71.4%. 10-phase interleaving technique enables the output voltage ripples of the both outputs less than 1% (<40mV) of the output voltages when 400pF of output buffer capacitors are used for both outputs.
{"title":"A fully integrated switched-capacitor DC-DC converter with dual output for low power application","authors":"HeungJun Jeon, Yong-Bin Kim","doi":"10.1145/2206781.2206803","DOIUrl":"https://doi.org/10.1145/2206781.2206803","url":null,"abstract":"This paper presents a fully integrated on-chip switched-capacitor (SC) DC-DC converter that supports two regulated power supply voltages of 2.2V and 3.2V from 5V input supply and delivers the maximum load currents up to 8mA at both of the outputs. The entire converter system uses two 2-to-1 converter blocks. The upper output voltage (3.2V) is generated from the 2-to-1_up converter by means of averaging the 5V input and the generated lower output voltage (2.2V), which is generated from 2-to-1_dw converter. Since 2-to-1_up converter is less sensitive to the bottom-plate parasitic capacitance loss, they are implemented with MOS capacitors, which show higher capacitance density (2.7fF/μm2, α=6.5%) than MIM capacitors (1fF/μm2, α=2.5%) while they have bigger bottom-plate parasitic capacitance ratio (α). The proposed implementation saves the area and quiescent currents for the control blocks since each block shares required analog and digital control blocks. The proposed converter is designed using high-voltage 0.35μm BCDMOS technology. Both output voltages are regulated by means of pulse frequency modulation (PFM) technique using 18-bit shift registers and digitally controlled oscillators (DCOs). Over the wide output power ranges from 5.4mW to 43.2mW, the converter achieves the average efficiency of 70.0% and the peak efficiency of 71.4%. 10-phase interleaving technique enables the output voltage ripples of the both outputs less than 1% (<40mV) of the output voltages when 400pF of output buffer capacitors are used for both outputs.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130647856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Negative-Bias Temperature Instability seriously affects nanoscale circuits reliability and performance. Continuous stress and increasing operating temperatures lead to device degradation and long-term system unavailability. The opportunity to optimize the duty-cycle of the stress/recovery phases to reduce Vth degradation leads to innovative research of reliability-oriented resources allocation at architectural level. This work explores the impact of different allocation strategies on the processor degradation, through a novel estimation methodology. Experimental results show that the proposed NBTI-aware allocation strategy can guarantee from 10% and up to 30% lower degradation compared to classical strategies, under different operating scenarios and under process variability.
{"title":"NBTI mitigation in microprocessor designs","authors":"S. Corbetta, W. Fornaciari","doi":"10.1145/2206781.2206791","DOIUrl":"https://doi.org/10.1145/2206781.2206791","url":null,"abstract":"Negative-Bias Temperature Instability seriously affects nanoscale circuits reliability and performance. Continuous stress and increasing operating temperatures lead to device degradation and long-term system unavailability. The opportunity to optimize the duty-cycle of the stress/recovery phases to reduce Vth degradation leads to innovative research of reliability-oriented resources allocation at architectural level. This work explores the impact of different allocation strategies on the processor degradation, through a novel estimation methodology. Experimental results show that the proposed NBTI-aware allocation strategy can guarantee from 10% and up to 30% lower degradation compared to classical strategies, under different operating scenarios and under process variability.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114529090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：