Pub Date : 2023-12-30DOI: 10.54105/ijvlsid.a1212.092222
Abinet Arba
We are moving towards the era of scaling down of transistor size, short channel effects (SCEs) and errors are becoming major concern. NSFET is emerging transistors, which gives better SCEs performance compared to conventional MOSFET and FinFET transistors. In this paper, (7, 4) Hamming code was implemented at input side of ALU to prevent error which occur when the transistors size decreases (scale down). The efficiency of any system depends on the performance of internal components. If internal components satisfy the criteria of area, power and delay, the system will always be a efficient system, therefore in this paper the smart ALU was designed by making the internal components to satisfy criteria of area, power and delay. All internal components of ALU including (7, 4) Hamming code was designed by using MICROWIND 3.9 and DSCH 3.9 software and each component design was started from schematic diagram and moved up to automatic physical design by using Verilog code and including post layout simulation with spice netlist which contains parasitic parameters and finally area, power consumption, propagation delay including global delay analysis with RC information and operating frequency of each internal components of ALU was measured and compared with existing one and also Number of error detected and corrected was measured. Two kind of technology was used depending on their advantages (3nm technology for arithmetic design and 7nm technology for remain component design).
{"title":"Design of Smart Alu with Error Detection and Correction at Input Side","authors":"Abinet Arba","doi":"10.54105/ijvlsid.a1212.092222","DOIUrl":"https://doi.org/10.54105/ijvlsid.a1212.092222","url":null,"abstract":"We are moving towards the era of scaling down of transistor size, short channel effects (SCEs) and errors are becoming major concern. NSFET is emerging transistors, which gives better SCEs performance compared to conventional MOSFET and FinFET transistors. In this paper, (7, 4) Hamming code was implemented at input side of ALU to prevent error which occur when the transistors size decreases (scale down). The efficiency of any system depends on the performance of internal components. If internal components satisfy the criteria of area, power and delay, the system will always be a efficient system, therefore in this paper the smart ALU was designed by making the internal components to satisfy criteria of area, power and delay. All internal components of ALU including (7, 4) Hamming code was designed by using MICROWIND 3.9 and DSCH 3.9 software and each component design was started from schematic diagram and moved up to automatic physical design by using Verilog code and including post layout simulation with spice netlist which contains parasitic parameters and finally area, power consumption, propagation delay including global delay analysis with RC information and operating frequency of each internal components of ALU was measured and compared with existing one and also Number of error detected and corrected was measured. Two kind of technology was used depending on their advantages (3nm technology for arithmetic design and 7nm technology for remain component design).","PeriodicalId":275481,"journal":{"name":"Indian Journal of VLSI Design","volume":" 9","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139140839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-30DOI: 10.54105/ijvlsid.a1216.033123
Dr. G. Sasikala, G. S. Krishna
Now a days all embedded processors are manufactured in such a way that it may consume low power to provide longer life to the system using various low power techniques like clock gating, data gating, variable frequency mechanism, variable voltage mechanism and variable threshold techniques. In this paper these techniques are implemented using VHDL language in Vivado and results are compared to identify the better one among all possible ones. There are various characteristics compared here are power consumption, number of look up tables and number of flip flops consumed.
{"title":"Low Power Embedded SoC Design","authors":"Dr. G. Sasikala, G. S. Krishna","doi":"10.54105/ijvlsid.a1216.033123","DOIUrl":"https://doi.org/10.54105/ijvlsid.a1216.033123","url":null,"abstract":"Now a days all embedded processors are manufactured in such a way that it may consume low power to provide longer life to the system using various low power techniques like clock gating, data gating, variable frequency mechanism, variable voltage mechanism and variable threshold techniques. In this paper these techniques are implemented using VHDL language in Vivado and results are compared to identify the better one among all possible ones. There are various characteristics compared here are power consumption, number of look up tables and number of flip flops consumed.","PeriodicalId":275481,"journal":{"name":"Indian Journal of VLSI Design","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122547355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-30DOI: 10.54105/ijvlsid.a1215.033123
Priya Singh, Dr. Vandana Niranjan, Prof. Ashwni Kumar
In this paper a comparative study of different CMOS transimpedance amplifier has been presented. Standard device parameters of transimpedance amplifier such as gain, input refereed noise, power dissipation and group delay are studied and compared. Here the transimpedance amplifier is divided on the basis of its topology and device technology used and performance is summarized to get the overview. Most of the analysis taken are performed on 0.18 μm technology and some are implemented using 45nm, 0.13μm, 65nm, and 90nm.
{"title":"A Comparative Study of CMOS Transimpedance Amplifier (TIA)","authors":"Priya Singh, Dr. Vandana Niranjan, Prof. Ashwni Kumar","doi":"10.54105/ijvlsid.a1215.033123","DOIUrl":"https://doi.org/10.54105/ijvlsid.a1215.033123","url":null,"abstract":"In this paper a comparative study of different CMOS transimpedance amplifier has been presented. Standard device parameters of transimpedance amplifier such as gain, input refereed noise, power dissipation and group delay are studied and compared. Here the transimpedance amplifier is divided on the basis of its topology and device technology used and performance is summarized to get the overview. Most of the analysis taken are performed on 0.18 μm technology and some are implemented using 45nm, 0.13μm, 65nm, and 90nm.","PeriodicalId":275481,"journal":{"name":"Indian Journal of VLSI Design","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116534428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-30DOI: 10.54105/ijvlsid.a1217.033123
P. S. Yadav, Harsha Jain
Due to the substantial impact embedded Static Random Access Memory (SRAM)s have on the overall system and their relatively limited design, it is essential to manage embedded SRAM trade-offs strategically. SRAMs have power, performance and density trade-offs in general. In all applications, all three dimensions are necessary to some extent; accordingly, embedded SRAM design must incorporate the most crucial system-specific requirements when developing embedded SRAM. This paper discusses many SRAM factors, including Static Noise Margin (SNM), Read Access Time (RAT),Write Access Time (WAT), Read Stability and Write Ability, Power, Data Retention Voltage (DRV), and Process Control. All these factors are crucial when designing SRAM for embedded memory applications. There has also been a discussion of the parameter comparisons and the literature review of the current papers.
{"title":"Review of 6T SRAM for Embedded Memory Applications","authors":"P. S. Yadav, Harsha Jain","doi":"10.54105/ijvlsid.a1217.033123","DOIUrl":"https://doi.org/10.54105/ijvlsid.a1217.033123","url":null,"abstract":"Due to the substantial impact embedded Static Random Access Memory (SRAM)s have on the overall system and their relatively limited design, it is essential to manage embedded SRAM trade-offs strategically. SRAMs have power, performance and density trade-offs in general. In all applications, all three dimensions are necessary to some extent; accordingly, embedded SRAM design must incorporate the most crucial system-specific requirements when developing embedded SRAM. This paper discusses many SRAM factors, including Static Noise Margin (SNM), Read Access Time (RAT),Write Access Time (WAT), Read Stability and Write Ability, Power, Data Retention Voltage (DRV), and Process Control. All these factors are crucial when designing SRAM for embedded memory applications. There has also been a discussion of the parameter comparisons and the literature review of the current papers.","PeriodicalId":275481,"journal":{"name":"Indian Journal of VLSI Design","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124606804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-30DOI: 10.54105/ijvlsid.a1213.033123
Hadi Kolivand, M. Hayati
In this paper, an approach for the reduction of unwanted edges in contour detection based on local filtering is presented. Our approach can be used as a preprocessing step before contour detection. Also our approach is useful for object recognition based on feature extraction tasks, because many contour detection methods can’t delete all unwanted edges carefully. Our method consists of a computational algorithm that has 7 steps. Including smoothing, edge detection, smoothing, decreasing of pixels, thresholding, local filtering, and mask creation respectively. We use smoothing for adhering neighbor edge pixels and weakening alone edge pixels. So we can amplify the correct edge pixels and attenuate unwanted edge pixels by smoothing the edge image. In local filtering, we use a proposed casual template that determines noisy regions and correct regions and therefore can create a mask matrix that its elements related to mentioned regions. Finally we can use the "mask matrix" for improving contours by using a “And” operator and we ensure final contour that has a few context effect.
{"title":"An Approach for the Reduction of Unwanted Edges in Contour Detection Based on Local Filtering","authors":"Hadi Kolivand, M. Hayati","doi":"10.54105/ijvlsid.a1213.033123","DOIUrl":"https://doi.org/10.54105/ijvlsid.a1213.033123","url":null,"abstract":"In this paper, an approach for the reduction of unwanted edges in contour detection based on local filtering is presented. Our approach can be used as a preprocessing step before contour detection. Also our approach is useful for object recognition based on feature extraction tasks, because many contour detection methods can’t delete all unwanted edges carefully. Our method consists of a computational algorithm that has 7 steps. Including smoothing, edge detection, smoothing, decreasing of pixels, thresholding, local filtering, and mask creation respectively. We use smoothing for adhering neighbor edge pixels and weakening alone edge pixels. So we can amplify the correct edge pixels and attenuate unwanted edge pixels by smoothing the edge image. In local filtering, we use a proposed casual template that determines noisy regions and correct regions and therefore can create a mask matrix that its elements related to mentioned regions. Finally we can use the \"mask matrix\" for improving contours by using a “And” operator and we ensure final contour that has a few context effect.","PeriodicalId":275481,"journal":{"name":"Indian Journal of VLSI Design","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134534812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-09-30DOI: 10.54105/ijvlsid.d1209.091422
Ishita Khindria, Kashika Hingorani, V. Niranjan
The evolution of portable electronic devices and their widespread application has led to an increased focus on power dissipation as one of the critical parameters. An increase in functionality requirement and design complexity on a single chip has resulted in increased power dissipation. High power dissipation has motivated study and innovation on low power circuit design techniques. Adiabatic logic has been studied as one of the design techniques to reduce power dissipation by reusing the power that was getting dissipated in conventional designs. This paper presents the application of Wave Shaping Diode Adiabatic Logic (WSDAL) to implement an ALU and analyse the improvement in power dissipation as compared to the conventional CMOS design. The WSDAL design uses a slow and time-fluctuating 2-phase sinusoidal Power Clock (PC), which supplies power as well as a clock to the designs. WSDAL uses an Ultra-Low Power Diode (ULPD) structure that operates as a wave shaping device and reduces glitches at the output. The design has been implemented in OrCAD Capture and simulated using Pspice in TSMC 180nm technology. The simulations were performed at 200MHz PC frequency and power dissipation was studied over a range of voltages from 1.4V to 2.2V. The simulations show that WSDAL ALU dissipates less power than the CMOS design. This study indicates that WSDAL-based designs have the potential to be deployed for power dissipation reduction in portable devices.
随着便携式电子设备的发展和广泛应用，功耗作为关键参数之一受到越来越多的关注。单个芯片上功能需求和设计复杂性的增加导致了功耗的增加。高功耗激发了低功耗电路设计技术的研究和创新。绝热逻辑是一种利用传统设计中消耗的功率来降低功耗的设计技术。本文介绍了用波形整形二极管绝热逻辑(WSDAL)来实现ALU，并分析了与传统CMOS设计相比在功耗方面的改进。WSDAL设计使用慢速且时间波动的两相正弦功率时钟(PC)，它为设计提供电源和时钟。WSDAL使用超低功率二极管(Ultra-Low Power Diode, ULPD)结构，作为波形整形器件，减少输出端的小故障。该设计已在OrCAD Capture中实现，并使用台积电180nm工艺的Pspice进行了仿真。仿真在200MHz PC频率下进行，并研究了1.4V至2.2V电压范围内的功耗。仿真结果表明，与CMOS设计相比，WSDAL ALU功耗更低。这项研究表明，基于wsdl的设计具有在便携式设备中用于降低功耗的潜力。
{"title":"Low Power ALU using Wave Shaping Diode Adiabatic Logic","authors":"Ishita Khindria, Kashika Hingorani, V. Niranjan","doi":"10.54105/ijvlsid.d1209.091422","DOIUrl":"https://doi.org/10.54105/ijvlsid.d1209.091422","url":null,"abstract":"The evolution of portable electronic devices and their widespread application has led to an increased focus on power dissipation as one of the critical parameters. An increase in functionality requirement and design complexity on a single chip has resulted in increased power dissipation. High power dissipation has motivated study and innovation on low power circuit design techniques. Adiabatic logic has been studied as one of the design techniques to reduce power dissipation by reusing the power that was getting dissipated in conventional designs. This paper presents the application of Wave Shaping Diode Adiabatic Logic (WSDAL) to implement an ALU and analyse the improvement in power dissipation as compared to the conventional CMOS design. The WSDAL design uses a slow and time-fluctuating 2-phase sinusoidal Power Clock (PC), which supplies power as well as a clock to the designs. WSDAL uses an Ultra-Low Power Diode (ULPD) structure that operates as a wave shaping device and reduces glitches at the output. The design has been implemented in OrCAD Capture and simulated using Pspice in TSMC 180nm technology. The simulations were performed at 200MHz PC frequency and power dissipation was studied over a range of voltages from 1.4V to 2.2V. The simulations show that WSDAL ALU dissipates less power than the CMOS design. This study indicates that WSDAL-based designs have the potential to be deployed for power dissipation reduction in portable devices.","PeriodicalId":275481,"journal":{"name":"Indian Journal of VLSI Design","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122113401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-09-30DOI: 10.54105/ijvlsid.b1210.092222
Nibha Kumari, Prof. Vandana Niranjan
Static Random-Access Memory (SRAM) occupies approximately 90% of total area on a chip due to high number of transistors used for a single SRAM cell. Therefore, SRAM cell becomes a power-hungry block on a chip and it becomes more prominent at lower technologies from both dynamic and static perspective. Static power consumption is due to leakage current associated with the transistors that are off and dynamic power consumption is due to charging and discharging of the circuit capacitance. As gate length or channel length decreases gate oxide thickness also scales down. Scaling down of conventional transistor results in huge tunneling of electron from gate into channel leading to higher leakage power consumption. So, transistor with metal gate, high-k dielectric and strained-Si is used which shows better result in terms of low-power consumption, better performance with acceptable delay. Among various topologies of SRAM cell 6T is considered as a suitable choice for low power applications.
{"title":"Low-Power 6T SRAM Cell using 22nm CMOS Technology","authors":"Nibha Kumari, Prof. Vandana Niranjan","doi":"10.54105/ijvlsid.b1210.092222","DOIUrl":"https://doi.org/10.54105/ijvlsid.b1210.092222","url":null,"abstract":"Static Random-Access Memory (SRAM) occupies approximately 90% of total area on a chip due to high number of transistors used for a single SRAM cell. Therefore, SRAM cell becomes a power-hungry block on a chip and it becomes more prominent at lower technologies from both dynamic and static perspective. Static power consumption is due to leakage current associated with the transistors that are off and dynamic power consumption is due to charging and discharging of the circuit capacitance. As gate length or channel length decreases gate oxide thickness also scales down. Scaling down of conventional transistor results in huge tunneling of electron from gate into channel leading to higher leakage power consumption. So, transistor with metal gate, high-k dielectric and strained-Si is used which shows better result in terms of low-power consumption, better performance with acceptable delay. Among various topologies of SRAM cell 6T is considered as a suitable choice for low power applications.","PeriodicalId":275481,"journal":{"name":"Indian Journal of VLSI Design","volume":"323 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132420076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-03-30DOI: 10.54105/ijvlsid.c1207.031322
Dr.E.N. Ganesh.
The objective of the project is to design a low cost Spectral Monitor for a Space vehicle velocity measurement application, based on Doppler Shift principle by generating an radar signal source from earth station towards moving target device in space and processing received high speed analog 200MHz radar signal from target vehicle device through Antenna, analog pre-processing and FPGA based spectral analyzer. The hardware reconfigurable spectral analyzer design consist of ADC(500MSPS) Interface block, SRAM Memory(1024x16) block, Radix-2 FFT (16 bit DSP block) and LCD Display (Monitoring) driver algorithm implemented On-Chip SOC-FPGA system. The proposed algorithm can be used to meet the need of many real time application such as space exploration, wideband communication, command and control application. The desired algorithm is implemented on-chip reconfigurable hardware SOC-FPGA while keeping the cost, power and area of device low compared to general purpose processor and Embedded based microcontroller. The code architecture is described using hardware description language, VHDL and synthesized and simulated using Xilinx 12.2 ISE Design suite.
本课题的目标是基于多普勒频移原理，从地面站向空间运动目标装置产生雷达信号源，通过天线、模拟预处理和基于FPGA的频谱分析仪处理接收到的来自目标装置的200MHz高速模拟雷达信号，为空间飞行器测速应用设计一种低成本的频谱监测仪。硬件可重构频谱分析仪设计由ADC(500MSPS)接口块、SRAM (1024x16)内存块、Radix-2 FFT(16位DSP块)和LCD显示(监控)驱动算法组成，实现片上SOC-FPGA系统。该算法可满足空间探测、宽带通信、指挥控制等实时应用的需要。所需的算法在片上可重构硬件SOC-FPGA上实现，同时与通用处理器和嵌入式微控制器相比，保持低成本，低功耗和低面积。采用硬件描述语言VHDL对代码体系结构进行了描述，并使用Xilinx 12.2 ISE Design套件进行了合成和仿真。
{"title":"Analysis of Velocity Measurement of Radar Signal in Space Vehicle Application using VLSI Chip","authors":"Dr.E.N. Ganesh.","doi":"10.54105/ijvlsid.c1207.031322","DOIUrl":"https://doi.org/10.54105/ijvlsid.c1207.031322","url":null,"abstract":"The objective of the project is to design a low cost Spectral Monitor for a Space vehicle velocity measurement application, based on Doppler Shift principle by generating an radar signal source from earth station towards moving target device in space and processing received high speed analog 200MHz radar signal from target vehicle device through Antenna, analog pre-processing and FPGA based spectral analyzer. The hardware reconfigurable spectral analyzer design consist of ADC(500MSPS) Interface block, SRAM Memory(1024x16) block, Radix-2 FFT (16 bit DSP block) and LCD Display (Monitoring) driver algorithm implemented On-Chip SOC-FPGA system. The proposed algorithm can be used to meet the need of many real time application such as space exploration, wideband communication, command and control application. The desired algorithm is implemented on-chip reconfigurable hardware SOC-FPGA while keeping the cost, power and area of device low compared to general purpose processor and Embedded based microcontroller. The code architecture is described using hardware description language, VHDL and synthesized and simulated using Xilinx 12.2 ISE Design suite.","PeriodicalId":275481,"journal":{"name":"Indian Journal of VLSI Design","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131655915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-03-30DOI: 10.54105/ijvlsid.c1206.031322
Vineeta Singh, Sarika Parihar, V. Niranjan
The paper presents the various trans-impedance amplifier (TIA) topologies has been studied and presented with an insight of their Gain and Bandwidth. The device parameters such as gain and bandwidth has been studied and compared for various TIA topologies. The performance of the presented topologies of TIA has been compared and summarized to get an overview. The comparison is done on the basis of its topology and device technology along with gain, bandwidth and power supply. In this paper recent advancement and future scope are also discussed.
{"title":"A Comparative Analysis of Gain and Bandwidth of CMOS Transimpedance Amplifier","authors":"Vineeta Singh, Sarika Parihar, V. Niranjan","doi":"10.54105/ijvlsid.c1206.031322","DOIUrl":"https://doi.org/10.54105/ijvlsid.c1206.031322","url":null,"abstract":"The paper presents the various trans-impedance amplifier (TIA) topologies has been studied and presented with an insight of their Gain and Bandwidth. The device parameters such as gain and bandwidth has been studied and compared for various TIA topologies. The performance of the presented topologies of TIA has been compared and summarized to get an overview. The comparison is done on the basis of its topology and device technology along with gain, bandwidth and power supply. In this paper recent advancement and future scope are also discussed.","PeriodicalId":275481,"journal":{"name":"Indian Journal of VLSI Design","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114303499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-03-10DOI: 10.35940/ijvlsid.c1204.031322
Shurbhit Surage, M. Chawla
The relevance of electricity generation from renewable energy sources is growing every day in the current global energy environment. The scarcity of fossil fuels and the environmental risks connected with traditional power producing methods are the main reasons behind this. The major sources of non-conventional energy are wind and solar which can be harnessed easily. A new system design for hybrid photovoltaic and wind-power generation is introduced within this study. A Modified M.P.P.T. has been proposed to strengthen productivity of this system. The proposed approach employs the Incremental Conductance (IC) MPPT technique. Under varied climatic conditions (Solar irradiance & Temperature), IC is utilized to determine the optimum voltage output of a photo voltaic generator (P.V.G.) within the photo voltaic system (P.V.) structure. The Incremental Conductance is utilized to manage the converter’s technology having boosting function. The P.M.S.G. is used to determine the maximum voltage output for varied wind flow rates in wind turbine system. Simulations are conducted in Matlab2019b to test efficacy of the proposed MPPT. The proposed scheme's effectiveness can be supported with simulation results.
{"title":"Hybrid Renewable Energy Generation Through Incremental Conductance Mppt","authors":"Shurbhit Surage, M. Chawla","doi":"10.35940/ijvlsid.c1204.031322","DOIUrl":"https://doi.org/10.35940/ijvlsid.c1204.031322","url":null,"abstract":"The relevance of electricity generation from renewable energy sources is growing every day in the current global energy environment. The scarcity of fossil fuels and the environmental risks connected with traditional power producing methods are the main reasons behind this. The major sources of non-conventional energy are wind and solar which can be harnessed easily. A new system design for hybrid photovoltaic and wind-power generation is introduced within this study. A Modified M.P.P.T. has been proposed to strengthen productivity of this system. The proposed approach employs the Incremental Conductance (IC) MPPT technique. Under varied climatic conditions (Solar irradiance & Temperature), IC is utilized to determine the optimum voltage output of a photo voltaic generator (P.V.G.) within the photo voltaic system (P.V.) structure. The Incremental Conductance is utilized to manage the converter’s technology having boosting function. The P.M.S.G. is used to determine the maximum voltage output for varied wind flow rates in wind turbine system. Simulations are conducted in Matlab2019b to test efficacy of the proposed MPPT. The proposed scheme's effectiveness can be supported with simulation results.","PeriodicalId":275481,"journal":{"name":"Indian Journal of VLSI Design","volume":"224 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123288001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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