Pub Date : 1993-06-01DOI: 10.1109/ECTC.1993.346768
H. Karstensen, C. Hanke, M. Honsberg
The design, set-up, and characterisation of a fixed length multi-channel parallel optical interconnection cable with electrical connectors (miniature sub-D connectors) at either sides is presented. The link is electrically compatible to ECL voltage level. Ribbons of both standard 1.3 /spl mu/m single-mode and graded-index multimode fibers are used as interconnection medium. The laser diodes are GaAs SQW LD (single quantum well) with very low threshold current. The photodiodes are made of silicon. The number of channels is 4, an upgrading to 12 channels is also presented.<>
{"title":"DC-coupled parallel optical interconnect cable with fiber ribbon","authors":"H. Karstensen, C. Hanke, M. Honsberg","doi":"10.1109/ECTC.1993.346768","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346768","url":null,"abstract":"The design, set-up, and characterisation of a fixed length multi-channel parallel optical interconnection cable with electrical connectors (miniature sub-D connectors) at either sides is presented. The link is electrically compatible to ECL voltage level. Ribbons of both standard 1.3 /spl mu/m single-mode and graded-index multimode fibers are used as interconnection medium. The laser diodes are GaAs SQW LD (single quantum well) with very low threshold current. The photodiodes are made of silicon. The number of channels is 4, an upgrading to 12 channels is also presented.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131706007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-06-01DOI: 10.1109/ECTC.1993.346797
C. S. Chang
To approximate the frequency dependence of the characteristic impedance and signal attenuation of a DC resistive transmission line, we propose formulas with one pole and one zero on the negative real axis. We then derive the algebraic time-domain solutions for the near-end and far-end voltages of this line, which is driven by a constant resistance source. The far-end of this line is either open circuited or terminated by a constant resistance load. Nomographs to guide the MCM wiring net designs are also developed and presented.<>
{"title":"Resistive signal line wiring net designs in multichip modules","authors":"C. S. Chang","doi":"10.1109/ECTC.1993.346797","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346797","url":null,"abstract":"To approximate the frequency dependence of the characteristic impedance and signal attenuation of a DC resistive transmission line, we propose formulas with one pole and one zero on the negative real axis. We then derive the algebraic time-domain solutions for the near-end and far-end voltages of this line, which is driven by a constant resistance source. The far-end of this line is either open circuited or terminated by a constant resistance load. Nomographs to guide the MCM wiring net designs are also developed and presented.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133470566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-06-01DOI: 10.1109/ECTC.1993.346738
H. Hashemi, M. Olla, D. Cobb, P. Sandborn, M. McShane, G. Hawkins, P. Lin
A low-cost multichip module (MCM) package has been developed to house a 40 MHz digital signal processor static RAM chipset. A design and prototype effort was undertaken to design, procure, assemble, and test these modules. The design constraint was to merge a state-of-the-art high-density interconnect substrate with conventional chip assembly techniques while meeting a prespecified cost goal. The package concept is that of an MCM-L substrate with more than one chip, where the chips are connected to the substrate by means of conventional gold wire bonding and the part is overmolded. A mix of solder balls and peripheral leads is used to interface to the package. The mix of package connectorization approaches is used to increase the routing resources, decouple the signal and power/ground distribution, and provide good thermal coupling between the package and the next level board. Issues such as board layout, component design and fabrication, board assembly, and first-order cost models are discussed.<>
{"title":"A mixed solder grid array and peripheral leaded MCM package","authors":"H. Hashemi, M. Olla, D. Cobb, P. Sandborn, M. McShane, G. Hawkins, P. Lin","doi":"10.1109/ECTC.1993.346738","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346738","url":null,"abstract":"A low-cost multichip module (MCM) package has been developed to house a 40 MHz digital signal processor static RAM chipset. A design and prototype effort was undertaken to design, procure, assemble, and test these modules. The design constraint was to merge a state-of-the-art high-density interconnect substrate with conventional chip assembly techniques while meeting a prespecified cost goal. The package concept is that of an MCM-L substrate with more than one chip, where the chips are connected to the substrate by means of conventional gold wire bonding and the part is overmolded. A mix of solder balls and peripheral leads is used to interface to the package. The mix of package connectorization approaches is used to increase the routing resources, decouple the signal and power/ground distribution, and provide good thermal coupling between the package and the next level board. Issues such as board layout, component design and fabrication, board assembly, and first-order cost models are discussed.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114463550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-06-01DOI: 10.1109/ECTC.1993.346715
V. Patel, W.C. Mak, B. Rice, L. Feinstein
A transient thermal impedance tester design and its general capabilities are presented. Transient temperature measurements on several power IC packages are obtained. Transient responses of the package subjected to repetitive pulses and to a complex transient power pulse are presented. Temperature measurements on a test chip are compared with the solution as obtained from transient thermal finite element analysis. The effects of measurement delay time on junction temperature measurement are discussed.<>
{"title":"Transient thermal impedance tester for power IC packages","authors":"V. Patel, W.C. Mak, B. Rice, L. Feinstein","doi":"10.1109/ECTC.1993.346715","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346715","url":null,"abstract":"A transient thermal impedance tester design and its general capabilities are presented. Transient temperature measurements on several power IC packages are obtained. Transient responses of the package subjected to repetitive pulses and to a complex transient power pulse are presented. Temperature measurements on a test chip are compared with the solution as obtained from transient thermal finite element analysis. The effects of measurement delay time on junction temperature measurement are discussed.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115922862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-06-01DOI: 10.1109/ECTC.1993.346719
Y. Tsukada, Y. Mashimoto, N. Watanuki
In FCA (Flip Chip Attach) technology, the encapsulation for the flip chip joints relieves the stress which is supposed to be concentrated on these joints by the thermal cycling of the system. It allows us to use low cost-material such as epoxy for a carrier of flip chip bonding though it has significantly higher CTE than ceramic. However, the chip replacement after encapsulation becomes difficult when it is found to be defective. To resolve this problem, we have developed a simple replacement technique. In this technique, the encapsulated chip for replacement is ground off with about a half height of encapsulation. After providing carrier bumps with solder injection, a new chip is placed and the joining cycle is followed with the same manner of initial chip join. The reliability of the joints showed the same level as the initially built joints. This technique can be applied for the replacement of any kind of encapsulated flip chip bonding.<>
{"title":"A novel chip replacement method for encapsulated flip chip bonding","authors":"Y. Tsukada, Y. Mashimoto, N. Watanuki","doi":"10.1109/ECTC.1993.346719","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346719","url":null,"abstract":"In FCA (Flip Chip Attach) technology, the encapsulation for the flip chip joints relieves the stress which is supposed to be concentrated on these joints by the thermal cycling of the system. It allows us to use low cost-material such as epoxy for a carrier of flip chip bonding though it has significantly higher CTE than ceramic. However, the chip replacement after encapsulation becomes difficult when it is found to be defective. To resolve this problem, we have developed a simple replacement technique. In this technique, the encapsulated chip for replacement is ground off with about a half height of encapsulation. After providing carrier bumps with solder injection, a new chip is placed and the joining cycle is followed with the same manner of initial chip join. The reliability of the joints showed the same level as the initially built joints. This technique can be applied for the replacement of any kind of encapsulated flip chip bonding.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115289831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-06-01DOI: 10.1109/ECTC.1993.346845
E. Gouno, G. Deleuze, M. Brizoux, C. Robert
This paper proposes a new approach of electronic components reliability using Bayesian statistics. The purpose is to estimate the failure rate in use conditions through data from accelerated tests. Priors densities used in the model has been built with physics considerations and simulations. Furthermore, this work provided new forms of accelerated factors.<>
{"title":"Bayesian approach of failure rate estimation in field conditions through accelerated testing","authors":"E. Gouno, G. Deleuze, M. Brizoux, C. Robert","doi":"10.1109/ECTC.1993.346845","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346845","url":null,"abstract":"This paper proposes a new approach of electronic components reliability using Bayesian statistics. The purpose is to estimate the failure rate in use conditions through data from accelerated tests. Priors densities used in the model has been built with physics considerations and simulations. Furthermore, this work provided new forms of accelerated factors.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124969547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-06-01DOI: 10.1109/ECTC.1993.346810
B. Beaman, Daniel Shih, G. Walker
Elastomeric connectors are a relatively new technology compared with conventional connector systems. A wide variety of elastomeric connectors are available today to meet the interconnection requirements for many different electronic packaging applications. Multichip modules are one of the many applications that benefit from the high density interconnection capabilities of elastomeric connectors. The ELASTICON connector is a new high performance elastomeric connector that was developed to address some of the key limitations of existing MCM and land grid array connectors. The ELASTICON connector uses gold or gold alloy wires for the conductive elements embedded in an elastomer material. The size, shape and spacing along with the elastomer material properties can be tailored to specific application requirements. The processes that have been developed for fabricating the ELASTICON connector represent a new direction for elastomeric connector manufacturing. Besides LGA packaging applications, ELASTICON connectors can be used for board-to-board and cable-to-board interconnections as well as high density PCB and IC chip testing applications.<>
{"title":"A new direction for elastomeric connectors","authors":"B. Beaman, Daniel Shih, G. Walker","doi":"10.1109/ECTC.1993.346810","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346810","url":null,"abstract":"Elastomeric connectors are a relatively new technology compared with conventional connector systems. A wide variety of elastomeric connectors are available today to meet the interconnection requirements for many different electronic packaging applications. Multichip modules are one of the many applications that benefit from the high density interconnection capabilities of elastomeric connectors. The ELASTICON connector is a new high performance elastomeric connector that was developed to address some of the key limitations of existing MCM and land grid array connectors. The ELASTICON connector uses gold or gold alloy wires for the conductive elements embedded in an elastomer material. The size, shape and spacing along with the elastomer material properties can be tailored to specific application requirements. The processes that have been developed for fabricating the ELASTICON connector represent a new direction for elastomeric connector manufacturing. Besides LGA packaging applications, ELASTICON connectors can be used for board-to-board and cable-to-board interconnections as well as high density PCB and IC chip testing applications.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123508535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-06-01DOI: 10.1109/ECTC.1993.346743
D. Norwood, W. Worobey, D. Peterson, D. Miller
Sandia National Laboratories is developing diamond substrate technology to meet the requirements of high thermal conductivity. Thin-film processes were developed and characterized to delineate conductor-resistor networks on free-standing diamond substrates having fine line gold conductors and low and high sheet resistivity resistors. Thin-film hybrid circuit technology was developed on CVD (chemical vapor deposition)-processed, polycrystalline diamond substrates having as-deposited surface finishes as well as those with polished surfaces. Conductors were defined by pattern plating gold and resistors were processed from sputtered tantalum nitride films which were deposited to sheet resistivities of 5 and/or 100 ohms per square. Resistor films on diamond substrates were evaluated for temperature coefficient of resistance (TCR), stability with time and temperature, and trimmability using YAG laser processing. Plated gold conductors were patterned on diamond to feature sizes of 25 microns and successfully tested for adhesion and bondability. Advanced YAG laser trimming techniques were developed to allow resistor trims on both low and high value resistors to within 1% of design value while maintaining required resistor stability.<>
{"title":"Diamond-a new high thermal conductivity substrate for multichip modules and hybrid circuits","authors":"D. Norwood, W. Worobey, D. Peterson, D. Miller","doi":"10.1109/ECTC.1993.346743","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346743","url":null,"abstract":"Sandia National Laboratories is developing diamond substrate technology to meet the requirements of high thermal conductivity. Thin-film processes were developed and characterized to delineate conductor-resistor networks on free-standing diamond substrates having fine line gold conductors and low and high sheet resistivity resistors. Thin-film hybrid circuit technology was developed on CVD (chemical vapor deposition)-processed, polycrystalline diamond substrates having as-deposited surface finishes as well as those with polished surfaces. Conductors were defined by pattern plating gold and resistors were processed from sputtered tantalum nitride films which were deposited to sheet resistivities of 5 and/or 100 ohms per square. Resistor films on diamond substrates were evaluated for temperature coefficient of resistance (TCR), stability with time and temperature, and trimmability using YAG laser processing. Plated gold conductors were patterned on diamond to feature sizes of 25 microns and successfully tested for adhesion and bondability. Advanced YAG laser trimming techniques were developed to allow resistor trims on both low and high value resistors to within 1% of design value while maintaining required resistor stability.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121082611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-06-01DOI: 10.1109/ECTC.1993.346829
G. Subbarayan, K. Ramakrishna, B. Sammakia, P.C. Chen
The reliability of vias used in thin film packages was estimated through analytical and numerical models. Several processes that produce thermally induced strains in the vias during manufacture, assembly (e.g., card and heat sink attach, and encapsulation of the chip), and stress-tests (e.g., T&H, ship shock, and accelerated thermal cycling) were evaluated to determine the steps which induced potentially high strains in the vias. The study consisted of two parts. In the first part, a preliminary analysis was made in which analytical estimates of via strains during the various processes were obtained under the assumptions of linear elasticity. In the second part of the study, detailed elastic-plastic finite element analyses were carried out to determine the via strains during the various processes. The models were two-dimensional, axi-symmetric in nature. In addition to uniformly plated vias, the study also included analysis of non-uniformly plated vias. In both parts of the study, via strain during a single cycle of ATC (accelerated thermal cycle) was combined with the Coffin-Manson equation for plated copper to determine the number of ATC cycles to failure. Via plating thicknesses analyzed were in the range of 0.5 to 1.4 mils. It was concluded from the study that if the via was manufacturable, then it would survive the accelerated thermal cycling test and hence the field use. This conclusion was in agreement with the results of an ATC test conducted on products with uniformly plated vias. Another conclusion from the study was that vias with non-uniform plating were unlikely to survive the rigors of the manufacturing processes.<>
{"title":"Mechanical integrity of vias in a thin-film package during manufacture, assembly, and stress-test","authors":"G. Subbarayan, K. Ramakrishna, B. Sammakia, P.C. Chen","doi":"10.1109/ECTC.1993.346829","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346829","url":null,"abstract":"The reliability of vias used in thin film packages was estimated through analytical and numerical models. Several processes that produce thermally induced strains in the vias during manufacture, assembly (e.g., card and heat sink attach, and encapsulation of the chip), and stress-tests (e.g., T&H, ship shock, and accelerated thermal cycling) were evaluated to determine the steps which induced potentially high strains in the vias. The study consisted of two parts. In the first part, a preliminary analysis was made in which analytical estimates of via strains during the various processes were obtained under the assumptions of linear elasticity. In the second part of the study, detailed elastic-plastic finite element analyses were carried out to determine the via strains during the various processes. The models were two-dimensional, axi-symmetric in nature. In addition to uniformly plated vias, the study also included analysis of non-uniformly plated vias. In both parts of the study, via strain during a single cycle of ATC (accelerated thermal cycle) was combined with the Coffin-Manson equation for plated copper to determine the number of ATC cycles to failure. Via plating thicknesses analyzed were in the range of 0.5 to 1.4 mils. It was concluded from the study that if the via was manufacturable, then it would survive the accelerated thermal cycling test and hence the field use. This conclusion was in agreement with the results of an ATC test conducted on products with uniformly plated vias. Another conclusion from the study was that vias with non-uniform plating were unlikely to survive the rigors of the manufacturing processes.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125406850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-06-01DOI: 10.1109/ECTC.1993.346754
Y. Arai, H. Takahara, K. Koyabu, S. Fujita, Y. Akahori, J. Nishikido
2.8-Gbit/s, 3-channel optical transmitter and receiver modules have been developed for board-to-board interconnection in Asynchronous Transfer Mode (ATM) switching systems. These modules are constructed with optical and electrical submodules. The optical submodule mainly consists of a multimode-fiber array and an optical device array. The electrical submodule is constructed by using multichip module technology with GaAs ICs and multilayer ceramic substrates. These submodules are independently assembled after they are tested. Over a wide range of temperatures, error-free 250-m transmission is successfully demonstrated without automatic power-control and automatic temperature control circuits in the transmitter module.<>
{"title":"Multigigabit multichannel optical interconnection modules for asynchronous transfer mode switching systems","authors":"Y. Arai, H. Takahara, K. Koyabu, S. Fujita, Y. Akahori, J. Nishikido","doi":"10.1109/ECTC.1993.346754","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346754","url":null,"abstract":"2.8-Gbit/s, 3-channel optical transmitter and receiver modules have been developed for board-to-board interconnection in Asynchronous Transfer Mode (ATM) switching systems. These modules are constructed with optical and electrical submodules. The optical submodule mainly consists of a multimode-fiber array and an optical device array. The electrical submodule is constructed by using multichip module technology with GaAs ICs and multilayer ceramic substrates. These submodules are independently assembled after they are tested. Over a wide range of temperatures, error-free 250-m transmission is successfully demonstrated without automatic power-control and automatic temperature control circuits in the transmitter module.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126311501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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