Pub Date : 1993-06-01DOI: 10.1109/ECTC.1993.346768
H. Karstensen, C. Hanke, M. Honsberg
The design, set-up, and characterisation of a fixed length multi-channel parallel optical interconnection cable with electrical connectors (miniature sub-D connectors) at either sides is presented. The link is electrically compatible to ECL voltage level. Ribbons of both standard 1.3 /spl mu/m single-mode and graded-index multimode fibers are used as interconnection medium. The laser diodes are GaAs SQW LD (single quantum well) with very low threshold current. The photodiodes are made of silicon. The number of channels is 4, an upgrading to 12 channels is also presented.<>
{"title":"DC-coupled parallel optical interconnect cable with fiber ribbon","authors":"H. Karstensen, C. Hanke, M. Honsberg","doi":"10.1109/ECTC.1993.346768","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346768","url":null,"abstract":"The design, set-up, and characterisation of a fixed length multi-channel parallel optical interconnection cable with electrical connectors (miniature sub-D connectors) at either sides is presented. The link is electrically compatible to ECL voltage level. Ribbons of both standard 1.3 /spl mu/m single-mode and graded-index multimode fibers are used as interconnection medium. The laser diodes are GaAs SQW LD (single quantum well) with very low threshold current. The photodiodes are made of silicon. The number of channels is 4, an upgrading to 12 channels is also presented.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131706007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-06-01DOI: 10.1109/ECTC.1993.346797
C. S. Chang
To approximate the frequency dependence of the characteristic impedance and signal attenuation of a DC resistive transmission line, we propose formulas with one pole and one zero on the negative real axis. We then derive the algebraic time-domain solutions for the near-end and far-end voltages of this line, which is driven by a constant resistance source. The far-end of this line is either open circuited or terminated by a constant resistance load. Nomographs to guide the MCM wiring net designs are also developed and presented.<>
{"title":"Resistive signal line wiring net designs in multichip modules","authors":"C. S. Chang","doi":"10.1109/ECTC.1993.346797","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346797","url":null,"abstract":"To approximate the frequency dependence of the characteristic impedance and signal attenuation of a DC resistive transmission line, we propose formulas with one pole and one zero on the negative real axis. We then derive the algebraic time-domain solutions for the near-end and far-end voltages of this line, which is driven by a constant resistance source. The far-end of this line is either open circuited or terminated by a constant resistance load. Nomographs to guide the MCM wiring net designs are also developed and presented.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133470566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-06-01DOI: 10.1109/ECTC.1993.346793
S. Ray, D. Berger, G. Czornyj, A. Kumar, R. Tummala
This paper describes a fabrication method for multilevel, thin film wiring in which each wiring level and a solid via or stud to the level below, are formed as one integral unit. The processing scheme described makes use of a photosensitive polyimide (PSPI) for defining the wiring channels and a non-photosensitive polyimide for the vias. The via opening in the non-photosensitive polyimide is formed by laser ablation while the wiring channels are formed in the PSPI layer by photolithography. The via hole and the channels in the PSPI are filled in the same metallization step consisting of electroplating copper over a sputtered seed layer. The wiring pattern is finally delineated when a planarization step removes the excess plated copper. This processing method, which we refer to as the Dual Layer Metallization (DLM) method, is found to be very economical, in terms of the number of process steps involved, for forming multilevel, polyimide-copper wiring structures.<>
{"title":"Dual-Level Metal (DLM) method for fabricating thin film wiring structures","authors":"S. Ray, D. Berger, G. Czornyj, A. Kumar, R. Tummala","doi":"10.1109/ECTC.1993.346793","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346793","url":null,"abstract":"This paper describes a fabrication method for multilevel, thin film wiring in which each wiring level and a solid via or stud to the level below, are formed as one integral unit. The processing scheme described makes use of a photosensitive polyimide (PSPI) for defining the wiring channels and a non-photosensitive polyimide for the vias. The via opening in the non-photosensitive polyimide is formed by laser ablation while the wiring channels are formed in the PSPI layer by photolithography. The via hole and the channels in the PSPI are filled in the same metallization step consisting of electroplating copper over a sputtered seed layer. The wiring pattern is finally delineated when a planarization step removes the excess plated copper. This processing method, which we refer to as the Dual Layer Metallization (DLM) method, is found to be very economical, in terms of the number of process steps involved, for forming multilevel, polyimide-copper wiring structures.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125079824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-06-01DOI: 10.1109/ECTC.1993.346829
G. Subbarayan, K. Ramakrishna, B. Sammakia, P.C. Chen
The reliability of vias used in thin film packages was estimated through analytical and numerical models. Several processes that produce thermally induced strains in the vias during manufacture, assembly (e.g., card and heat sink attach, and encapsulation of the chip), and stress-tests (e.g., T&H, ship shock, and accelerated thermal cycling) were evaluated to determine the steps which induced potentially high strains in the vias. The study consisted of two parts. In the first part, a preliminary analysis was made in which analytical estimates of via strains during the various processes were obtained under the assumptions of linear elasticity. In the second part of the study, detailed elastic-plastic finite element analyses were carried out to determine the via strains during the various processes. The models were two-dimensional, axi-symmetric in nature. In addition to uniformly plated vias, the study also included analysis of non-uniformly plated vias. In both parts of the study, via strain during a single cycle of ATC (accelerated thermal cycle) was combined with the Coffin-Manson equation for plated copper to determine the number of ATC cycles to failure. Via plating thicknesses analyzed were in the range of 0.5 to 1.4 mils. It was concluded from the study that if the via was manufacturable, then it would survive the accelerated thermal cycling test and hence the field use. This conclusion was in agreement with the results of an ATC test conducted on products with uniformly plated vias. Another conclusion from the study was that vias with non-uniform plating were unlikely to survive the rigors of the manufacturing processes.<>
{"title":"Mechanical integrity of vias in a thin-film package during manufacture, assembly, and stress-test","authors":"G. Subbarayan, K. Ramakrishna, B. Sammakia, P.C. Chen","doi":"10.1109/ECTC.1993.346829","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346829","url":null,"abstract":"The reliability of vias used in thin film packages was estimated through analytical and numerical models. Several processes that produce thermally induced strains in the vias during manufacture, assembly (e.g., card and heat sink attach, and encapsulation of the chip), and stress-tests (e.g., T&H, ship shock, and accelerated thermal cycling) were evaluated to determine the steps which induced potentially high strains in the vias. The study consisted of two parts. In the first part, a preliminary analysis was made in which analytical estimates of via strains during the various processes were obtained under the assumptions of linear elasticity. In the second part of the study, detailed elastic-plastic finite element analyses were carried out to determine the via strains during the various processes. The models were two-dimensional, axi-symmetric in nature. In addition to uniformly plated vias, the study also included analysis of non-uniformly plated vias. In both parts of the study, via strain during a single cycle of ATC (accelerated thermal cycle) was combined with the Coffin-Manson equation for plated copper to determine the number of ATC cycles to failure. Via plating thicknesses analyzed were in the range of 0.5 to 1.4 mils. It was concluded from the study that if the via was manufacturable, then it would survive the accelerated thermal cycling test and hence the field use. This conclusion was in agreement with the results of an ATC test conducted on products with uniformly plated vias. Another conclusion from the study was that vias with non-uniform plating were unlikely to survive the rigors of the manufacturing processes.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125406850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-06-01DOI: 10.1109/ECTC.1993.346839
R. Pufall
For the real-time recording of essential bond parameters: bond-force; ultrasonic amplitude; bonding time; during the bonding process, sensors are applied to the bond arm. The methods (measuring procedures) and necessary hardware and software for the monitoring of the measured values have been developed. Strain gauges are fixed to the bond arm and provide a signal proportional to the applied bond-force. A piezo-ceramic sensor is attached to the horn of the bond arm to measure the amplitude of the ultrasound. The bond-time is deducible from the duration of the ultrasonic signal. The electrical signals are recorded and interpreted in real-time using a PC compatible PCD3T (Siemens) computer. The sensorised bond arm can be used advantageously with either nail-head or wedge-wedge bond machines, with both thick and thin wire bonds. Results are discussed for 25 /spl mu/m Al-wire bonds on different surfaces. To show correlation for ultrasound and bond-sticking, frequency-distributions are presented. To check bond quality, extensive shear tests and pull tests were performed. Results show that shear tests are more sensitive to bond quality than pull tests. The data from automatic process control can be used to substitute SPC (Statistical Process Control) and minimise destructive tests. Bond quality can be monitored by observing the 2nd harmonic of the ultrasonic signal. Bond parameters drifting towards bad bond quality can be avoided.<>
{"title":"Automatic process control of wire bonding","authors":"R. Pufall","doi":"10.1109/ECTC.1993.346839","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346839","url":null,"abstract":"For the real-time recording of essential bond parameters: bond-force; ultrasonic amplitude; bonding time; during the bonding process, sensors are applied to the bond arm. The methods (measuring procedures) and necessary hardware and software for the monitoring of the measured values have been developed. Strain gauges are fixed to the bond arm and provide a signal proportional to the applied bond-force. A piezo-ceramic sensor is attached to the horn of the bond arm to measure the amplitude of the ultrasound. The bond-time is deducible from the duration of the ultrasonic signal. The electrical signals are recorded and interpreted in real-time using a PC compatible PCD3T (Siemens) computer. The sensorised bond arm can be used advantageously with either nail-head or wedge-wedge bond machines, with both thick and thin wire bonds. Results are discussed for 25 /spl mu/m Al-wire bonds on different surfaces. To show correlation for ultrasound and bond-sticking, frequency-distributions are presented. To check bond quality, extensive shear tests and pull tests were performed. Results show that shear tests are more sensitive to bond quality than pull tests. The data from automatic process control can be used to substitute SPC (Statistical Process Control) and minimise destructive tests. Bond quality can be monitored by observing the 2nd harmonic of the ultrasonic signal. Bond parameters drifting towards bad bond quality can be avoided.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125486297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-06-01DOI: 10.1109/ECTC.1993.346762
D. L. Robinson, R. Brady, I. M. Higgins
Mismatches in thermal expansion between encapsulant, die and substrate lead to stresses that can cause failures in thermal cycling of electronic parts. These stresses become especially troublesome as die size increases. In order to minimize failures, low stress encapsulants are needed. This paper describes development of a low stress silicon-carbon liquid encapsulant. Development was done on multichip modules (MCM-L) with large die. In order to develop a low stress encapsulant, a designed experiment was run. Variables in the full factorial design included: (1) encapsulant filler level, (2) encapsulant elastomer type, (3) encapsulant elastomer level, (4) board thickness, and (5) cure schedule. The material variables (1-3) gave rise to 8 formulations with widely varying properties, such as CTE and modulus. Air to air thermal cycling (-55/spl deg/C to +125/spl deg/C) was performed on MCM-L test boards with encapsulated 7.62 mm/spl times/19.05 mm (300 mil/spl times/750 mil) die. Parts were tested in situ throughout the cycling up to 2000 cycles. Results of the designed experiment indicated that filler level was the dominant variable, with high filler level providing the most reliability. Several other variables perhaps had minor effects. Continuing work is examining filler content, elastomer content, and dispensability further.<>
封装剂、模具和衬底之间的热膨胀不匹配会导致应力，从而导致电子部件的热循环失效。随着模具尺寸的增加，这些应力变得特别麻烦。为了尽量减少故障，需要使用低应力密封剂。本文介绍了一种低应力硅碳液体封装剂的研制。在大芯片的多芯片模块(MCM-L)上进行开发。为研制低应力密封胶，进行了设计试验。全因子设计中的变量包括:(1)密封剂填充水平，(2)密封剂弹性体类型，(3)密封剂弹性体水平，(4)板厚度，(5)固化时间表。材料变量(1-3)产生了8种具有广泛不同性能的配方，如CTE和模量。在MCM-L测试板上进行空气对空气热循环(-55/spl℃至+125/spl℃)，该测试板采用封装的7.62 mm/spl倍/19.05 mm (300 mil/spl倍/750 mil)模具。零件在整个循环过程中进行了多达2000次的原位测试。设计试验结果表明，填料水平是主导变量，填料水平越高，可靠性越高。其他几个变量可能有轻微的影响。继续进行的工作是进一步检查填料含量、弹性体含量和可有可无。
{"title":"Development of a low stress silicon-carbon liquid encapsulant","authors":"D. L. Robinson, R. Brady, I. M. Higgins","doi":"10.1109/ECTC.1993.346762","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346762","url":null,"abstract":"Mismatches in thermal expansion between encapsulant, die and substrate lead to stresses that can cause failures in thermal cycling of electronic parts. These stresses become especially troublesome as die size increases. In order to minimize failures, low stress encapsulants are needed. This paper describes development of a low stress silicon-carbon liquid encapsulant. Development was done on multichip modules (MCM-L) with large die. In order to develop a low stress encapsulant, a designed experiment was run. Variables in the full factorial design included: (1) encapsulant filler level, (2) encapsulant elastomer type, (3) encapsulant elastomer level, (4) board thickness, and (5) cure schedule. The material variables (1-3) gave rise to 8 formulations with widely varying properties, such as CTE and modulus. Air to air thermal cycling (-55/spl deg/C to +125/spl deg/C) was performed on MCM-L test boards with encapsulated 7.62 mm/spl times/19.05 mm (300 mil/spl times/750 mil) die. Parts were tested in situ throughout the cycling up to 2000 cycles. Results of the designed experiment indicated that filler level was the dominant variable, with high filler level providing the most reliability. Several other variables perhaps had minor effects. Continuing work is examining filler content, elastomer content, and dispensability further.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133232640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-06-01DOI: 10.1109/ECTC.1993.346832
H. Shaukatullah, M. Gaynes, L.H. White
Surface mount plastic packages are a cost effective way to package integrated circuit chips. However, plastics have poor thermal conductivity and therefore, plastic packages are not suitable for packaging high powered chips. Recently several variations of surface mount plastic packages have been developed for improving the thermal performance. These various techniques for improving the thermal performance can be broadly classified into two categories: internal enhancement of the package and external enhancement. For internal enhancement, high conductivity materials are used to improve heat spreading within the package. Examples of such enhancement include plastic packages with molded and exposed heat spreaders, packages made from metals like aluminium, and ceramic packages. For external enhancement, the thermal performance is improved by attaching a suitable heat sink to the package. This paper discusses the thermal performance of the various surface mount packages with and without heat sinks. It is shown that with a suitable heat sink, the thermal performance of a plastic package is similar to that of a metal or a plastic package with exposed heat spreader. In terms of cost, heat sink attachment offers the most cost effective way of improving the thermal performance of the plastic package, provided there is some space available for the heat sink.<>
{"title":"Thermal enhancement of surface mount electronic packages with heat sinks","authors":"H. Shaukatullah, M. Gaynes, L.H. White","doi":"10.1109/ECTC.1993.346832","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346832","url":null,"abstract":"Surface mount plastic packages are a cost effective way to package integrated circuit chips. However, plastics have poor thermal conductivity and therefore, plastic packages are not suitable for packaging high powered chips. Recently several variations of surface mount plastic packages have been developed for improving the thermal performance. These various techniques for improving the thermal performance can be broadly classified into two categories: internal enhancement of the package and external enhancement. For internal enhancement, high conductivity materials are used to improve heat spreading within the package. Examples of such enhancement include plastic packages with molded and exposed heat spreaders, packages made from metals like aluminium, and ceramic packages. For external enhancement, the thermal performance is improved by attaching a suitable heat sink to the package. This paper discusses the thermal performance of the various surface mount packages with and without heat sinks. It is shown that with a suitable heat sink, the thermal performance of a plastic package is similar to that of a metal or a plastic package with exposed heat spreader. In terms of cost, heat sink attachment offers the most cost effective way of improving the thermal performance of the plastic package, provided there is some space available for the heat sink.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133017073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-06-01DOI: 10.1109/ECTC.1993.346808
S. Sasaki, T. Kishimoto, N. Sugiura
This paper describes a trial coaxial surface mounted connector for PGA-type high-speed multichip modules (MCM). An MCM connector is needed to ensure testability and connection reliability of MCMs mounted on a printed circuit board. Our connector consists of a coaxial elements, a common ground housing made of conductive resin, and a ground contact spring plate. It has 68 signal contacts. We investigated the performance of this connector by experiment and simulation. Its insertion force is only about 53 gf per signal pin. The characteristic impedance is from 45.6 /spl Omega/ to 61.4 /spl Omega/. The average resistance between two contacts is 28 m/spl Omega/ with a deviation of less than plus or minus 5 m/spl Omega/. The insertion loss was measured to be -0.4 dB at 1.0 GHz. Crosstalk noise is less than 1.2%. This prototype-connector transmitted pulses of up to 1.2 Gb/s, showing that it is applicable to high-speed MCMs.<>
{"title":"Coaxial SMT module connector for high-speed MCM","authors":"S. Sasaki, T. Kishimoto, N. Sugiura","doi":"10.1109/ECTC.1993.346808","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346808","url":null,"abstract":"This paper describes a trial coaxial surface mounted connector for PGA-type high-speed multichip modules (MCM). An MCM connector is needed to ensure testability and connection reliability of MCMs mounted on a printed circuit board. Our connector consists of a coaxial elements, a common ground housing made of conductive resin, and a ground contact spring plate. It has 68 signal contacts. We investigated the performance of this connector by experiment and simulation. Its insertion force is only about 53 gf per signal pin. The characteristic impedance is from 45.6 /spl Omega/ to 61.4 /spl Omega/. The average resistance between two contacts is 28 m/spl Omega/ with a deviation of less than plus or minus 5 m/spl Omega/. The insertion loss was measured to be -0.4 dB at 1.0 GHz. Crosstalk noise is less than 1.2%. This prototype-connector transmitted pulses of up to 1.2 Gb/s, showing that it is applicable to high-speed MCMs.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"230 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117321275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-06-01DOI: 10.1109/ECTC.1993.346715
V. Patel, W.C. Mak, B. Rice, L. Feinstein
A transient thermal impedance tester design and its general capabilities are presented. Transient temperature measurements on several power IC packages are obtained. Transient responses of the package subjected to repetitive pulses and to a complex transient power pulse are presented. Temperature measurements on a test chip are compared with the solution as obtained from transient thermal finite element analysis. The effects of measurement delay time on junction temperature measurement are discussed.<>
{"title":"Transient thermal impedance tester for power IC packages","authors":"V. Patel, W.C. Mak, B. Rice, L. Feinstein","doi":"10.1109/ECTC.1993.346715","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346715","url":null,"abstract":"A transient thermal impedance tester design and its general capabilities are presented. Transient temperature measurements on several power IC packages are obtained. Transient responses of the package subjected to repetitive pulses and to a complex transient power pulse are presented. Temperature measurements on a test chip are compared with the solution as obtained from transient thermal finite element analysis. The effects of measurement delay time on junction temperature measurement are discussed.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115922862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-06-01DOI: 10.1109/ECTC.1993.346806
R. Pokrzywa, V. Fiacco
This paper describes a high density, controlled impedance flexible interconnect system used between daughter cards and a mother board in a coolant immersed environment. Topics presented include connector design, alignment techniques utilized, uniform contact pressure methods, connector assembly and feasibility/reliability testing performed on the connector.<>
{"title":"A high density pad-on-pad connector utilizing a flexible circuit","authors":"R. Pokrzywa, V. Fiacco","doi":"10.1109/ECTC.1993.346806","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346806","url":null,"abstract":"This paper describes a high density, controlled impedance flexible interconnect system used between daughter cards and a mother board in a coolant immersed environment. Topics presented include connector design, alignment techniques utilized, uniform contact pressure methods, connector assembly and feasibility/reliability testing performed on the connector.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"155 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116364639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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