Hui Ma, Dongfeng Wang, F. Bastani, I. Yen, K. Cooper
Component-based development (CBD) techniques have been widely used to enhance the productivity and reduce the cost for software systems development. However, applying CBD techniques to embedded software development faces additional challenges. For embedded systems, it is crucial to consider the quality of service (QoS) attributes, such as timeliness, memory limitations, output precision, battery constraints. Frequently, multiple components implementing the same functionality with different QoS properties can be used to compose a system. Also, software components may have parameters that can be configured to satisfy different QoS requirements. Composition analysis, which is used to determine the most suitable component selections and parameter settings to best satisfy the system QoS requirement, is very important in embedded software development process. In this paper, we present a model and the methodologies to facilitate composition analysis. We define QoS requirements as constraints and objectives. Composition analysis is performed based on the QoS properties and requirements to find solutions (component selections and parameter settings) that can optimize the QoS objectives while satisfying the QoS constraints. We use a multiobjective concept to model the composition analysis problem and use an evolutionary algorithm to determine the Pareto-optimal solutions efficiently.
{"title":"A model and methodology for composition QoS analysis of embedded systems","authors":"Hui Ma, Dongfeng Wang, F. Bastani, I. Yen, K. Cooper","doi":"10.1109/RTAS.2005.2","DOIUrl":"https://doi.org/10.1109/RTAS.2005.2","url":null,"abstract":"Component-based development (CBD) techniques have been widely used to enhance the productivity and reduce the cost for software systems development. However, applying CBD techniques to embedded software development faces additional challenges. For embedded systems, it is crucial to consider the quality of service (QoS) attributes, such as timeliness, memory limitations, output precision, battery constraints. Frequently, multiple components implementing the same functionality with different QoS properties can be used to compose a system. Also, software components may have parameters that can be configured to satisfy different QoS requirements. Composition analysis, which is used to determine the most suitable component selections and parameter settings to best satisfy the system QoS requirement, is very important in embedded software development process. In this paper, we present a model and the methodologies to facilitate composition analysis. We define QoS requirements as constraints and objectives. Composition analysis is performed based on the QoS properties and requirements to find solutions (component selections and parameter settings) that can optimize the QoS objectives while satisfying the QoS constraints. We use a multiobjective concept to model the composition analysis problem and use an evolutionary algorithm to determine the Pareto-optimal solutions efficiently.","PeriodicalId":291045,"journal":{"name":"11th IEEE Real Time and Embedded Technology and Applications Symposium","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131967664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Modern embedded systems are typically integrated as multiprocessor system on chips, and are often characterized by the complex behaviors and dependencies that system components exhibit. Different events that trigger such systems normally cause different execution demands, depending on their event type as well as on the task they are processed by, leading to complex workload correlations. For example in data processing systems, the size of an events payload data will typically determine its execution demand on most or all system components, leading to highly correlated workloads. Performance analysis of such complex system is often very difficult, and conventional analysis methods have no means to capture the possible existence of workload correlations. This leads to overly pessimistic analysis results, and thus to too expensive system designs with considerable performance reserves. We propose an abstract model to characterize and capture workload correlations present in a system architecture, and we show how the captured additional system information can be incorporated into an existing framework for modular performance analysis of embedded systems. We also present a method to analytically obtain the proposed abstract workload correlation model from a typical system specification. The applicability of our approach and its advantages over conventional performance analysis methods is shown in a detailed case study of a multiprocessor system on chip, where the analysis results obtained with our approach are considerably improved compared to the results obtained with conventional analysis methods.
{"title":"Characterizing workload correlations in multi processor hard real-time systems","authors":"E. Wandeler, L. Thiele","doi":"10.1109/RTAS.2005.13","DOIUrl":"https://doi.org/10.1109/RTAS.2005.13","url":null,"abstract":"Modern embedded systems are typically integrated as multiprocessor system on chips, and are often characterized by the complex behaviors and dependencies that system components exhibit. Different events that trigger such systems normally cause different execution demands, depending on their event type as well as on the task they are processed by, leading to complex workload correlations. For example in data processing systems, the size of an events payload data will typically determine its execution demand on most or all system components, leading to highly correlated workloads. Performance analysis of such complex system is often very difficult, and conventional analysis methods have no means to capture the possible existence of workload correlations. This leads to overly pessimistic analysis results, and thus to too expensive system designs with considerable performance reserves. We propose an abstract model to characterize and capture workload correlations present in a system architecture, and we show how the captured additional system information can be incorporated into an existing framework for modular performance analysis of embedded systems. We also present a method to analytically obtain the proposed abstract workload correlation model from a typical system specification. The applicability of our approach and its advantages over conventional performance analysis methods is shown in a detailed case study of a multiprocessor system on chip, where the analysis results obtained with our approach are considerably improved compared to the results obtained with conventional analysis methods.","PeriodicalId":291045,"journal":{"name":"11th IEEE Real Time and Embedded Technology and Applications Symposium","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132169410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Haifeng Zhu, J. Lehoczky, Jeffery P. Hansen, R. Rajkumar
Many existing and emerging network applications such as voice-over-IP, videoconferencing and online gaming have end-to-end timing requirements. Despite the real-time demands of these applications, they are usually deployed on best-effort networks such as the Internet. This results in unpredictable and often unsatisfactory performance. In this paper we propose a simple and novel task (or packet) scheduling algorithm Diff-EDF (differentiated earliest deadline first) which can meet the real-time needs of these applications while continuing to provide best effort service to nonreal time traffic. In our system we consider each flow as having stochastic traffic characteristics, a stochastic deadline and a maximum allowable miss rate. The Diff-EDF service meets the flow miss rate requirements through the combination of an admission control test and a scheduling algorithm similar to EDF (earliest deadline first). However, unlike standard EDF scheduling each flow receives a deadline bias based on the flow's miss rate requirement. Applying this bias allows the miss rate to be controlled on a flow-by-flow basis. Both the admission control test and the bias selection algorithms can be computed as a linear function of the flow traffic parameters and the logarithms of the miss rate requirements resulting in an efficient implementation. In this paper, we presented the proposed system structure, protocols, algorithms, analysis and experiments. Experiments with randomly generated and real-life data closely match values predicted by the theory.
{"title":"Diff-EDF: a simple mechanism for differentiated EDF service","authors":"Haifeng Zhu, J. Lehoczky, Jeffery P. Hansen, R. Rajkumar","doi":"10.1109/RTAS.2005.18","DOIUrl":"https://doi.org/10.1109/RTAS.2005.18","url":null,"abstract":"Many existing and emerging network applications such as voice-over-IP, videoconferencing and online gaming have end-to-end timing requirements. Despite the real-time demands of these applications, they are usually deployed on best-effort networks such as the Internet. This results in unpredictable and often unsatisfactory performance. In this paper we propose a simple and novel task (or packet) scheduling algorithm Diff-EDF (differentiated earliest deadline first) which can meet the real-time needs of these applications while continuing to provide best effort service to nonreal time traffic. In our system we consider each flow as having stochastic traffic characteristics, a stochastic deadline and a maximum allowable miss rate. The Diff-EDF service meets the flow miss rate requirements through the combination of an admission control test and a scheduling algorithm similar to EDF (earliest deadline first). However, unlike standard EDF scheduling each flow receives a deadline bias based on the flow's miss rate requirement. Applying this bias allows the miss rate to be controlled on a flow-by-flow basis. Both the admission control test and the bias selection algorithms can be computed as a linear function of the flow traffic parameters and the logarithms of the miss rate requirements resulting in an efficient implementation. In this paper, we presented the proposed system structure, protocols, algorithms, analysis and experiments. Experiments with randomly generated and real-life data closely match values predicted by the theory.","PeriodicalId":291045,"journal":{"name":"11th IEEE Real Time and Embedded Technology and Applications Symposium","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114498398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The development of software for complex reactive embedded systems requires automated support for the verification of functional and nonfunctional properties. Currently, a language (or a design methodology) that can provide both at the same time without incurring in excessive inefficiencies is not available and separation of concerns is the solution advocated by many. Most research and commercial languages and tools focus on providing support for the design and validation of functional properties. At a different level, models and theory have been developed for supporting the description of the threads and resources composing the software architecture, and schedulability analysis provides support for the validation of timing constraints. However, the design of the concurrent structure of the application is still done manually. The system designer has to decide the number of threads, their structure and interactions, without the possibility of evaluating the trade-off between different solutions. This paper presents a solution towards what we believe to be a key objective, that is the synthesis of the architecture-level design and the automated logical-to-architectural mapping. Our proposal tries to reduce the overheads and excessive priority inversions of existing solutions that map all functional blocks (or reactions) into a single thread or assign a thread of execution to each action or possibly to each active object. After presenting our algorithm, we compare it with existing solutions and provide a schedulability analysis of the resulting system.
{"title":"From functional blocks to the synthesis of the architectural model in embedded real-time applications","authors":"Cesare Bartolini, G. Lipari, M. Natale","doi":"10.1109/RTAS.2005.24","DOIUrl":"https://doi.org/10.1109/RTAS.2005.24","url":null,"abstract":"The development of software for complex reactive embedded systems requires automated support for the verification of functional and nonfunctional properties. Currently, a language (or a design methodology) that can provide both at the same time without incurring in excessive inefficiencies is not available and separation of concerns is the solution advocated by many. Most research and commercial languages and tools focus on providing support for the design and validation of functional properties. At a different level, models and theory have been developed for supporting the description of the threads and resources composing the software architecture, and schedulability analysis provides support for the validation of timing constraints. However, the design of the concurrent structure of the application is still done manually. The system designer has to decide the number of threads, their structure and interactions, without the possibility of evaluating the trade-off between different solutions. This paper presents a solution towards what we believe to be a key objective, that is the synthesis of the architecture-level design and the automated logical-to-architectural mapping. Our proposal tries to reduce the overheads and excessive priority inversions of existing solutions that map all functional blocks (or reactions) into a single thread or assign a thread of execution to each action or possibly to each active object. After presenting our algorithm, we compare it with existing solutions and provide a schedulability analysis of the resulting system.","PeriodicalId":291045,"journal":{"name":"11th IEEE Real Time and Embedded Technology and Applications Symposium","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131454137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper we address the problem of schedulability analysis of distributed real-time transactions under EDF, where each transaction is a chain of precedence constrained tasks. We propose a new efficient methodology and a set of algorithms that explicitly take into account the offsets of the transactions. We show, with an extensive set of simulations, that our methodology provides improved schedulability conditions with respect to existing algorithms. Finally, we apply the methodology to an important class of systems: heterogeneous multiprocessor systems, with a general purpose processor and one or more coprocessors (DSPs).
{"title":"Improved schedulability analysis of real-time transactions with earliest deadline scheduling","authors":"R. Pellizzoni, G. Lipari","doi":"10.1109/RTAS.2005.28","DOIUrl":"https://doi.org/10.1109/RTAS.2005.28","url":null,"abstract":"In this paper we address the problem of schedulability analysis of distributed real-time transactions under EDF, where each transaction is a chain of precedence constrained tasks. We propose a new efficient methodology and a set of algorithms that explicitly take into account the offsets of the transactions. We show, with an extensive set of simulations, that our methodology provides improved schedulability conditions with respect to existing algorithms. Finally, we apply the methodology to an important class of systems: heterogeneous multiprocessor systems, with a general purpose processor and one or more coprocessors (DSPs).","PeriodicalId":291045,"journal":{"name":"11th IEEE Real Time and Embedded Technology and Applications Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129978894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The increasing use of electronics in transport systems, such as the automotive and avionic domain, has lead to dramatic improvements with respect to functionality, safety, and cost. However, with this growth of electronics the likelihood of failures due to faults originating from electronic equipment also increases. Although permanent failure rates are constantly diminishing due to improvements in manufacturing, the downsizing of semiconductor features has lead to a significant increase in transient system disturbances. Furthermore, transients are frequently the precursors of upcoming permanent failures. In order to cope with this development, a diagnostic subsystem must especially be designed to detect and analyze such transients to reduce the failure-not-found ratio in today's systems. Therefore, diagnostic detection mechanisms must be devised that refrain from traditional error detection techniques operating only on component-local data in favor of a system-wide view to detect and analyze correlated failures and infer the corresponding fault. In this work, we present out-of-norm assertions (ONAs) as a diagnostic mechanism operating on the distributed state to detect correlated component malfunction. ONAs take the characteristics of faults in the time, value and space domain into account in order to discriminate between different types of faults that are affecting the operation of the distributed system. Since ONAs are specified on the interface state mutual error detection of interface state variables is performed. In contrast to bivalent assertions that need to indisputably decide on correct or incorrect system states at the time of occurrence, the proposed ONAs are also useful in the detection of system irregularities that cannot be forced into the predominant bivalent assessment scheme.
随着电子设备在运输系统（如汽车和航空领域）中的使用日益增多，其功能、安全性和成本都有了显著提高。然而，随着电子技术的发展，电子设备故障导致故障的可能性也在增加。虽然由于制造工艺的改进，永久故障率在不断降低，但半导体功能的小型化导致瞬态系统干扰显著增加。此外，瞬态干扰往往是即将发生的永久性故障的前兆。为了应对这种发展，必须特别设计一个诊断子系统来检测和分析这种瞬态干扰，以降低当今系统中未发现故障的比率。因此，诊断检测机制的设计必须摒弃仅针对组件本地数据的传统错误检测技术，转而从整个系统的角度来检测和分析相关故障，并推断出相应的故障。在这项工作中，我们提出了异常断言（ONA）作为一种诊断机制，在分布式状态下运行，以检测相关的组件故障。ONA 将故障在时域、值域和空间域的特征考虑在内，以便区分影响分布式系统运行的不同类型故障。由于 ONA 是在接口状态上指定的，因此要对接口状态变量进行相互错误检测。二价断言需要在发生时无可争议地判定系统状态的正确与否，与此不同的是，所提出的 ONA 还可用于检测无法强制纳入主流二价评估方案的系统异常。
{"title":"Out-of-norm assertions [diagnostic mechanism]","authors":"P. Peti, R. Obermaisser, H. Kopetz","doi":"10.1109/RTAS.2005.38","DOIUrl":"https://doi.org/10.1109/RTAS.2005.38","url":null,"abstract":"The increasing use of electronics in transport systems, such as the automotive and avionic domain, has lead to dramatic improvements with respect to functionality, safety, and cost. However, with this growth of electronics the likelihood of failures due to faults originating from electronic equipment also increases. Although permanent failure rates are constantly diminishing due to improvements in manufacturing, the downsizing of semiconductor features has lead to a significant increase in transient system disturbances. Furthermore, transients are frequently the precursors of upcoming permanent failures. In order to cope with this development, a diagnostic subsystem must especially be designed to detect and analyze such transients to reduce the failure-not-found ratio in today's systems. Therefore, diagnostic detection mechanisms must be devised that refrain from traditional error detection techniques operating only on component-local data in favor of a system-wide view to detect and analyze correlated failures and infer the corresponding fault. In this work, we present out-of-norm assertions (ONAs) as a diagnostic mechanism operating on the distributed state to detect correlated component malfunction. ONAs take the characteristics of faults in the time, value and space domain into account in order to discriminate between different types of faults that are affecting the operation of the distributed system. Since ONAs are specified on the interface state mutual error detection of interface state variables is performed. In contrast to bivalent assertions that need to indisputably decide on correct or incorrect system states at the time of occurrence, the proposed ONAs are also useful in the detection of system irregularities that cannot be forced into the predominant bivalent assessment scheme.","PeriodicalId":291045,"journal":{"name":"11th IEEE Real Time and Embedded Technology and Applications Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131197877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper addresses the problem of operating parameter assignment to multiple real-time tasks in a phased array radar system. The objective is to maximize the resulting system utility while ensuring the schedulability of all tasks with the assigned operating parameters. For this, we propose a novel framework by integrating the existing resource management framework called QRAM (QoS-based resource allocation model) with the notion of schedulability envelope. The schedulability envelope designed offline hides the complex details of phased array antenna scheduling and provides a linear formula as its quantitative abstraction. This abstraction allows QRAM to find the optimal resource assignment without concerning the details of complex scheduling. Our experimental results show that the proposed framework can achieve significantly improved system utility compared to the existing techniques.
{"title":"A novel framework for quality-aware resource management in phased array radar systems","authors":"Chang-Gun Lee","doi":"10.1109/RTAS.2005.3","DOIUrl":"https://doi.org/10.1109/RTAS.2005.3","url":null,"abstract":"This paper addresses the problem of operating parameter assignment to multiple real-time tasks in a phased array radar system. The objective is to maximize the resulting system utility while ensuring the schedulability of all tasks with the assigned operating parameters. For this, we propose a novel framework by integrating the existing resource management framework called QRAM (QoS-based resource allocation model) with the notion of schedulability envelope. The schedulability envelope designed offline hides the complex details of phased array antenna scheduling and provides a linear formula as its quantitative abstraction. This abstraction allows QRAM to find the optimal resource assignment without concerning the details of complex scheduling. Our experimental results show that the proposed framework can achieve significantly improved system utility compared to the existing techniques.","PeriodicalId":291045,"journal":{"name":"11th IEEE Real Time and Embedded Technology and Applications Symposium","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130039455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
X. Koutsoukos, Radhika Tekumalla, B. Natarajan, Chenyang Lu
Feedback control real-time scheduling (FCS) aims at satisfying performance specifications of real-time systems based on adaptive resource management. Existing FCS algorithms often rely on the existence of continuous control variables in real-time systems. A number of real-time systems, however, support only a finite set of discrete configurations that limit the adaptation mechanisms. This paper presents hybrid supervisory utilization control (HySUCON) for scheduling such real-time systems. HySUCON enforces processor utilization bounds by managing the switchings between the discrete configurations. Our approach is based on a best-first-search algorithm that is invoked only if reconfiguration is necessary. Theoretical analysis and simulations demonstrate that the approach leads to robust utilization bounds for varying execution times. Experimental results demonstrate the algorithm performance for a representative application scenario.
{"title":"Hybrid supervisory utilization control of real-time systems","authors":"X. Koutsoukos, Radhika Tekumalla, B. Natarajan, Chenyang Lu","doi":"10.1109/RTAS.2005.26","DOIUrl":"https://doi.org/10.1109/RTAS.2005.26","url":null,"abstract":"Feedback control real-time scheduling (FCS) aims at satisfying performance specifications of real-time systems based on adaptive resource management. Existing FCS algorithms often rely on the existence of continuous control variables in real-time systems. A number of real-time systems, however, support only a finite set of discrete configurations that limit the adaptation mechanisms. This paper presents hybrid supervisory utilization control (HySUCON) for scheduling such real-time systems. HySUCON enforces processor utilization bounds by managing the switchings between the discrete configurations. Our approach is based on a best-first-search algorithm that is invoked only if reconfiguration is necessary. Theoretical analysis and simulations demonstrate that the approach leads to robust utilization bounds for varying execution times. Experimental results demonstrate the algorithm performance for a representative application scenario.","PeriodicalId":291045,"journal":{"name":"11th IEEE Real Time and Embedded Technology and Applications Symposium","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114414579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With processor speed doubling every 18 months, more and more system functionalities are implemented as software (SW) in the design process of embedded systems. Selecting the "right" RTOS before the SW is developed is very important. In this paper, we present an RTOS modeling tool based on SystemC. It is configurable to support modeling and timed simulation of most popular embedded RTOSs. Timing fidelity is achieved by using delay annotation. The OS timing information is derived from published benchmark data. Experiments show that the accuracy of our approach is able to help designers gain confidence in their RTOS selection. By avoiding using an instruction set simulator, the simulation can be speeded up by more than 3 orders of magnitude. Any other component integrable with SystemC can also be integrated in our simulation environment.
{"title":"Timed RTOS modeling for embedded system design","authors":"Zhengting He, A. Mok, Cheng Peng","doi":"10.1109/RTAS.2005.52","DOIUrl":"https://doi.org/10.1109/RTAS.2005.52","url":null,"abstract":"With processor speed doubling every 18 months, more and more system functionalities are implemented as software (SW) in the design process of embedded systems. Selecting the \"right\" RTOS before the SW is developed is very important. In this paper, we present an RTOS modeling tool based on SystemC. It is configurable to support modeling and timed simulation of most popular embedded RTOSs. Timing fidelity is achieved by using delay annotation. The OS timing information is derived from published benchmark data. Experiments show that the accuracy of our approach is able to help designers gain confidence in their RTOS selection. By avoiding using an instruction set simulator, the simulation can be speeded up by more than 3 orders of magnitude. Any other component integrable with SystemC can also be integrated in our simulation environment.","PeriodicalId":291045,"journal":{"name":"11th IEEE Real Time and Embedded Technology and Applications Symposium","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133817997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The increasing popularity of high-volume performance-critical Internet applications is a challenge for servers to provide individual response-time guarantees. Considering the fact that most Internet applications can tolerate a small percentage of deadline misses, we define delay constraint as a statistical guarantee to relax server resource requirements. A recent decay function model characterizes the relationship between the request delay constraint, deadline misses, and server capacity in a transfer function based filter system. A time-invariant scheduler was proposed to minimize system load variances in support of requests with the same delay constraints. This paper extends the model to support requests with different deadlines and describes an optimal time-variant scheduling policy that minimizes load variances and capacity requirement. The resultant capacity bound is further tightened by utilizing the information of request arrival distribution. Simulation results validate the extended decay function model and show the superiority of the scheduler in comparison with other scheduling algorithms.
{"title":"Optimal time-variant resource allocation for Internet servers with delay constraints","authors":"Xiliang Zhong, Chengzhong Xu, Minghua Xu, Jianbin Wei","doi":"10.1109/RTAS.2005.37","DOIUrl":"https://doi.org/10.1109/RTAS.2005.37","url":null,"abstract":"The increasing popularity of high-volume performance-critical Internet applications is a challenge for servers to provide individual response-time guarantees. Considering the fact that most Internet applications can tolerate a small percentage of deadline misses, we define delay constraint as a statistical guarantee to relax server resource requirements. A recent decay function model characterizes the relationship between the request delay constraint, deadline misses, and server capacity in a transfer function based filter system. A time-invariant scheduler was proposed to minimize system load variances in support of requests with the same delay constraints. This paper extends the model to support requests with different deadlines and describes an optimal time-variant scheduling policy that minimizes load variances and capacity requirement. The resultant capacity bound is further tightened by utilizing the information of request arrival distribution. Simulation results validate the extended decay function model and show the superiority of the scheduler in comparison with other scheduling algorithms.","PeriodicalId":291045,"journal":{"name":"11th IEEE Real Time and Embedded Technology and Applications Symposium","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123520384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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