Conventionally, a real-time operating system (RTOS) is built without knowing which specific applications is executed upon it. The RTOS is built for the general case, rather than to meet the specific requirements of an application. This paper proposes a generic module-based reflective framework to implement an RTOS that allows applications to dynamically adapt the policies within the RTOS to better meet application-specific requirements. The specific approach taken is to augment a conventional /spl mu/-kernel with a module-based reflective mechanism that allows applications to dynamically change the behaviour of themselves, and the policies of the underlying RTOS. Reflection is used to allow applications and system modules to access key OS data structures to obtain information pertaining to the current system performance and resource management policies (e.g. scheduling). An application is then able to modify or introduce new policies into the RTOS to satisfy its demands. Evaluation of our approach shows a considerable performance gain.
{"title":"Implementing application specific RTOS policies using reflection","authors":"A. Patil, N. Audsley","doi":"10.1109/RTAS.2005.27","DOIUrl":"https://doi.org/10.1109/RTAS.2005.27","url":null,"abstract":"Conventionally, a real-time operating system (RTOS) is built without knowing which specific applications is executed upon it. The RTOS is built for the general case, rather than to meet the specific requirements of an application. This paper proposes a generic module-based reflective framework to implement an RTOS that allows applications to dynamically adapt the policies within the RTOS to better meet application-specific requirements. The specific approach taken is to augment a conventional /spl mu/-kernel with a module-based reflective mechanism that allows applications to dynamically change the behaviour of themselves, and the policies of the underlying RTOS. Reflection is used to allow applications and system modules to access key OS data structures to obtain information pertaining to the current system performance and resource management policies (e.g. scheduling). An application is then able to modify or introduce new policies into the RTOS to satisfy its demands. Evaluation of our approach shows a considerable performance gain.","PeriodicalId":291045,"journal":{"name":"11th IEEE Real Time and Embedded Technology and Applications Symposium","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127670220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sibin Mohan, F. Mueller, D. Whalley, Christopher A. Healy
Low-end embedded architectures, such as sensor nodes, have become popular in diverse fields, many of which impose real-time constraints. Currently, the Atmel Atmega processor family used by Berkeley Motes lacks support for deriving safe bounds on the WCET, which is a prerequisite for performing real-time schedulability analysis. Our work fills this gap by providing an analytical method to obtain WCET bounds for this processor architecture. Our first contribution is to analyze both C and NesC code, the latter of which is unprecedented. The second contribution is to model control hazards and variable-cycle instructions, both handled more efficiently by our approach than by previous ones and results in up to 77% improvement in bounding the WCET. The results demonstrate that our timing analysis framework is able to tightly and safely estimate the WCET of the benchmarks while simulator results are shown to not always provide safe WCET bounds. While motivated by the Atmel Atmega series of processors, results are equally applicable to low-end embedded processors. This work is, to the best of our knowledge, the first set of experiments where timing results are contrasted from execution on an actual processor, from a cycle-accurate simulator and from a static timing analyzer. Furthermore, making our timing analysis toolset available to the Atmel Atmega processor family is a significant contribution towards addressing a documented need for tool support for sensor node architectures commonly used in networked systems of embedded computers, or so-called EmNets.
{"title":"Timing analysis for sensor network nodes of the Atmega processor family","authors":"Sibin Mohan, F. Mueller, D. Whalley, Christopher A. Healy","doi":"10.1109/RTAS.2005.53","DOIUrl":"https://doi.org/10.1109/RTAS.2005.53","url":null,"abstract":"Low-end embedded architectures, such as sensor nodes, have become popular in diverse fields, many of which impose real-time constraints. Currently, the Atmel Atmega processor family used by Berkeley Motes lacks support for deriving safe bounds on the WCET, which is a prerequisite for performing real-time schedulability analysis. Our work fills this gap by providing an analytical method to obtain WCET bounds for this processor architecture. Our first contribution is to analyze both C and NesC code, the latter of which is unprecedented. The second contribution is to model control hazards and variable-cycle instructions, both handled more efficiently by our approach than by previous ones and results in up to 77% improvement in bounding the WCET. The results demonstrate that our timing analysis framework is able to tightly and safely estimate the WCET of the benchmarks while simulator results are shown to not always provide safe WCET bounds. While motivated by the Atmel Atmega series of processors, results are equally applicable to low-end embedded processors. This work is, to the best of our knowledge, the first set of experiments where timing results are contrasted from execution on an actual processor, from a cycle-accurate simulator and from a static timing analyzer. Furthermore, making our timing analysis toolset available to the Atmel Atmega processor family is a significant contribution towards addressing a documented need for tool support for sensor node architectures commonly used in networked systems of embedded computers, or so-called EmNets.","PeriodicalId":291045,"journal":{"name":"11th IEEE Real Time and Embedded Technology and Applications Symposium","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133799926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Orlando Moreira, J. Mol, M. Bekooij, J. V. Meerbergen
An embedded multiprocessor that can run multiple hard-real-time (HRT) jobs simultaneously has to guarantee that enough resources are available to meet the timing constraints. It is essential that both application model and hardware be tailored to this goal. Moreover, suitable resource allocation and scheduling are needed. This paper proposes a resource allocator that gives guarantees for HRT streaming applications. Because new jobs arrive during operation, resource allocation is performed at run-time. This provides admission control. Resource budget enforcement is handled by local schedulers. We formalize our resource allocation problem and show that it is NP-complete. We developed heuristics to tackle the problem during runtime and evaluated them. A modified First-fit Vector Bin-Packing algorithm provides a good solution; it can allocate 95% of the resources, while handling a large number of job arrivals and departures on a heavily loaded system.
{"title":"Multiprocessor resource allocation for hard-real-time streaming with a dynamic job-mix","authors":"Orlando Moreira, J. Mol, M. Bekooij, J. V. Meerbergen","doi":"10.1109/RTAS.2005.33","DOIUrl":"https://doi.org/10.1109/RTAS.2005.33","url":null,"abstract":"An embedded multiprocessor that can run multiple hard-real-time (HRT) jobs simultaneously has to guarantee that enough resources are available to meet the timing constraints. It is essential that both application model and hardware be tailored to this goal. Moreover, suitable resource allocation and scheduling are needed. This paper proposes a resource allocator that gives guarantees for HRT streaming applications. Because new jobs arrive during operation, resource allocation is performed at run-time. This provides admission control. Resource budget enforcement is handled by local schedulers. We formalize our resource allocation problem and show that it is NP-complete. We developed heuristics to tackle the problem during runtime and evaluated them. A modified First-fit Vector Bin-Packing algorithm provides a good solution; it can allocate 95% of the resources, while handling a large number of job arrivals and departures on a heavily loaded system.","PeriodicalId":291045,"journal":{"name":"11th IEEE Real Time and Embedded Technology and Applications Symposium","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133422013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yi-Neng Lin, Chiuan-Hung Lin, Ying-Dar Lin, Y. Lai
Networking applications, such as VPN and content filtering, demand extra computing power in order to meet the throughput requirement nowadays. In addition to pure ASIC solutions, network processor architecture is emerging as an alternative to scale up data-plane processing while retaining design flexibility. This article, rather than proposing new algorithms, illustrates the experience in developing IPSec-based VPN gateways over network processors, and investigates the performance issues. The external benchmarks reveal that the system can reach 45 Mbps for IPSec using 3DES algorithm, which improves by 350% compared to single XScale core processor and parallels the throughput of a PIII 1 GHz processor. Through the internal benchmarks, we analyze the turnaround times of the main functional blocks, and identify the core processor as the performance bottleneck for both packet forwarding and IPSec processing.
{"title":"VPN gateways over network processors: implementation and evaluation","authors":"Yi-Neng Lin, Chiuan-Hung Lin, Ying-Dar Lin, Y. Lai","doi":"10.1109/RTAS.2005.58","DOIUrl":"https://doi.org/10.1109/RTAS.2005.58","url":null,"abstract":"Networking applications, such as VPN and content filtering, demand extra computing power in order to meet the throughput requirement nowadays. In addition to pure ASIC solutions, network processor architecture is emerging as an alternative to scale up data-plane processing while retaining design flexibility. This article, rather than proposing new algorithms, illustrates the experience in developing IPSec-based VPN gateways over network processors, and investigates the performance issues. The external benchmarks reveal that the system can reach 45 Mbps for IPSec using 3DES algorithm, which improves by 350% compared to single XScale core processor and parallels the throughput of a PIII 1 GHz processor. Through the internal benchmarks, we analyze the turnaround times of the main functional blocks, and identify the core processor as the performance bottleneck for both packet forwarding and IPSec processing.","PeriodicalId":291045,"journal":{"name":"11th IEEE Real Time and Embedded Technology and Applications Symposium","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114412544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Convoy driving on public highways is a useful phenomena which increases the safety and the throughput of the highway. We present an approach through which a wireless Convoy Driving Device assists the driver in the task of deciding to join or leave a convoy, influencing the speed and formation of the convoy. Our approach handles complex situations like the merging and splitting of convoys, and it offers valuable lessons with applications for other cases of teamwork of mobile entities.
{"title":"Convoy driving through ad-hoc coalition formation","authors":"M. Khan, Ladislau Bölöni","doi":"10.1109/RTAS.2005.15","DOIUrl":"https://doi.org/10.1109/RTAS.2005.15","url":null,"abstract":"Convoy driving on public highways is a useful phenomena which increases the safety and the throughput of the highway. We present an approach through which a wireless Convoy Driving Device assists the driver in the task of deciding to join or leave a convoy, influencing the speed and formation of the convoy. Our approach handles complex situations like the merging and splitting of convoys, and it offers valuable lessons with applications for other cases of teamwork of mobile entities.","PeriodicalId":291045,"journal":{"name":"11th IEEE Real Time and Embedded Technology and Applications Symposium","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129917165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Wankang Zhao, William C. Kreahling, D. Whalley, Christopher A. Healy, F. Mueller
It is advantageous to perform compiler optimizations to lower the WCET of a task since tasks with lower WCETs are easier to schedule and more likely to meet their deadlines. Compiler writers in recent years have used profile information to detect the frequently executed paths in a program and there has been much effort to develop compiler optimizations to improve these paths in order to reduce average-case execution time. In this paper we describe our approach to reduce WCET by adapting and applying optimizations designed for frequent paths to the worst-case paths in an application. Our compiler uses feedback from our timing analyzer to detect the WCET paths through a function that will be subject to aggressive optimizations, reflect subsequent effects on the WCET of the paths due to these optimizations, and to also ensure that the worst-case path optimizations actually improve the WCET before committing to a code size increase. We evaluate a number of WC path optimizations and present results showing the decrease in WCET versus the increase in code size.
{"title":"Improving WCET by optimizing worst-case paths","authors":"Wankang Zhao, William C. Kreahling, D. Whalley, Christopher A. Healy, F. Mueller","doi":"10.1109/RTAS.2005.29","DOIUrl":"https://doi.org/10.1109/RTAS.2005.29","url":null,"abstract":"It is advantageous to perform compiler optimizations to lower the WCET of a task since tasks with lower WCETs are easier to schedule and more likely to meet their deadlines. Compiler writers in recent years have used profile information to detect the frequently executed paths in a program and there has been much effort to develop compiler optimizations to improve these paths in order to reduce average-case execution time. In this paper we describe our approach to reduce WCET by adapting and applying optimizations designed for frequent paths to the worst-case paths in an application. Our compiler uses feedback from our timing analyzer to detect the WCET paths through a function that will be subject to aggressive optimizations, reflect subsequent effects on the WCET of the paths due to these optimizations, and to also ensure that the worst-case path optimizations actually improve the WCET before committing to a code size increase. We evaluate a number of WC path optimizations and present results showing the decrease in WCET versus the increase in code size.","PeriodicalId":291045,"journal":{"name":"11th IEEE Real Time and Embedded Technology and Applications Symposium","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126715076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we propose a new technique, called a delayed locking technique, to improve the real-time performance of embedded Linux. The proposed technique employs the rule that entering a critical section is allowed only if the operation does not disturb the future execution of the real-time application. To execute this rule, we introduce the concepts of timer interrupt prediction and lock hold time acquisition. In addition, we designed and implemented a new high-resolution timer that is simple, yet efficient. We implemented the prototype on Linux 2.4.18. Experimental results show that the worst-case OS latency of real-time process is reduced to 23% of the original one, at the expense of slowdown of the nonreal-time process by 20%. Though we focus only on embedded Linux, our technique is useful for all kinds of real-time operating systems in which the critical section is significantly long.
{"title":"Delayed locking technique for improving real-time performance of embedded Linux by prediction of timer interrupt","authors":"Jupyung Lee, K. Park","doi":"10.1109/RTAS.2005.16","DOIUrl":"https://doi.org/10.1109/RTAS.2005.16","url":null,"abstract":"In this paper, we propose a new technique, called a delayed locking technique, to improve the real-time performance of embedded Linux. The proposed technique employs the rule that entering a critical section is allowed only if the operation does not disturb the future execution of the real-time application. To execute this rule, we introduce the concepts of timer interrupt prediction and lock hold time acquisition. In addition, we designed and implemented a new high-resolution timer that is simple, yet efficient. We implemented the prototype on Linux 2.4.18. Experimental results show that the worst-case OS latency of real-time process is reduced to 23% of the original one, at the expense of slowdown of the nonreal-time process by 20%. Though we focus only on embedded Linux, our technique is useful for all kinds of real-time operating systems in which the critical section is significantly long.","PeriodicalId":291045,"journal":{"name":"11th IEEE Real Time and Embedded Technology and Applications Symposium","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121524806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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