While caches have become invaluable for higher-end architectures due to their ability to hide, in part, the gap between processor speed and memory access times, caches (and particularly data caches) limit the timing predictability for data accesses that may reside in memory or in cache. This is a significant problem for real-time systems. The objective our work is to provide accurate predictions of data cache behavior of scalar and nonscalar references whose reference patterns are known at compile time. Such knowledge about cache behavior provides the basis for significant improvements in bounding the worst-case execution time (WCET) of real-time programs, particularly for hard-to-analyze data caches. We exploit the power of the cache miss equations (CME) framework but lift a number of limitations of traditional CME to generalize the analysis to more arbitrary programs. We further devised a transformation, coined "forced" loop fusion, which facilitates the analysis across sequential loops. Our contributions result in exact data cache reference patterns minus; in contrast to approximate cache miss behavior of prior work. Experimental results indicate improvements on the accuracy of worst-case data cache behavior up to two orders of magnitude over the original approach. In fact, our results closely bound and sometimes even exactly match those obtained by trace-driven simulation for worst-case inputs. The resulting WCET bounds of timing analysis confirm these findings in terms of providing tight bounds. Overall, our contributions lift analytical approaches to predict data cache behavior to a level suitable for efficient static timing analysis and, subsequently, real-time schedulability of tasks with predictable WCET.
{"title":"Bounding worst-case data cache behavior by analytically deriving cache reference patterns","authors":"H. Ramaprasad, F. Mueller","doi":"10.1109/RTAS.2005.12","DOIUrl":"https://doi.org/10.1109/RTAS.2005.12","url":null,"abstract":"While caches have become invaluable for higher-end architectures due to their ability to hide, in part, the gap between processor speed and memory access times, caches (and particularly data caches) limit the timing predictability for data accesses that may reside in memory or in cache. This is a significant problem for real-time systems. The objective our work is to provide accurate predictions of data cache behavior of scalar and nonscalar references whose reference patterns are known at compile time. Such knowledge about cache behavior provides the basis for significant improvements in bounding the worst-case execution time (WCET) of real-time programs, particularly for hard-to-analyze data caches. We exploit the power of the cache miss equations (CME) framework but lift a number of limitations of traditional CME to generalize the analysis to more arbitrary programs. We further devised a transformation, coined \"forced\" loop fusion, which facilitates the analysis across sequential loops. Our contributions result in exact data cache reference patterns minus; in contrast to approximate cache miss behavior of prior work. Experimental results indicate improvements on the accuracy of worst-case data cache behavior up to two orders of magnitude over the original approach. In fact, our results closely bound and sometimes even exactly match those obtained by trace-driven simulation for worst-case inputs. The resulting WCET bounds of timing analysis confirm these findings in terms of providing tight bounds. Overall, our contributions lift analytical approaches to predict data cache behavior to a level suitable for efficient static timing analysis and, subsequently, real-time schedulability of tasks with predictable WCET.","PeriodicalId":291045,"journal":{"name":"11th IEEE Real Time and Embedded Technology and Applications Symposium","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125255116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present a new model of real-time periodic distributed asynchronous computation in which information flows through sequences of periodic tasks, where task inputs are obtained by sampling other task's outputs as well as sampling the environment. We introduce a metric for end-to-end timing called the age of an output, which is the time since the external inputs on which an output value is based were sampled. We present some bounds on age scheduling efficiency, reduce the problem of finding a feasible distributed age schedule to finding a solution for a system of nonlinear constraints, and discuss use of a commercial solver to find a solution to a large problem derived from a real-world system.
{"title":"Real-time sampled signal flows through asynchronous distributed systems","authors":"S. Vestal","doi":"10.1109/RTAS.2005.44","DOIUrl":"https://doi.org/10.1109/RTAS.2005.44","url":null,"abstract":"We present a new model of real-time periodic distributed asynchronous computation in which information flows through sequences of periodic tasks, where task inputs are obtained by sampling other task's outputs as well as sampling the environment. We introduce a metric for end-to-end timing called the age of an output, which is the time since the external inputs on which an output value is based were sampled. We present some bounds on age scheduling efficiency, reduce the problem of finding a feasible distributed age schedule to finding a solution for a system of nonlinear constraints, and discuss use of a commercial solver to find a solution to a large problem derived from a real-world system.","PeriodicalId":291045,"journal":{"name":"11th IEEE Real Time and Embedded Technology and Applications Symposium","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128095113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A critical component of a real-time operating system (RTOS) is its process scheduler. While the prior research on process scheduling focuses mostly on meeting hard/soft deadlines, preemption and priory assignment related issues, problems arise from existence of cache memories are largely ignored. Focusing on data accesses and a cache based embedded system, this paper proposes an adaptive locality-conscious process scheduling algorithm. The main goal of the proposed algorithm is to exploit (reuse) the contents of the on-chip cache memory to the highest extent possible. The algorithm tries to achieve its goal by determining the order in which the processes get scheduled such that the successively-executing processes share a large number of data elements. We implemented our scheduler within a customized simulation platform and simulated it using a set of benchmark codes. Our experimental results reveal that the proposed scheduling algorithm is very successful in practice, and reduces process completion times significantly for both rate-monotonic scheduling (RMS) and earliest-deadline-first scheduling (EDF). We also explain how process code transformations can be used for increasing the savings achieved by the locality-conscious scheduler, and show how the proposed approach operates with a base scheduler such as RMS and EDF.
{"title":"An adaptive locality-conscious process scheduler for embedded systems","authors":"Guilin Chen, Guangyu Chen, O. Ozturk, M. Kandemir","doi":"10.1109/RTAS.2005.6","DOIUrl":"https://doi.org/10.1109/RTAS.2005.6","url":null,"abstract":"A critical component of a real-time operating system (RTOS) is its process scheduler. While the prior research on process scheduling focuses mostly on meeting hard/soft deadlines, preemption and priory assignment related issues, problems arise from existence of cache memories are largely ignored. Focusing on data accesses and a cache based embedded system, this paper proposes an adaptive locality-conscious process scheduling algorithm. The main goal of the proposed algorithm is to exploit (reuse) the contents of the on-chip cache memory to the highest extent possible. The algorithm tries to achieve its goal by determining the order in which the processes get scheduled such that the successively-executing processes share a large number of data elements. We implemented our scheduler within a customized simulation platform and simulated it using a set of benchmark codes. Our experimental results reveal that the proposed scheduling algorithm is very successful in practice, and reduces process completion times significantly for both rate-monotonic scheduling (RMS) and earliest-deadline-first scheduling (EDF). We also explain how process code transformations can be used for increasing the savings achieved by the locality-conscious scheduler, and show how the proposed approach operates with a base scheduler such as RMS and EDF.","PeriodicalId":291045,"journal":{"name":"11th IEEE Real Time and Embedded Technology and Applications Symposium","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128462668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Dasarathy, S. Gadgil, R. Vaidyanathan, K. Parmeswaran, B. Coan, M. Conarty, V. Bhanot
We present adaptive network QoS (quality of service) technology that provides ongoing, end-to-end assurance that critical traffic belonging to admitted flows has bounded queuing loss, delay, and jitter. Our technology uses a bandwidth broker to provide admission control, and leverages differentiated services and class of service functionality of high-end routers and switches for enforcement. The technology employs an integrated QoS treatment across a hybrid layer-2/layer-3 network and adapts to changes in mission requirements, work load and configurations; it uses discovery algorithms in these layers to maintain a current view of resource availability. Under the DARPA ARMS (adaptive and reflective middleware systems) program, our technology is being developed, integrated and validated in a CORBA-based multilayer resource management framework.
{"title":"Network QoS assurance in a multi-layer adaptive resource management scheme for mission-critical applications using the CORBA middleware framework","authors":"B. Dasarathy, S. Gadgil, R. Vaidyanathan, K. Parmeswaran, B. Coan, M. Conarty, V. Bhanot","doi":"10.1109/RTAS.2005.34","DOIUrl":"https://doi.org/10.1109/RTAS.2005.34","url":null,"abstract":"We present adaptive network QoS (quality of service) technology that provides ongoing, end-to-end assurance that critical traffic belonging to admitted flows has bounded queuing loss, delay, and jitter. Our technology uses a bandwidth broker to provide admission control, and leverages differentiated services and class of service functionality of high-end routers and switches for enforcement. The technology employs an integrated QoS treatment across a hybrid layer-2/layer-3 network and adapts to changes in mission requirements, work load and configurations; it uses discovery algorithms in these layers to maintain a current view of resource availability. Under the DARPA ARMS (adaptive and reflective middleware systems) program, our technology is being developed, integrated and validated in a CORBA-based multilayer resource management framework.","PeriodicalId":291045,"journal":{"name":"11th IEEE Real Time and Embedded Technology and Applications Symposium","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125091057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
While utilization bound based schedulability test is simple and effective, it is often difficult to derive the bound itself. For its analytical complexity, utilization bound results are usually obtained on a case-by-case basis. In this paper, we develop a general framework that allows one to effectively derive schedulability bounds for a wide range of real-time systems with different workload patterns and schedulers. Our analytical model is capable of describing a wide range of tasks and schedulers' behaviors. We propose a new definition of utilization, called workload rate. While similar to utilization, workload rate enables flexible representation of different scheduling and workload scenarios and leads to uniform derivation of schedulability bounds. We derive a parameterized schedulability bound for static priority schedulers with arbitrary priority assignment. Existing utilization bounds for different priority assignments and task releasing patterns can be derived from our closed-form formula by simple assignments of proper parameters.
{"title":"On schedulability bounds of static priority schedulers","authors":"Jianjia Wu, Jyh-Charn S. Liu, Wei Zhao","doi":"10.1109/RTAS.2005.35","DOIUrl":"https://doi.org/10.1109/RTAS.2005.35","url":null,"abstract":"While utilization bound based schedulability test is simple and effective, it is often difficult to derive the bound itself. For its analytical complexity, utilization bound results are usually obtained on a case-by-case basis. In this paper, we develop a general framework that allows one to effectively derive schedulability bounds for a wide range of real-time systems with different workload patterns and schedulers. Our analytical model is capable of describing a wide range of tasks and schedulers' behaviors. We propose a new definition of utilization, called workload rate. While similar to utilization, workload rate enables flexible representation of different scheduling and workload scenarios and leads to uniform derivation of schedulability bounds. We derive a parameterized schedulability bound for static priority schedulers with arbitrary priority assignment. Existing utilization bounds for different priority assignments and task releasing patterns can be derived from our closed-form formula by simple assignments of proper parameters.","PeriodicalId":291045,"journal":{"name":"11th IEEE Real Time and Embedded Technology and Applications Symposium","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122178151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Control systems running on a computer are subject to timing disturbances coming from implementation constraints. Fortunately closed-loop systems behave robustly w.r.t. modelling errors and disturbances, and the controller design can be performed to explicitly enhance robustness against specific uncertainties. On one hand robustness in process controllers can be used to comply with weakly modelled timing uncertainties. On the other hand the principle of robust closed-loop control can also be applied to the real-time scheduler to provide online adaption of some scheduling parameters, with the objective of controlling the computing resource allocation. The control performance specification may be set according to both control and implementation constraints. The approach is illustrated through several examples using simulation and an experimental feedback scheduler is briefly described.
{"title":"Robust control/scheduling co-design: application to robot control","authors":"D. Simon, D. Robert, O. Sename","doi":"10.1109/RTAS.2005.46","DOIUrl":"https://doi.org/10.1109/RTAS.2005.46","url":null,"abstract":"Control systems running on a computer are subject to timing disturbances coming from implementation constraints. Fortunately closed-loop systems behave robustly w.r.t. modelling errors and disturbances, and the controller design can be performed to explicitly enhance robustness against specific uncertainties. On one hand robustness in process controllers can be used to comply with weakly modelled timing uncertainties. On the other hand the principle of robust closed-loop control can also be applied to the real-time scheduler to provide online adaption of some scheduling parameters, with the objective of controlling the computing resource allocation. The control performance specification may be set according to both control and implementation constraints. The approach is illustrated through several examples using simulation and an experimental feedback scheduler is briefly described.","PeriodicalId":291045,"journal":{"name":"11th IEEE Real Time and Embedded Technology and Applications Symposium","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129341292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Consider a team of robots equipped with sensors that collaborate with one another to achieve a common goal. Sensors on robots produce periodic updates that must be transmitted to other robots and processed in real-time to enable such collaboration. Since the robots communicate with one another over an ad-hoc wireless network, we consider the problem of providing timeliness guarantees for multihop message transmissions in such a network. We derive the effective deadline and the latest start time for per-hop message transmissions from the validity intervals of the sensor data and the constraints imposed by the consuming task at the destination. Our technique schedules messages by carefully exploiting spatial channel reuse for each per-hop transmission to avoid MAC layer collisions, so that deadline misses are minimized. Extensive simulations show the effectiveness of our channel reuse-based SLF (smallest latest-start-time first) technique when compared to a simple per-hop SLF technique, especially at moderate to high channel utilization or when the probability of collisions is high.
{"title":"Scheduling messages with deadlines in multi-hop real-time sensor networks","authors":"Huan Li, P. Shenoy, K. Ramamritham","doi":"10.1109/RTAS.2005.48","DOIUrl":"https://doi.org/10.1109/RTAS.2005.48","url":null,"abstract":"Consider a team of robots equipped with sensors that collaborate with one another to achieve a common goal. Sensors on robots produce periodic updates that must be transmitted to other robots and processed in real-time to enable such collaboration. Since the robots communicate with one another over an ad-hoc wireless network, we consider the problem of providing timeliness guarantees for multihop message transmissions in such a network. We derive the effective deadline and the latest start time for per-hop message transmissions from the validity intervals of the sensor data and the constraints imposed by the consuming task at the destination. Our technique schedules messages by carefully exploiting spatial channel reuse for each per-hop transmission to avoid MAC layer collisions, so that deadline misses are minimized. Extensive simulations show the effectiveness of our channel reuse-based SLF (smallest latest-start-time first) technique when compared to a simple per-hop SLF technique, especially at moderate to high channel utilization or when the probability of collisions is high.","PeriodicalId":291045,"journal":{"name":"11th IEEE Real Time and Embedded Technology and Applications Symposium","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121975401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Tejasvi Aswathanarayana, D. Niehaus, Venkita Subramonian, C. Gill
This paper describes a scheduling abstraction, called group scheduling, that emphasizes fine grain configurability of system scheduling semantics. The group scheduling approach described and evaluated in this paper provides an extremely flexible framework within which a wide range of scheduling semantics can be expressed, including familiar priority and deadline based algorithms. The paper describes both OS and middleware based implementations of the framework, and shows through evaluation that they can produce the same behavior for a nontrivial set of application computations. We also show that the framework can support application-specific scheduling constraints such as progress, to improve performance of applications whose scheduling semantics do not match those of traditional scheduling algorithms.
{"title":"Design and performance of configurable endsystem scheduling mechanisms","authors":"Tejasvi Aswathanarayana, D. Niehaus, Venkita Subramonian, C. Gill","doi":"10.1109/RTAS.2005.17","DOIUrl":"https://doi.org/10.1109/RTAS.2005.17","url":null,"abstract":"This paper describes a scheduling abstraction, called group scheduling, that emphasizes fine grain configurability of system scheduling semantics. The group scheduling approach described and evaluated in this paper provides an extremely flexible framework within which a wide range of scheduling semantics can be expressed, including familiar priority and deadline based algorithms. The paper describes both OS and middleware based implementations of the framework, and shows through evaluation that they can produce the same behavior for a nontrivial set of application computations. We also show that the framework can support application-specific scheduling constraints such as progress, to improve performance of applications whose scheduling semantics do not match those of traditional scheduling algorithms.","PeriodicalId":291045,"journal":{"name":"11th IEEE Real Time and Embedded Technology and Applications Symposium","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130346865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper provides two contributions to R&D on model-driven development (MDD) techniques that help codify the impact of middleware configurations on end-to-end distributed real-time and embedded (DRE) system quality of service (QoS). First, we describe how MDD techniques can help select middleware configuration parameters that satisfy key functional and QoS requirements of DRE systems. Second, we apply our MDD techniques to empirically evaluate the end-to-end QoS of representative DRE systems in the avionics and industrial manufacturing domains. Our results show how MDD techniques significantly enhance conventional ad hoc processes used by developers to configure middleware that meets the QoS needs of DRE systems.
{"title":"Model-driven techniques for evaluating the QoS of middleware configurations for DRE systems","authors":"A. Krishna, E. Turkay, A. Gokhale, D. Schmidt","doi":"10.1109/RTAS.2005.32","DOIUrl":"https://doi.org/10.1109/RTAS.2005.32","url":null,"abstract":"This paper provides two contributions to R&D on model-driven development (MDD) techniques that help codify the impact of middleware configurations on end-to-end distributed real-time and embedded (DRE) system quality of service (QoS). First, we describe how MDD techniques can help select middleware configuration parameters that satisfy key functional and QoS requirements of DRE systems. Second, we apply our MDD techniques to empirically evaluate the end-to-end QoS of representative DRE systems in the avionics and industrial manufacturing domains. Our results show how MDD techniques significantly enhance conventional ad hoc processes used by developers to configure middleware that meets the QoS needs of DRE systems.","PeriodicalId":291045,"journal":{"name":"11th IEEE Real Time and Embedded Technology and Applications Symposium","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125337721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Mathur, B. W. Edwards, Jacob Goldstein, H. Nguyen, Jeffrey Pine, B. Plante, J. Thacker, C. Hoover
Current flight software (FSW) systems embed customized pieces of software to control spacecraft instrumentation. Because spacecraft contain unique hardware components, reusing software device drivers or higher-level FSW subsystems dependent on the drivers across different missions is difficult; and changing instrumentation for an FSW is complicated and time-consuming. This paper outlines an innovative approach to design software components that interact reliably with aerospace instruments and applications while promoting reuse and ease of change. As building blocks for a flight instruments reuse & standardization library (FIRSL), the reusable software drivers are in the form of low-level devices or high-level composite devices for space-based missions. The paper also describes the proof of concept used to verify the results of applying the FIRSL design approach.
{"title":"An approach for designing reusable, embedded software components for spacecraft flight instruments","authors":"D. Mathur, B. W. Edwards, Jacob Goldstein, H. Nguyen, Jeffrey Pine, B. Plante, J. Thacker, C. Hoover","doi":"10.1109/RTAS.2005.7","DOIUrl":"https://doi.org/10.1109/RTAS.2005.7","url":null,"abstract":"Current flight software (FSW) systems embed customized pieces of software to control spacecraft instrumentation. Because spacecraft contain unique hardware components, reusing software device drivers or higher-level FSW subsystems dependent on the drivers across different missions is difficult; and changing instrumentation for an FSW is complicated and time-consuming. This paper outlines an innovative approach to design software components that interact reliably with aerospace instruments and applications while promoting reuse and ease of change. As building blocks for a flight instruments reuse & standardization library (FIRSL), the reusable software drivers are in the form of low-level devices or high-level composite devices for space-based missions. The paper also describes the proof of concept used to verify the results of applying the FIRSL design approach.","PeriodicalId":291045,"journal":{"name":"11th IEEE Real Time and Embedded Technology and Applications Symposium","volume":"332 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134022295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：