Pub Date : 2019-03-06DOI: 10.1109/ISDCS.2019.8719087
Tongxin Yang, Toshinori Sato, Tomoaki Ukezono
Modern applications such as image processing and deep learning are error tolerant in some level of inaccuracy. Approximate computing is one of the promising techniques that benefit applications in such domain by trading power for accuracy. This paper supposes applications that prioritize power and area over accuracy and proposes lower-power approximate multiply-add (MAC) unit with reduced area. The proposed MAC unit utilizes an approximate tree compressor (ATC), which was proposed in the previous study. From the experimental designs, it is unveiled that the proposed MAC unit consumes 48.7% less power and its area is 49.7% smaller than the conventional MAC unit.
{"title":"A Low-Power Approximate Multiply-Add Unit","authors":"Tongxin Yang, Toshinori Sato, Tomoaki Ukezono","doi":"10.1109/ISDCS.2019.8719087","DOIUrl":"https://doi.org/10.1109/ISDCS.2019.8719087","url":null,"abstract":"Modern applications such as image processing and deep learning are error tolerant in some level of inaccuracy. Approximate computing is one of the promising techniques that benefit applications in such domain by trading power for accuracy. This paper supposes applications that prioritize power and area over accuracy and proposes lower-power approximate multiply-add (MAC) unit with reduced area. The proposed MAC unit utilizes an approximate tree compressor (ATC), which was proposed in the previous study. From the experimental designs, it is unveiled that the proposed MAC unit consumes 48.7% less power and its area is 49.7% smaller than the conventional MAC unit.","PeriodicalId":293660,"journal":{"name":"2019 2nd International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121810297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/ISDCS.2019.8719102
Tera Sakata, Yu Mitani, K. Miyaji, Satoshi Kaneko, Takaharu Uekura, Hidetoshi Taki, Hideya Momose, K. Johguchi
Recently, demand for sweat measuring sensors has been increasing, especially for detection of heat stroke, dehydration and pathology of neurological diseases. Currently commercially available sensors are immobile, as they are large and require cables and hoses. Previous studies have presented a design that combines a custom chip analog to digital converter (ADC), discrete capacitive humidity and thermal sensors in a single board. In addition to the ADC, this study integrates a thermal sensor and a time to digital converter (TDC) into a chip. We evaluated the custom chip by comparing the readings of our chip with the market available discrete chip of ADT-7410 inside a environment chamber. Our custom chip size is 2.6 mm2 with a 0.18 $mu$m CMOS process including TDC and thermal sensor. Our system produces results comparable to those of a commercially available system, while being much smaller.
{"title":"A CMOS Integrated Sweat Monitoring System for Medical Applications","authors":"Tera Sakata, Yu Mitani, K. Miyaji, Satoshi Kaneko, Takaharu Uekura, Hidetoshi Taki, Hideya Momose, K. Johguchi","doi":"10.1109/ISDCS.2019.8719102","DOIUrl":"https://doi.org/10.1109/ISDCS.2019.8719102","url":null,"abstract":"Recently, demand for sweat measuring sensors has been increasing, especially for detection of heat stroke, dehydration and pathology of neurological diseases. Currently commercially available sensors are immobile, as they are large and require cables and hoses. Previous studies have presented a design that combines a custom chip analog to digital converter (ADC), discrete capacitive humidity and thermal sensors in a single board. In addition to the ADC, this study integrates a thermal sensor and a time to digital converter (TDC) into a chip. We evaluated the custom chip by comparing the readings of our chip with the market available discrete chip of ADT-7410 inside a environment chamber. Our custom chip size is 2.6 mm2 with a 0.18 $mu$m CMOS process including TDC and thermal sensor. Our system produces results comparable to those of a commercially available system, while being much smaller.","PeriodicalId":293660,"journal":{"name":"2019 2nd International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128378017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/ISDCS.2019.8719088
T. Iizuka, Hiroyuki Hashigami, M. Miura-Mattausch, H. Mattausch
Carrier generation due to impact ionization is an underlying physical mechanism in the snapback phenomenon. An exceedingly large amount of current during the snapback phenomenon is supplied from the two branches of carrier generation due to impact ionization; one originates from the surface channel current and the other from the source-junction injected current which tends to flow across a deeper location than the surface channel current. Device simulation for a power Laterally-Diffused MOSFET has revealed twin peaks of carrier generation rate distribution near the drain junction. This finding validates an incorporation of substrate current model equations in a common functional form to a MOSFET compact model, except for a distinct set of model parameters respectively; one for the shallow current and the other for the deep current.
{"title":"Validation on Duality in Impact-ionization Carrier Generation at the Onset of Snapback in Power MOSFETs","authors":"T. Iizuka, Hiroyuki Hashigami, M. Miura-Mattausch, H. Mattausch","doi":"10.1109/ISDCS.2019.8719088","DOIUrl":"https://doi.org/10.1109/ISDCS.2019.8719088","url":null,"abstract":"Carrier generation due to impact ionization is an underlying physical mechanism in the snapback phenomenon. An exceedingly large amount of current during the snapback phenomenon is supplied from the two branches of carrier generation due to impact ionization; one originates from the surface channel current and the other from the source-junction injected current which tends to flow across a deeper location than the surface channel current. Device simulation for a power Laterally-Diffused MOSFET has revealed twin peaks of carrier generation rate distribution near the drain junction. This finding validates an incorporation of substrate current model equations in a common functional form to a MOSFET compact model, except for a distinct set of model parameters respectively; one for the shallow current and the other for the deep current.","PeriodicalId":293660,"journal":{"name":"2019 2nd International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124027029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/ISDCS.2019.8719275
Soumajit Ghosh, V. Roshan, Avishek Dutta, Subhajit Das, T. Maiti, M. Miura-Mattausch, H. Rahaman
This work presents power MOSFET optimization strategy with second generation HiSIM_HV to design a DC-DC converter circuit as a highly efficient switch. A DC-DC power converter circuit optimization is performed by minimizing the values of the circuit elements, such as inductor, capacitor and resistor for very high frequency switching application. Switching losses and non-linearity of ON-resistance are taken care of to improve the efficiency of the switch at high frequency. We also performed DC and AC analyses of HiSIM_HV MOSFET with for BUCK converter circuit design. This optimization technique can be applicable to other DC-DC converters.
{"title":"Optimization of DC-DC Power Converter Design with Second Generation HiSIM_HV Model","authors":"Soumajit Ghosh, V. Roshan, Avishek Dutta, Subhajit Das, T. Maiti, M. Miura-Mattausch, H. Rahaman","doi":"10.1109/ISDCS.2019.8719275","DOIUrl":"https://doi.org/10.1109/ISDCS.2019.8719275","url":null,"abstract":"This work presents power MOSFET optimization strategy with second generation HiSIM_HV to design a DC-DC converter circuit as a highly efficient switch. A DC-DC power converter circuit optimization is performed by minimizing the values of the circuit elements, such as inductor, capacitor and resistor for very high frequency switching application. Switching losses and non-linearity of ON-resistance are taken care of to improve the efficiency of the switch at high frequency. We also performed DC and AC analyses of HiSIM_HV MOSFET with for BUCK converter circuit design. This optimization technique can be applicable to other DC-DC converters.","PeriodicalId":293660,"journal":{"name":"2019 2nd International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128134532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/ISDCS.2019.8719094
Subhajit Das, S. Bhattacharya, Debaprasad Das, H. Rahaman
In this work, a comparative stability analysis of copper (Cu), pristine and AsF5-intercalated top contact (TC) multilayer graphene nanoribbon (MLGNR) interconnect is presented. In this work, Bode stability formalism of AsF5 - intercalated TC-MLGNR interconnect using ABCD transmission parameter based multi-conductor transmission line model, has been presented for the first time. The variation in stability has been studied for conventional copper, pristine and AsF5 intercalated interconnect for different interconnect lengths (10$mu$m and 100$mu$m) and different level of edge roughness. It is shown that, AsF5-interclation doped TC-MLGNR interconnects offer better stability, for similar dimensions, than its pristine counterpart as well as conventional copper wires at local, intermediate and global interconnect for high frequency applications.
{"title":"Comparative Stability Analysis of Pristine and AsF5 Intercalation Doped Top Contact Graphene Nano Ribbon Interconnects","authors":"Subhajit Das, S. Bhattacharya, Debaprasad Das, H. Rahaman","doi":"10.1109/ISDCS.2019.8719094","DOIUrl":"https://doi.org/10.1109/ISDCS.2019.8719094","url":null,"abstract":"In this work, a comparative stability analysis of copper (Cu), pristine and AsF5-intercalated top contact (TC) multilayer graphene nanoribbon (MLGNR) interconnect is presented. In this work, Bode stability formalism of AsF5 - intercalated TC-MLGNR interconnect using ABCD transmission parameter based multi-conductor transmission line model, has been presented for the first time. The variation in stability has been studied for conventional copper, pristine and AsF5 intercalated interconnect for different interconnect lengths (10$mu$m and 100$mu$m) and different level of edge roughness. It is shown that, AsF5-interclation doped TC-MLGNR interconnects offer better stability, for similar dimensions, than its pristine counterpart as well as conventional copper wires at local, intermediate and global interconnect for high frequency applications.","PeriodicalId":293660,"journal":{"name":"2019 2nd International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"173 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134413193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/ISDCS.2019.8719265
K. Inoue, Nozomi Kobori, Atsushi Hirota, T. Koide, Takumi Okamoto
We’ve demonstrated an experimental IoT network, where the bottom sensor network, the bridged IP network and the upper information-centric network are combined together. This architecture provides that the user easily gets to the required information, and takes place of today’s P2P and Client & Server model.
{"title":"An IoT-gateway with the information-centric communication","authors":"K. Inoue, Nozomi Kobori, Atsushi Hirota, T. Koide, Takumi Okamoto","doi":"10.1109/ISDCS.2019.8719265","DOIUrl":"https://doi.org/10.1109/ISDCS.2019.8719265","url":null,"abstract":"We’ve demonstrated an experimental IoT network, where the bottom sensor network, the bridged IP network and the upper information-centric network are combined together. This architecture provides that the user easily gets to the required information, and takes place of today’s P2P and Client & Server model.","PeriodicalId":293660,"journal":{"name":"2019 2nd International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134428664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/ISDCS.2019.8719259
H. Sasaki
Various types of data streams such as ultra-high-definition videos and the fifth generation mobile services may require both flexible network management and large capacity of transmission for the optical access networks. Time and Wavelength Division Multiplexing-Passive Optical Network (TWDM-PON) is regarded as a promising candidate for such applications realizing the aggregated bandwidth of 40 Gbps with four wavelength multiplexed 10 Gbps optical signals. Silicon (Si) photonics technology is critical to implement such bi-directional WDM optical transmission functions into a single ultra-compact photonic integrated circuit (PIC) at relatively low cost. The current status of the Si PIC development is reported. The PIC consists of following functional devices; a spot-size convertor for the efficient coupling between a Si waveguide and a single-mode optical fiber, the first WDM filter to separate bi-directional optical signals into up and down-stream signals, the second WDM filter for 100 GHz-wavelength separation, an array of avalanche photodiodes (APDs) for down-stream signal detection, and a modulator to modulate up-stream signals. A semiconductor laser diode die is surface mounted on the PIC. The detail of both device design and experimental results are discussed.
{"title":"Development of Silicon Photonics Integrated Circuits for Next Generation Optical Access Networks","authors":"H. Sasaki","doi":"10.1109/ISDCS.2019.8719259","DOIUrl":"https://doi.org/10.1109/ISDCS.2019.8719259","url":null,"abstract":"Various types of data streams such as ultra-high-definition videos and the fifth generation mobile services may require both flexible network management and large capacity of transmission for the optical access networks. Time and Wavelength Division Multiplexing-Passive Optical Network (TWDM-PON) is regarded as a promising candidate for such applications realizing the aggregated bandwidth of 40 Gbps with four wavelength multiplexed 10 Gbps optical signals. Silicon (Si) photonics technology is critical to implement such bi-directional WDM optical transmission functions into a single ultra-compact photonic integrated circuit (PIC) at relatively low cost. The current status of the Si PIC development is reported. The PIC consists of following functional devices; a spot-size convertor for the efficient coupling between a Si waveguide and a single-mode optical fiber, the first WDM filter to separate bi-directional optical signals into up and down-stream signals, the second WDM filter for 100 GHz-wavelength separation, an array of avalanche photodiodes (APDs) for down-stream signal detection, and a modulator to modulate up-stream signals. A semiconductor laser diode die is surface mounted on the PIC. The detail of both device design and experimental results are discussed.","PeriodicalId":293660,"journal":{"name":"2019 2nd International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126184055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/ISDCS.2019.8719249
S. Ghosal, I. Maity, P. Bhattacharyya
In the present work, the comparison of the hybrid structure (TiO2NT/RGO: TiO2 nanotube (TiO2NT) and Reduced Graphene Oxide (RGO)), along with its pristine counterpart (TiO2NT) based device, related to its fabrication, characterization and oxidizing vapor sensing potentiality integrated with Micro-heater, is reported. On top of the microheater, the deposited sputtered metal is Titanium (Ti) and Platinum (Pt) with the thickness of 10 nm / 80 nm. The calculated Temperature Coefficient of Resistance (TCR) of the sensor is 0.001690 and it’s determined by the measuring of resistance. The temperature of heater is selected in between of $25^{circ}mathrm{C}-250^{circ}mathrm{C}$. TiO2 nanotubes were fabricated through anodization method and the nanotubes were covered via the RGO layer in an unequal manner. After the detailed study, the vapor sensing performance of the pristine structure along with its hybrid counterpart were tested for the detection of different oxidizing vapor like CO2 and NO. The hybrid sensor showed $sim$35%, $sim$58.14%, and $sim$66.06% response magnitude for 5 ppm, 10 ppm, and 50 ppm of CO2 vapor concentrations, with the optimum temperature of $60^{circ}mathrm{lt pgt C}$ respectively, whereas for the pristine (the nanotube sensor) structure the nanotube sensor offered the response magnitude of $sim$21.08%, $sim$33.25% and $sim$51.76% respectively, at its optimum temperature of $135^{circ}mathrm{C}$. After doing the comprehensive illustration between the pristine structure and the hybrid structure, a detailed discussion has been presented correlating different sensing parameters like response magnitude, response time and recovery time.
{"title":"An Integrated CO2 Sensor Using TiO2NT/RGO Hybrid Sensing Layer with embedded Micro hot Plate","authors":"S. Ghosal, I. Maity, P. Bhattacharyya","doi":"10.1109/ISDCS.2019.8719249","DOIUrl":"https://doi.org/10.1109/ISDCS.2019.8719249","url":null,"abstract":"In the present work, the comparison of the hybrid structure (TiO2NT/RGO: TiO2 nanotube (TiO2NT) and Reduced Graphene Oxide (RGO)), along with its pristine counterpart (TiO2NT) based device, related to its fabrication, characterization and oxidizing vapor sensing potentiality integrated with Micro-heater, is reported. On top of the microheater, the deposited sputtered metal is Titanium (Ti) and Platinum (Pt) with the thickness of 10 nm / 80 nm. The calculated Temperature Coefficient of Resistance (TCR) of the sensor is 0.001690 and it’s determined by the measuring of resistance. The temperature of heater is selected in between of $25^{circ}mathrm{C}-250^{circ}mathrm{C}$. TiO2 nanotubes were fabricated through anodization method and the nanotubes were covered via the RGO layer in an unequal manner. After the detailed study, the vapor sensing performance of the pristine structure along with its hybrid counterpart were tested for the detection of different oxidizing vapor like CO2 and NO. The hybrid sensor showed $sim$35%, $sim$58.14%, and $sim$66.06% response magnitude for 5 ppm, 10 ppm, and 50 ppm of CO2 vapor concentrations, with the optimum temperature of $60^{circ}mathrm{lt pgt C}$ respectively, whereas for the pristine (the nanotube sensor) structure the nanotube sensor offered the response magnitude of $sim$21.08%, $sim$33.25% and $sim$51.76% respectively, at its optimum temperature of $135^{circ}mathrm{C}$. After doing the comprehensive illustration between the pristine structure and the hybrid structure, a detailed discussion has been presented correlating different sensing parameters like response magnitude, response time and recovery time.","PeriodicalId":293660,"journal":{"name":"2019 2nd International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125741518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/ISDCS.2019.8719263
H. Murakami, Yoshiki Tanaka, Junichi Yamashita, Rikako Takeshita, Yasunori Sakane, Takumi Okamoto, T. Koide
Quantitative data on the correlation between the state and the environment of agricultural crops is expected to make agricultural factories economically sustainable. In this work, growth rate of agricultural crops from images is quantified using by optical flow technique. Additionally, we developed system for management of measurement devices and analyzing obtained data.
{"title":"Development of In-situ Monitoring System for Crop Growth Observation","authors":"H. Murakami, Yoshiki Tanaka, Junichi Yamashita, Rikako Takeshita, Yasunori Sakane, Takumi Okamoto, T. Koide","doi":"10.1109/ISDCS.2019.8719263","DOIUrl":"https://doi.org/10.1109/ISDCS.2019.8719263","url":null,"abstract":"Quantitative data on the correlation between the state and the environment of agricultural crops is expected to make agricultural factories economically sustainable. In this work, growth rate of agricultural crops from images is quantified using by optical flow technique. Additionally, we developed system for management of measurement devices and analyzing obtained data.","PeriodicalId":293660,"journal":{"name":"2019 2nd International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122693353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/ISDCS.2019.8719250
Mingjun Liu, Qian Xie, Shuang Xia, Z. Wang
In this paper, a novel TFET architecture named the step-shaped gate TFET (SSG-TFET) has been proposed for the suppression of the ambipolar current. By adjusting the energy band, the SSG-TFET can evidently reduce the ambipolar current. We compare the proposed SSG-TFET with the conventional DGTFET, gate overlap on drain TFET (OGTFET) and gate underlap TFET (SG-TFET) by using TCAD tool Sentaurus and found that the SSG-TFET can evidently suppress the ambipolar current. To be specific, the ambipolar current of the SSG-TFET decreases 7 orders of magnitude from 10$^{-9} {A}/mu$m for conventional TFET to 10$^{-16}{A}/mu$m atVgs = -1.5 V. For the proposed SSG-TFET, we have found that there exists an optimal right gate dielectric thickness toxdb with minimum ambipolar current of SSG-TFET. Moreover, we investigate the influence of the Si body thickness tsi, the length of the oxide layer exceeds the interface of channel and the drain on the optimal thickness of the right gate dielectric of the SSG-TFET. The simulation results show that the optimal oxide layer thickness toxdb decreases with the increase of $t_{s}$, and toxdb increases with the increase length of Lun and Lov, but when Lov $gt 40$ nm, toxdb remains the same. The proposed SSG-TFET with low ambipolar current can be used for the ultra-low power integrated circuit applications.
{"title":"A Novel Step-shaped Gate Tunnel FET with Low Ambipolar Current","authors":"Mingjun Liu, Qian Xie, Shuang Xia, Z. Wang","doi":"10.1109/ISDCS.2019.8719250","DOIUrl":"https://doi.org/10.1109/ISDCS.2019.8719250","url":null,"abstract":"In this paper, a novel TFET architecture named the step-shaped gate TFET (SSG-TFET) has been proposed for the suppression of the ambipolar current. By adjusting the energy band, the SSG-TFET can evidently reduce the ambipolar current. We compare the proposed SSG-TFET with the conventional DGTFET, gate overlap on drain TFET (OGTFET) and gate underlap TFET (SG-TFET) by using TCAD tool Sentaurus and found that the SSG-TFET can evidently suppress the ambipolar current. To be specific, the ambipolar current of the SSG-TFET decreases 7 orders of magnitude from 10$^{-9} {A}/mu$m for conventional TFET to 10$^{-16}{A}/mu$m atVgs = -1.5 V. For the proposed SSG-TFET, we have found that there exists an optimal right gate dielectric thickness toxdb with minimum ambipolar current of SSG-TFET. Moreover, we investigate the influence of the Si body thickness tsi, the length of the oxide layer exceeds the interface of channel and the drain on the optimal thickness of the right gate dielectric of the SSG-TFET. The simulation results show that the optimal oxide layer thickness toxdb decreases with the increase of $t_{s}$, and toxdb increases with the increase length of Lun and Lov, but when Lov $gt 40$ nm, toxdb remains the same. The proposed SSG-TFET with low ambipolar current can be used for the ultra-low power integrated circuit applications.","PeriodicalId":293660,"journal":{"name":"2019 2nd International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"352 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115163810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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