Pub Date : 2019-11-01DOI: 10.1109/ICRC.2019.8914703
B. Reznychenko, Y. Paltiel, F. Remacle, M. Striccoli, E. Mazer, Maurizio Coden, E. Collini, Carlo Nazareno Dibenedetto, A. Donval, B. Fresch, Hugo Gattuso, N. Gross
The quantum properties of nanosystems present a new opportunity to enhance the power of classical computers, both for the parallelism of the computation and the speed of the optical operations. In this paper we present the COPAC project aiming at development of a ground-breaking nonlinear coherent spectroscopy combining optical addressing and spatially macroscopically resolved optical readout. The discrete structure of transitions between quantum levels provides a basis for implementation of logic functions even at room temperature. Exploiting the superposition of quantum states gives rise to the possibility of parallel computation by encoding different input values into transition frequencies. As an example of parallel single instruction multiple data calculation by a device developed during the COPAC project, we present a n-bit adder, showing that due to the properties of the system, the delay of this fundamental circuit can be reduced.
{"title":"An n-Bit Adder Realized via Coherent Optical Parallel Computing","authors":"B. Reznychenko, Y. Paltiel, F. Remacle, M. Striccoli, E. Mazer, Maurizio Coden, E. Collini, Carlo Nazareno Dibenedetto, A. Donval, B. Fresch, Hugo Gattuso, N. Gross","doi":"10.1109/ICRC.2019.8914703","DOIUrl":"https://doi.org/10.1109/ICRC.2019.8914703","url":null,"abstract":"The quantum properties of nanosystems present a new opportunity to enhance the power of classical computers, both for the parallelism of the computation and the speed of the optical operations. In this paper we present the COPAC project aiming at development of a ground-breaking nonlinear coherent spectroscopy combining optical addressing and spatially macroscopically resolved optical readout. The discrete structure of transitions between quantum levels provides a basis for implementation of logic functions even at room temperature. Exploiting the superposition of quantum states gives rise to the possibility of parallel computation by encoding different input values into transition frequencies. As an example of parallel single instruction multiple data calculation by a device developed during the COPAC project, we present a n-bit adder, showing that due to the properties of the system, the delay of this fundamental circuit can be reduced.","PeriodicalId":297574,"journal":{"name":"2019 IEEE International Conference on Rebooting Computing (ICRC)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124885421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-11-01DOI: 10.1109/ICRC.2019.8914718
Genki Ohashi, Hirosato Seki, M. Inuiguchi
In the conventional fuzzy inference models, various learning methods have been proposed. It is generally impossible to apply the steepest descent method to fuzzy inference models with consequent fuzzy sets, such as Mamdani's fuzzy inference model because it uses min and max operations in the inference process. Therefore, the Genetic Algorithm (GA) was useful for learning of the above model. In addition, it has been also proposed the method for obtaining fuzzy rules of the fuzzy inference models unified max operation from the steepest descent method by using equivalence property. On the other hand, Single Input Connected (SIC) fuzzy inference model can set a fuzzy rule of 1 input 1 output, so the number of rules can be reduced drastically. In the learning method of SIC model unified max operation with consequent fuzzy sets, GA was only applied to the model. Therefore, this paper proposes a leaning method of SIC model unified max operation with consequent fuzzy sets by using equivalence. Moreover, the proposed method is applied to a medical diagnosis and compared with the SIC model by using GA.
{"title":"On a Learning Method of the SIC Fuzzy Inference Model with Consequent Fuzzy Sets","authors":"Genki Ohashi, Hirosato Seki, M. Inuiguchi","doi":"10.1109/ICRC.2019.8914718","DOIUrl":"https://doi.org/10.1109/ICRC.2019.8914718","url":null,"abstract":"In the conventional fuzzy inference models, various learning methods have been proposed. It is generally impossible to apply the steepest descent method to fuzzy inference models with consequent fuzzy sets, such as Mamdani's fuzzy inference model because it uses min and max operations in the inference process. Therefore, the Genetic Algorithm (GA) was useful for learning of the above model. In addition, it has been also proposed the method for obtaining fuzzy rules of the fuzzy inference models unified max operation from the steepest descent method by using equivalence property. On the other hand, Single Input Connected (SIC) fuzzy inference model can set a fuzzy rule of 1 input 1 output, so the number of rules can be reduced drastically. In the learning method of SIC model unified max operation with consequent fuzzy sets, GA was only applied to the model. Therefore, this paper proposes a leaning method of SIC model unified max operation with consequent fuzzy sets by using equivalence. Moreover, the proposed method is applied to a medical diagnosis and compared with the SIC model by using GA.","PeriodicalId":297574,"journal":{"name":"2019 IEEE International Conference on Rebooting Computing (ICRC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127515009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-11-01DOI: 10.1109/ICRC.2019.8914705
M. Foltin, G. Aguiar, Rodrigo Antunes, P. Silveira, Gustavo Knuppe, J. Ambrosi, Soumitra Chatterjee, J. Kolhe, Sunil Lakshiminarashimha, D. Milojicic, J. Strachan, C. Warner, Amit Sharma, Eddie Lee, S. R. Chalamalasetti, C. Brueggen, Charles Williams, Nathaniel Jansen, Felipe Saenz, Luis Federico Li
Hybrid analog-digital neuromorphic accelerators show promise for significant increase in performance per watt of deep learning inference and training as compared with conventional technologies. In this work we present an FPGA demonstrator of a programmable hybrid inferencing accelerator, with memristor analog dot product engines emulated by digital matrix-vector multiplication units employing FPGA SRAM memory for in-situ weight storage. The full-chip demonstrator interfaced to a host by PCIe interface serves as a software development platform and a vehicle for further hardware microarchitecture improvements. Implementation of compute cores, tiles, network on a chip, and the host interface is discussed. New pipelining scheme is introduced to achieve high utilization of matrix-vector multiplication units while reducing tile data memory size requirements for neural network layer activations. The data flow orchestration between the tiles is described, controlled by a RISC-V core. Inferencing accuracy analysis is presented for an example RNN and CNN models. The demonstrator is instrumented with hardware monitors to enable performance measurements and tuning. Performance projections for future memristor-based ASIC are also discussed.
{"title":"FPGA Demonstrator of a Programmable Ultra-Efficient Memristor-Based Machine Learning Inference Accelerator","authors":"M. Foltin, G. Aguiar, Rodrigo Antunes, P. Silveira, Gustavo Knuppe, J. Ambrosi, Soumitra Chatterjee, J. Kolhe, Sunil Lakshiminarashimha, D. Milojicic, J. Strachan, C. Warner, Amit Sharma, Eddie Lee, S. R. Chalamalasetti, C. Brueggen, Charles Williams, Nathaniel Jansen, Felipe Saenz, Luis Federico Li","doi":"10.1109/ICRC.2019.8914705","DOIUrl":"https://doi.org/10.1109/ICRC.2019.8914705","url":null,"abstract":"Hybrid analog-digital neuromorphic accelerators show promise for significant increase in performance per watt of deep learning inference and training as compared with conventional technologies. In this work we present an FPGA demonstrator of a programmable hybrid inferencing accelerator, with memristor analog dot product engines emulated by digital matrix-vector multiplication units employing FPGA SRAM memory for in-situ weight storage. The full-chip demonstrator interfaced to a host by PCIe interface serves as a software development platform and a vehicle for further hardware microarchitecture improvements. Implementation of compute cores, tiles, network on a chip, and the host interface is discussed. New pipelining scheme is introduced to achieve high utilization of matrix-vector multiplication units while reducing tile data memory size requirements for neural network layer activations. The data flow orchestration between the tiles is described, controlled by a RISC-V core. Inferencing accuracy analysis is presented for an example RNN and CNN models. The demonstrator is instrumented with hardware monitors to enable performance measurements and tuning. Performance projections for future memristor-based ASIC are also discussed.","PeriodicalId":297574,"journal":{"name":"2019 IEEE International Conference on Rebooting Computing (ICRC)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133610292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-11-01DOI: 10.1109/ICRC.2019.8914709
Zhong Sun, G. Pedretti, D. Ielmini
The in-memory solution of linear systems with analog resistive switching memory in one computational step has been recently reported. In this work, we investigate the time complexity of solving linear systems with the circuit, based on the feedback theory of amplifiers. The result shows that the computing time is explicitly independent on the problem size N, rather it is dominated by the minimal eigenvalue of an associated matrix. By addressing the Toeplitz matrix and the Wishart matrix, we show that the computing time increases with log(N) or N1/2, respectively, thus indicating a significant speed-up of in-memory computing over classical digital computing for solving linear systems. For sparse positive-definite matrix that is targeted by a quantum computing algorithm, the in-memory computing circuit also shows a computing time superiority. These results support in-memory computing as a strong candidate for fast and energy-efficient accelerators of big data analytics and machine learning.
{"title":"Fast Solution of Linear Systems with Analog Resistive Switching Memory (RRAM)","authors":"Zhong Sun, G. Pedretti, D. Ielmini","doi":"10.1109/ICRC.2019.8914709","DOIUrl":"https://doi.org/10.1109/ICRC.2019.8914709","url":null,"abstract":"The in-memory solution of linear systems with analog resistive switching memory in one computational step has been recently reported. In this work, we investigate the time complexity of solving linear systems with the circuit, based on the feedback theory of amplifiers. The result shows that the computing time is explicitly independent on the problem size N, rather it is dominated by the minimal eigenvalue of an associated matrix. By addressing the Toeplitz matrix and the Wishart matrix, we show that the computing time increases with log(N) or N1/2, respectively, thus indicating a significant speed-up of in-memory computing over classical digital computing for solving linear systems. For sparse positive-definite matrix that is targeted by a quantum computing algorithm, the in-memory computing circuit also shows a computing time superiority. These results support in-memory computing as a strong candidate for fast and energy-efficient accelerators of big data analytics and machine learning.","PeriodicalId":297574,"journal":{"name":"2019 IEEE International Conference on Rebooting Computing (ICRC)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133242369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-11-01DOI: 10.1109/ICRC.2019.8914716
S. Tran, C. Teuscher
The quest for novel computing architectures is currently driven by (1) machine learning applications and (2) the need to reduce power consumption. To address both needs, we present a novel hierarchical reservoir computing architecture that relies on energy-efficient memcapacitive devices. Reservoir computing is a new brain-inspired machine learning architecture that typically relies on a monolithic, i.e., unstructured, network of devices. We use memcapacitive devices to perform the computations because they do not consume static power. Our results show that hierarchical memcapacitive reservoir computing device networks have a higher kernel quality, outperform monolithic reservoirs by 10%, and reduce the power consumption by a factor of 3.4× on our benchmark tasks. The proposed new architecture is relevant for building novel, adaptive, and power-efficient neuromorphic hardware with applications in embedded systems, the Internet-of-Things, and robotics.
{"title":"Hierarchical Memcapacitive Reservoir Computing Architecture","authors":"S. Tran, C. Teuscher","doi":"10.1109/ICRC.2019.8914716","DOIUrl":"https://doi.org/10.1109/ICRC.2019.8914716","url":null,"abstract":"The quest for novel computing architectures is currently driven by (1) machine learning applications and (2) the need to reduce power consumption. To address both needs, we present a novel hierarchical reservoir computing architecture that relies on energy-efficient memcapacitive devices. Reservoir computing is a new brain-inspired machine learning architecture that typically relies on a monolithic, i.e., unstructured, network of devices. We use memcapacitive devices to perform the computations because they do not consume static power. Our results show that hierarchical memcapacitive reservoir computing device networks have a higher kernel quality, outperform monolithic reservoirs by 10%, and reduce the power consumption by a factor of 3.4× on our benchmark tasks. The proposed new architecture is relevant for building novel, adaptive, and power-efficient neuromorphic hardware with applications in embedded systems, the Internet-of-Things, and robotics.","PeriodicalId":297574,"journal":{"name":"2019 IEEE International Conference on Rebooting Computing (ICRC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133272296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-11-01DOI: 10.1109/ICRC.2019.8914704
S. Serebryakov, D. Milojicic, N. Vassilieva, S. Fleischman, R. Clark
Deep Learning (DL) has gained wide adoption and different DL models have been deployed for an expanding number of applications. It is being used both for inference at the edge and for training in datacenters. Applications include image recognition, video analytics, pattern recognition in networking traffic, and many others. Different applications rely on different neural network models, and it has proven difficult to predict resource requirements for different models and applications. This leads to the nonsystematic and suboptimal selection of computational resources for DL applications resulting in overpaying for underutilized infrastructure or, even worse, the deployment of models on underpowered hardware and missed service level objectives. In this paper we present the DL Cookbook, a toolset that a) helps with benchmarking models on different hardware, b) guides the use of DL and c) provides reference designs. Automated benchmarking collects performance data for different DL workloads (training and inference with different models) on various hardware and software configurations. A web-based tool guides a choice of optimal hardware and software configuration via analysis of collected performance data and applying performance models. And finally, it offers reference hardware/software stacks for particular classes of deep learning workloads. This way the DL Cookbook helps both customers and hardware vendors match optimal DL models to the available hardware and vice versa, in case of acquisition, specify required hardware to models in question. Finally, DL Cookbook helps with reproducibility of results.
{"title":"Deep Learning Cookbook: Recipes for your AI Infrastructure and Applications","authors":"S. Serebryakov, D. Milojicic, N. Vassilieva, S. Fleischman, R. Clark","doi":"10.1109/ICRC.2019.8914704","DOIUrl":"https://doi.org/10.1109/ICRC.2019.8914704","url":null,"abstract":"Deep Learning (DL) has gained wide adoption and different DL models have been deployed for an expanding number of applications. It is being used both for inference at the edge and for training in datacenters. Applications include image recognition, video analytics, pattern recognition in networking traffic, and many others. Different applications rely on different neural network models, and it has proven difficult to predict resource requirements for different models and applications. This leads to the nonsystematic and suboptimal selection of computational resources for DL applications resulting in overpaying for underutilized infrastructure or, even worse, the deployment of models on underpowered hardware and missed service level objectives. In this paper we present the DL Cookbook, a toolset that a) helps with benchmarking models on different hardware, b) guides the use of DL and c) provides reference designs. Automated benchmarking collects performance data for different DL workloads (training and inference with different models) on various hardware and software configurations. A web-based tool guides a choice of optimal hardware and software configuration via analysis of collected performance data and applying performance models. And finally, it offers reference hardware/software stacks for particular classes of deep learning workloads. This way the DL Cookbook helps both customers and hardware vendors match optimal DL models to the available hardware and vice versa, in case of acquisition, specify required hardware to models in question. Finally, DL Cookbook helps with reproducibility of results.","PeriodicalId":297574,"journal":{"name":"2019 IEEE International Conference on Rebooting Computing (ICRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130858272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-11-01DOI: 10.1109/ICRC.2019.8914697
S. Kulkarni, Sachin Bhat, C. A. Moritz
The machinery of life operates on the complex interactions between genes and proteins. Attempts to capture these interactions have culminated into the study of Genetic Networks. Genetic defects lead to erroneous interactions, which in turn lead to diseases. For personalized treatment of these diseases, a careful analysis of Genetic Networks and a patient's genetic data is required. In this work, we co-design a novel probabilistic AI model along with a reconfigurable architecture to enable personalized treatment for cancer patients. This approach enables a cost-effective and scalable solution for widespread use of personalized medicine. Our model offers interpretability and realistic confidences in its predictions, which is essential for medical applications. The resulting personalized inference on a dataset of 3k patients agrees with doctor's treatment choices in 80% of the cases. The other cases are diverging from the universal guideline, enabling individualized treatment options based on genetic data. Our architecture is validated on a hybrid SoC-FPGA platform which performs 25× faster than software, implemented on a 16-core Xeon workstation, while consuming 25× less power.
{"title":"Reconfigurable Probabilistic AI Architecture for Personalized Cancer Treatment","authors":"S. Kulkarni, Sachin Bhat, C. A. Moritz","doi":"10.1109/ICRC.2019.8914697","DOIUrl":"https://doi.org/10.1109/ICRC.2019.8914697","url":null,"abstract":"The machinery of life operates on the complex interactions between genes and proteins. Attempts to capture these interactions have culminated into the study of Genetic Networks. Genetic defects lead to erroneous interactions, which in turn lead to diseases. For personalized treatment of these diseases, a careful analysis of Genetic Networks and a patient's genetic data is required. In this work, we co-design a novel probabilistic AI model along with a reconfigurable architecture to enable personalized treatment for cancer patients. This approach enables a cost-effective and scalable solution for widespread use of personalized medicine. Our model offers interpretability and realistic confidences in its predictions, which is essential for medical applications. The resulting personalized inference on a dataset of 3k patients agrees with doctor's treatment choices in 80% of the cases. The other cases are diverging from the universal guideline, enabling individualized treatment options based on genetic data. Our architecture is validated on a hybrid SoC-FPGA platform which performs 25× faster than software, implemented on a 16-core Xeon workstation, while consuming 25× less power.","PeriodicalId":297574,"journal":{"name":"2019 IEEE International Conference on Rebooting Computing (ICRC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133745480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-11-01DOI: 10.1109/ICRC.2019.8914715
D. Mountain
Theshold gates are a specific type of neural network that have been shown to be valuable for cybersecurity applications. These networks can be implemented using analog processing in memristive crossbar arrays. For these types of designs, the performance of the comparator circuit is a critical factor in the overall capabilities of the neural network. In this work a relatively simple comparator design is demonstrated to be compact, low-power, and fast. The design takes advantage of features inherent in the neural net architecture and memristor technology. This paper includes the basic design and specific enhancements to improve its capabilities, along with power, area, and timing estimates.
{"title":"A Comparator Design Targeted towards Neural Nets","authors":"D. Mountain","doi":"10.1109/ICRC.2019.8914715","DOIUrl":"https://doi.org/10.1109/ICRC.2019.8914715","url":null,"abstract":"Theshold gates are a specific type of neural network that have been shown to be valuable for cybersecurity applications. These networks can be implemented using analog processing in memristive crossbar arrays. For these types of designs, the performance of the comparator circuit is a critical factor in the overall capabilities of the neural network. In this work a relatively simple comparator design is demonstrated to be compact, low-power, and fast. The design takes advantage of features inherent in the neural net architecture and memristor technology. This paper includes the basic design and specific enhancements to improve its capabilities, along with power, area, and timing estimates.","PeriodicalId":297574,"journal":{"name":"2019 IEEE International Conference on Rebooting Computing (ICRC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122067470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-11-01DOI: 10.1109/ICRC.2019.8914708
O. Yakar, Yuqi Nie, K. Wada, Anuradha Agarwal, İlke Ercan
The saturation of rapid progress in transistor technology has brought us to a point where the computing systems face fundamental physical limitations. Emerging technologies propose various alternatives and photonic circuits are among promising candidates due to their high operation speed, energy efficient passive components, low crosstalk and appropriateness for parallel computation. In this work, we design a microring resonator (MRR) based Binary Decision Diagram (BDD) NAND logic gate and study its characteristics inline with a MRR-based BDD half adder circuit proposed by Wada et. al. [1]. We analyze energy efficiency limitations of BDD architectures using reversible and irreversible circuit structures. The circuits we focus on in this work are composed of silicon MRR-based switching nodes where the coupling gap and ring size play a key role in the performance of the circuits. We study the physical structure of the circuits as well as dynamics of the information processing, and calculate the fundamental lower bounds on the energy dissipation as a result of computation. We also perform extensive analyses on Lumerical MODE simulations to optimize the energy efficiency based on various factors including waveguide properties, ring radius and gap size. The results we obtain allow us to assess limitations imposed by the physical nature of MRR-based photonic circuits in computation, and compare theory against simulation and hence significantly contribute to the strategic development of this technology as a part of future computers.
{"title":"Energy Efficiency of Microring Resonator (MRR)-Based Binary Decision Diagram (BDD) Circuits","authors":"O. Yakar, Yuqi Nie, K. Wada, Anuradha Agarwal, İlke Ercan","doi":"10.1109/ICRC.2019.8914708","DOIUrl":"https://doi.org/10.1109/ICRC.2019.8914708","url":null,"abstract":"The saturation of rapid progress in transistor technology has brought us to a point where the computing systems face fundamental physical limitations. Emerging technologies propose various alternatives and photonic circuits are among promising candidates due to their high operation speed, energy efficient passive components, low crosstalk and appropriateness for parallel computation. In this work, we design a microring resonator (MRR) based Binary Decision Diagram (BDD) NAND logic gate and study its characteristics inline with a MRR-based BDD half adder circuit proposed by Wada et. al. [1]. We analyze energy efficiency limitations of BDD architectures using reversible and irreversible circuit structures. The circuits we focus on in this work are composed of silicon MRR-based switching nodes where the coupling gap and ring size play a key role in the performance of the circuits. We study the physical structure of the circuits as well as dynamics of the information processing, and calculate the fundamental lower bounds on the energy dissipation as a result of computation. We also perform extensive analyses on Lumerical MODE simulations to optimize the energy efficiency based on various factors including waveguide properties, ring radius and gap size. The results we obtain allow us to assess limitations imposed by the physical nature of MRR-based photonic circuits in computation, and compare theory against simulation and hence significantly contribute to the strategic development of this technology as a part of future computers.","PeriodicalId":297574,"journal":{"name":"2019 IEEE International Conference on Rebooting Computing (ICRC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117070005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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