We describe a method to compute high-quality antialiased lines by adding a modest amount of hardware to a fragment generator based upon half-plane edge functions. (A fragment contains the information needed to paint one pixel of a line or a polygon.) We surround an antialiased line with four edge functions to create a long, thin, rectangle. We scale the edge functions so that they compute signed distances from the four edges. At each fragment within the antialiased line, the four distances to the fragment are combined and the result indexes an intensity table. The table is computed by convolving a filter kernel with a prototypical line at various distances from the line's edge. Because the convolutions aren't performed in hardware, we can use wider, more complex filters with better high-frequency rejection than the narrow box filter common to supersampling antialiasing hardware. The result is smoother antialiased lines. Our algorithm is parameterized by the line width and filter radius. These parameters do not affect the rendering algorithm, but only the setup of the edge functions. Our algorithm antialiases line endpoints without special handling. We exploit this to paint small blurry squares as approximations to small antialiased round points. We do not need a different fragment generator for antialiased lines, and so can take advantage of all optimizations introduced in the existing fragment generator.
{"title":"Prefiltered antialiased lines using half-plane distance functions","authors":"Bob McNamara, Joel McCormack, N. Jouppi","doi":"10.1145/346876.348226","DOIUrl":"https://doi.org/10.1145/346876.348226","url":null,"abstract":"We describe a method to compute high-quality antialiased lines by adding a modest amount of hardware to a fragment generator based upon half-plane edge functions. (A fragment contains the information needed to paint one pixel of a line or a polygon.) We surround an antialiased line with four edge functions to create a long, thin, rectangle. We scale the edge functions so that they compute signed distances from the four edges. At each fragment within the antialiased line, the four distances to the fragment are combined and the result indexes an intensity table. The table is computed by convolving a filter kernel with a prototypical line at various distances from the line's edge. Because the convolutions aren't performed in hardware, we can use wider, more complex filters with better high-frequency rejection than the narrow box filter common to supersampling antialiasing hardware. The result is smoother antialiased lines. Our algorithm is parameterized by the line width and filter radius. These parameters do not affect the rendering algorithm, but only the setup of the edge functions. Our algorithm antialiases line endpoints without special handling. We exploit this to paint small blurry squares as approximations to small antialiased round points. We do not need a different fragment generator for antialiased lines, and so can take advantage of all optimizations introduced in the existing fragment generator.","PeriodicalId":298241,"journal":{"name":"Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware","volume":"97 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131486970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Rezk-Salama, Klaus Engel, M. Bauer, G. Greiner, T. Ertl
Interactive direct volume rendering has yet been restricted to high-end graphics workstations and special-purpose hardware, due to the large amount of trilinear interpolations, that are necessary to obtain high image quality. Implementations that use the 2D-texture capabilities of standard PC hardware, usually render object-aligned slices in order to substitute trilinear by bilinear interpolation. However the resulting images often contain visual artifacts caused by the lack of spatial interpolation. In this paper we propose new rendering techniques that significantly improve both performance and image quality of the 2D-texture based approach. We will show how in ulti-texturing capabilitiesof modern consumer PC graphboards are exploited to enable in teractive high quality volume visualization on low-cost hardware. Furthermore we demonstrate how multi-stage rasterization hardware can be used to efficiently render shaded isosurfaces and to compute diffuse illumination for semi-transparent volume rendering at interactive frame rates.
{"title":"Interactive volume on standard PC graphics hardware using multi-textures and multi-stage rasterization","authors":"C. Rezk-Salama, Klaus Engel, M. Bauer, G. Greiner, T. Ertl","doi":"10.1145/346876.348238","DOIUrl":"https://doi.org/10.1145/346876.348238","url":null,"abstract":"Interactive direct volume rendering has yet been restricted to high-end graphics workstations and special-purpose hardware, due to the large amount of trilinear interpolations, that are necessary to obtain high image quality. Implementations that use the 2D-texture capabilities of standard PC hardware, usually render object-aligned slices in order to substitute trilinear by bilinear interpolation. However the resulting images often contain visual artifacts caused by the lack of spatial interpolation. In this paper we propose new rendering techniques that significantly improve both performance and image quality of the 2D-texture based approach. We will show how in ulti-texturing capabilitiesof modern consumer PC graphboards are exploited to enable in teractive high quality volume visualization on low-cost hardware. Furthermore we demonstrate how multi-stage rasterization hardware can be used to efficiently render shaded isosurfaces and to compute diffuse illumination for semi-transparent volume rendering at interactive frame rates.","PeriodicalId":298241,"journal":{"name":"Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133908540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The power and utility of volume rendering is increased by global illumination. We present a hardware architecture, GI-Cube, designed to accelerate volume rendering, empower volumetric global illumination, and enable a host of ray-based volumetric processing. The algorithm reorders ray processing based on a partitioning of the volume. A cache enables efficient processing of coherent rays within a hardware pipeline. We study the flexibility and performance of this new architecture using both high and low level simulations.
{"title":"GI-cube: an architecture for volumetric global illumination and rendering","authors":"F. Dachille, A. Kaufman","doi":"10.1145/346876.348241","DOIUrl":"https://doi.org/10.1145/346876.348241","url":null,"abstract":"The power and utility of volume rendering is increased by global illumination. We present a hardware architecture, GI-Cube, designed to accelerate volume rendering, empower volumetric global illumination, and enable a host of ray-based volumetric processing. The algorithm reorders ray processing based on a partitioning of the volume. A cache enables efficient processing of coherent rays within a hardware pipeline. We study the flexibility and performance of this new architecture using both high and low level simulations.","PeriodicalId":298241,"journal":{"name":"Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129851873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes a modified A-buffer algorithm and its hardware architecture for single-pass full-screen antialiasing. For storage and management of fragments, a dynamic memory management scheme, which can be efficiently implemented by hardware is introduced. In the fragment resolving stage, a subpixel color-blending scheme that resolves subpixels simultaneously is used to correctly blend transparencies and resolve intersections of polygons in a pixel. A rasterization processor architecture, which can process multiple pixels simultaneously, is also presented. CR
{"title":"Single-pass full-screen hardware accelerated antialiasing","authors":"Jin-Aeon Lee, L. Kim","doi":"10.1145/346876.348225","DOIUrl":"https://doi.org/10.1145/346876.348225","url":null,"abstract":"This paper describes a modified A-buffer algorithm and its hardware architecture for single-pass full-screen antialiasing. For storage and management of fragments, a dynamic memory management scheme, which can be efficiently implemented by hardware is introduced. In the fragment resolving stage, a subpixel color-blending scheme that resolves subpixels simultaneously is used to correctly blend transparencies and resolve intersections of polygons in a pixel. A rasterization processor architecture, which can process multiple pixels simultaneously, is also presented. CR","PeriodicalId":298241,"journal":{"name":"Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121689795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper we present a low-cost memory architecture running at 100 MHz which is suited for any PCI-based volume rendering accelerator using the ray-casting approach. Current SDRAM technology, parallel access to all voxels required for trilinear interpolation, a cubic addressing scheme, and a buffering mechanism accommodating memory latency are applied to achieve high frame-rates. A total of four off-the-shelf standard DIMM modules are required enabling up to 9 Hz (averaged over a representative set of views) for datasets of 256 voxels, using early ray termination as the only algorithmic optimization. The presented memory architecture is a good balance of cost versus feasibility on a standard PCI card accepting data replication and will be used for the VIZARD II ray casting accelerator. CR Categories: B.3.2 [Memory Structures]: Design Style, Associative and Cache Memories; I.3.1 [Computer Graphics]: Hardware Architecture, Graphics Processors; I.3.3 [Computer Graphics]: Picture/Image Generation, Display Algorithms
{"title":"A low-cost memory architecture for PCI-based interactive ray casting","authors":"M. Doggett, M. Meissner, Urs Kanus","doi":"10.1145/311534.311566","DOIUrl":"https://doi.org/10.1145/311534.311566","url":null,"abstract":"In this paper we present a low-cost memory architecture running at 100 MHz which is suited for any PCI-based volume rendering accelerator using the ray-casting approach. Current SDRAM technology, parallel access to all voxels required for trilinear interpolation, a cubic addressing scheme, and a buffering mechanism accommodating memory latency are applied to achieve high frame-rates. A total of four off-the-shelf standard DIMM modules are required enabling up to 9 Hz (averaged over a representative set of views) for datasets of 256 voxels, using early ray termination as the only algorithmic optimization. The presented memory architecture is a good balance of cost versus feasibility on a standard PCI card accepting data replication and will be used for the VIZARD II ray casting accelerator. CR Categories: B.3.2 [Memory Structures]: Design Style, Associative and Cache Memories; I.3.1 [Computer Graphics]: Hardware Architecture, Graphics Processors; I.3.3 [Computer Graphics]: Picture/Image Generation, Display Algorithms","PeriodicalId":298241,"journal":{"name":"Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114887226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We discuss hardware extensions to 3D-texturing units, which are very small but nevertheless remove some substantial performance limits typically found when using a 3D-texturing unit for volume rendering. The underlying algorithm uses only a slight mod$cation of existing method, which limits negative impacts on application software. In particular, the method speeds up the compositing operation, improves texture cache eflciency and allows for early ray termination and empty space skipping. Early ray termination can not be used in the traditional approach. Simulations show that, depending on data set properties, the performance of readily available, low-cost PC graphics accelerators is already suflcient for real-time volume visualization. Thus, in terms ofperformance, the TRIANGLECASTER-extensions can make dedicated volume rendering accelerators unnecessary. CCS
{"title":"TriangleCaster: extensions to 3D-texturing units for accelerated volume rendering","authors":"G. Knittel","doi":"10.1145/311534.311570","DOIUrl":"https://doi.org/10.1145/311534.311570","url":null,"abstract":"We discuss hardware extensions to 3D-texturing units, which are very small but nevertheless remove some substantial performance limits typically found when using a 3D-texturing unit for volume rendering. The underlying algorithm uses only a slight mod$cation of existing method, which limits negative impacts on application software. In particular, the method speeds up the compositing operation, improves texture cache eflciency and allows for early ray termination and empty space skipping. Early ray termination can not be used in the traditional approach. Simulations show that, depending on data set properties, the performance of readily available, low-cost PC graphics accelerators is already suflcient for real-time volume visualization. Thus, in terms ofperformance, the TRIANGLECASTER-extensions can make dedicated volume rendering accelerators unnecessary. CCS","PeriodicalId":298241,"journal":{"name":"Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121057480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Fast Footprint MlPmapping Tobias Hiittner, Wolfgang Strafier WSI/GRIS, University of Tiibingen Mapping textures onto surfaces of computer-generated objects is a technique which greatly improves the realism of their appearance. In this paper, we describe a new method for efficient and fast texture filtering to prevent aliasing during texture mapping. This method, called Fast Footprint MIPmapping, is very flexible and can be adapted to the internal bandwrdth of a graphrcs system. It adopts the prefiltered MIPmap data structure of currently available trilinear MIPmapping implementatrons, but exploits the texels fetched from texture memory in a more optimal manner. Furthermore, like trilinear MIPmapping, fast footprint MIPmapping can easily be realized in hardware. It is sufficient to fetch only eight texels per textured pixel to achieve a significant improvement over classical trilinear MIPmapping. CR Categories: I.3 [1.3.3 Picture/Image Generation]: Antialiasing-Bitmap and framebuffer operationsVrewing algorithms I.3 [1.3.7 Three-Dimensional Graphics and Realism]: Color, shading, shadowing, and texture
Tobias Hiittner, Wolfgang Strafier WSI/GRIS, Tiibingen大学将纹理映射到计算机生成对象的表面上是一种大大提高其外观真实感的技术。本文提出了一种高效快速的纹理滤波方法，以防止纹理映射过程中的混叠现象。这种方法称为快速足迹MIPmapping，非常灵活，可以适应图形系统的内部带宽。它采用了现有的三线性MIPmap实现的预滤波MIPmap数据结构，但以更优的方式利用了从纹理存储器中获取的纹理。此外，与三线性MIPmapping一样，快速占用MIPmapping可以很容易地在硬件上实现。与经典的三线性MIPmapping相比，每个纹理像素仅获取8个纹理就足以实现显著的改进。CR分类:I.3[1.3.3图片/图像生成]:抗锯齿-位图和帧缓冲操作;rewing算法I.3[1.3.7三维图形和现实主义]:颜色，阴影，阴影和纹理
{"title":"Fast footprint MIPmapping","authors":"Tobias Hüttner, W. Straßer","doi":"10.1145/311534.311572","DOIUrl":"https://doi.org/10.1145/311534.311572","url":null,"abstract":"Fast Footprint MlPmapping Tobias Hiittner, Wolfgang Strafier WSI/GRIS, University of Tiibingen Mapping textures onto surfaces of computer-generated objects is a technique which greatly improves the realism of their appearance. In this paper, we describe a new method for efficient and fast texture filtering to prevent aliasing during texture mapping. This method, called Fast Footprint MIPmapping, is very flexible and can be adapted to the internal bandwrdth of a graphrcs system. It adopts the prefiltered MIPmap data structure of currently available trilinear MIPmapping implementatrons, but exploits the texels fetched from texture memory in a more optimal manner. Furthermore, like trilinear MIPmapping, fast footprint MIPmapping can easily be realized in hardware. It is sufficient to fetch only eight texels per textured pixel to achieve a significant improvement over classical trilinear MIPmapping. CR Categories: I.3 [1.3.3 Picture/Image Generation]: Antialiasing-Bitmap and framebuffer operationsVrewing algorithms I.3 [1.3.7 Three-Dimensional Graphics and Realism]: Color, shading, shadowing, and texture","PeriodicalId":298241,"journal":{"name":"Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125105169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hybrid Volume and Polygon Rendering with Cube Hardware Kevin Kreeger and Arie Kaufman* Center for Visual Computing (CVC) and Department of Computer Science State University of New York at Stony Brook Stony Brook, NY 11794-4400 We present two methods which connect today’s polygon graphics hardware accelerators to Cube-5 volume rendering hardware, the successor to Cube4 The proposed methods allow mixing of both opaque and translucent polygons with volumes on PC class machines, while ensuring the correct compositing order of all objects. Both implementations connect the two hardware acceleration subsystems at the frame buffer. One shares a common DRAM buffer and one run-length encodes images of thin slabs of polygonal data and then combines them in the Cube composite buffer In both realizations, we take advantage of the predictable ordered access to frame buffer storage that is utilized by Cube-5 and the rest of the family of volume rendering accelerators based on the Cube design. CR Categories: 1.3.1 [Computer Graphics]: Hardware Architecture-Graphics Processors; 1.3.3 [Computer Graphics]: Picture/Image Generation-Display algorithms; 1.3.7 [Computer Graphics]: Three-Dimensional Graphics and Realism;
{"title":"Hybrid volume and polygon rendering with cube hardware","authors":"K. Kreeger, A. Kaufman","doi":"10.1145/311534.311568","DOIUrl":"https://doi.org/10.1145/311534.311568","url":null,"abstract":"Hybrid Volume and Polygon Rendering with Cube Hardware Kevin Kreeger and Arie Kaufman* Center for Visual Computing (CVC) and Department of Computer Science State University of New York at Stony Brook Stony Brook, NY 11794-4400 We present two methods which connect today’s polygon graphics hardware accelerators to Cube-5 volume rendering hardware, the successor to Cube4 The proposed methods allow mixing of both opaque and translucent polygons with volumes on PC class machines, while ensuring the correct compositing order of all objects. Both implementations connect the two hardware acceleration subsystems at the frame buffer. One shares a common DRAM buffer and one run-length encodes images of thin slabs of polygonal data and then combines them in the Cube composite buffer In both realizations, we take advantage of the predictable ordered access to frame buffer storage that is utilized by Cube-5 and the rest of the family of volume rendering accelerators based on the Cube design. CR Categories: 1.3.1 [Computer Graphics]: Hardware Architecture-Graphics Processors; 1.3.3 [Computer Graphics]: Picture/Image Generation-Display algorithms; 1.3.7 [Computer Graphics]: Three-Dimensional Graphics and Realism;","PeriodicalId":298241,"journal":{"name":"Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125977740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we present for the first time an approach for hardware accelerated displacement mapping. The displaced surface is generated from a 2D displacement map by remeshing a coarse triangle mesh according to the screen projection of the surface. The remeshing algorithm is implemented in hardware. Filtered access to the displacement map makes our approach competitive with available view dependent multiresolution techniques. The advantage of displacement mapping is the compact representation. A displacement mapped surface consumes together with all filter levels only a fraction of the storage space needed for a hardware compatible representation of an equivalent triangle mesh. A possible design of the displacement mapping rendering pipeline is proposed. Previously described hardware components are used as often as possible. Our approach can be smoothly integrated into all available graphics application programming interfaces. Most existing graphics applications can be extended to the new feature with marginal effort. CR Categories: I.3.1 [Computer Graphics]: Hardware Architecture—Raster display devices I.3.3 [Computer Graphics]: Picture/Image Generation—Bitmap and framebuffer operations, Display algorithms, Viewing algorithms I.3.5 [Computer Graphics]: Computational Geometry and Object Modeling—Curve, surface, solid, and object representations I.3.7 [Computer Graphics]: Three-Dimensional Graphics and Realism—Color, shading, shadowing, and texture
{"title":"Multiresolution rendering with displacement mapping","authors":"S. Gumhold, Tobias Hüttner","doi":"10.1145/311534.311578","DOIUrl":"https://doi.org/10.1145/311534.311578","url":null,"abstract":"In this paper, we present for the first time an approach for hardware accelerated displacement mapping. The displaced surface is generated from a 2D displacement map by remeshing a coarse triangle mesh according to the screen projection of the surface. The remeshing algorithm is implemented in hardware. Filtered access to the displacement map makes our approach competitive with available view dependent multiresolution techniques. The advantage of displacement mapping is the compact representation. A displacement mapped surface consumes together with all filter levels only a fraction of the storage space needed for a hardware compatible representation of an equivalent triangle mesh. A possible design of the displacement mapping rendering pipeline is proposed. Previously described hardware components are used as often as possible. Our approach can be smoothly integrated into all available graphics application programming interfaces. Most existing graphics applications can be extended to the new feature with marginal effort. CR Categories: I.3.1 [Computer Graphics]: Hardware Architecture—Raster display devices I.3.3 [Computer Graphics]: Picture/Image Generation—Bitmap and framebuffer operations, Display algorithms, Viewing algorithms I.3.5 [Computer Graphics]: Computational Geometry and Object Modeling—Curve, surface, solid, and object representations I.3.7 [Computer Graphics]: Three-Dimensional Graphics and Realism—Color, shading, shadowing, and texture","PeriodicalId":298241,"journal":{"name":"Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware","volume":"68 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134128207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
3D applications using hardware depth buffers for visibility testing are confronted with multiple choices of buffer types, sizes and formats. Some of the options are not exposed through 3D API or may be used by the driver without application’s knowledge. As a result, it becomes increasingly diffkult to select depth buffer optimal for desired balance between performance and precision. In this paper we provide comparative evaluation of depth precision for main depth buffer types with different size and format combinations. Results indicate that integer storage is preferred for some buffer types, while others achieve maximal depth resolution with floating-point format optimized for known scene parameters. We propose to give 3D applications full control of the depth buffer optimization by supporting multiple storage formats with the same buffer size and exposing them in 3D API. In the search for a unified depth buffer solution, we describe new type of the depth buffer and compare it with other options. Complementary floating-point Z buffer is a combination of a reversed-direction Z buffer and an optimal floating-point storage format. Non-linear mapping and storage format compensate each other’s effect on the depth precision; as a result, depth errors become significantly less dependent on the eye-space distance, improving depth resolution by the orders of magnitude in comparison with standard Z buffer. Results show that complementary Z buffer is also superior to inverse W buffer at any storage size. At 16 and 24 bits/pixel, average depth errors of complementary Z buffer remain 2 times larger than for true W buffer utilizing expensive high-precision per-pixel division. However, it provides absolutely best precision at 32 bits/pixel, when errors are limited by floating-point per-vertex input. Results suggest that complementary floating-point Z buffer can be considered as a candidate for replacement of both screen Z and inverse W buffers, at the same time making hardware investment in the true W buffer support less attractive. CR
{"title":"Optimal depth buffer for low-cost graphics hardware","authors":"Eugene Lapidous, Guofang Jiao","doi":"10.1145/311534.311579","DOIUrl":"https://doi.org/10.1145/311534.311579","url":null,"abstract":"3D applications using hardware depth buffers for visibility testing are confronted with multiple choices of buffer types, sizes and formats. Some of the options are not exposed through 3D API or may be used by the driver without application’s knowledge. As a result, it becomes increasingly diffkult to select depth buffer optimal for desired balance between performance and precision. In this paper we provide comparative evaluation of depth precision for main depth buffer types with different size and format combinations. Results indicate that integer storage is preferred for some buffer types, while others achieve maximal depth resolution with floating-point format optimized for known scene parameters. We propose to give 3D applications full control of the depth buffer optimization by supporting multiple storage formats with the same buffer size and exposing them in 3D API. In the search for a unified depth buffer solution, we describe new type of the depth buffer and compare it with other options. Complementary floating-point Z buffer is a combination of a reversed-direction Z buffer and an optimal floating-point storage format. Non-linear mapping and storage format compensate each other’s effect on the depth precision; as a result, depth errors become significantly less dependent on the eye-space distance, improving depth resolution by the orders of magnitude in comparison with standard Z buffer. Results show that complementary Z buffer is also superior to inverse W buffer at any storage size. At 16 and 24 bits/pixel, average depth errors of complementary Z buffer remain 2 times larger than for true W buffer utilizing expensive high-precision per-pixel division. However, it provides absolutely best precision at 32 bits/pixel, when errors are limited by floating-point per-vertex input. Results suggest that complementary floating-point Z buffer can be considered as a candidate for replacement of both screen Z and inverse W buffers, at the same time making hardware investment in the true W buffer support less attractive. CR","PeriodicalId":298241,"journal":{"name":"Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132943026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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