Functional verification is the most difficult and time-consuming step in VLSI design flow, owing to the complexity and scale of chips rapidly increasing. The key problem of VLSI functional verification is improving the efficiency and coverage. For the important component-Cache in the microprocessors, an FPGA-based pseudo-random functional verification method is proposed in this paper. The test bench of this method is synthesizable, and the field programmable gate array (FPGA) emulation process is integrated to improve the efficiency of verification. The functional verification coverage is increased by automatically generating the constraints directed pseudo-random test stimuli. The method is applied in the real chips, and is compared with the pseudo-random software simulation method. The results show that our method is faster by about three orders of magnitude, and find more bugs in the designs.
{"title":"An FPGA-based Random Functional Verification Method for Cache","authors":"Tiejun Li, Jianmin Zhang, Sikun Li","doi":"10.1109/NAS.2013.44","DOIUrl":"https://doi.org/10.1109/NAS.2013.44","url":null,"abstract":"Functional verification is the most difficult and time-consuming step in VLSI design flow, owing to the complexity and scale of chips rapidly increasing. The key problem of VLSI functional verification is improving the efficiency and coverage. For the important component-Cache in the microprocessors, an FPGA-based pseudo-random functional verification method is proposed in this paper. The test bench of this method is synthesizable, and the field programmable gate array (FPGA) emulation process is integrated to improve the efficiency of verification. The functional verification coverage is increased by automatically generating the constraints directed pseudo-random test stimuli. The method is applied in the real chips, and is compared with the pseudo-random software simulation method. The results show that our method is faster by about three orders of magnitude, and find more bugs in the designs.","PeriodicalId":298759,"journal":{"name":"IEEE International Conference on Networking, Architecture and Storages","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126909368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes a framework for the application of residutaion theory in network calculus. Min-plus convolution and deconvolution composes a dual-residuated pair, their properties can be studied by using residuation theory. End-to-end performance bounds can also be obtained by residuation method. The application of residuation theory in max-plus network calculus theory and time varying network calculus are also studied.
{"title":"Application of Residuation Theory in Network Calculus","authors":"Baohua Fan, He-ying Zhang, Wenhua Dou","doi":"10.1109/NAS.2009.38","DOIUrl":"https://doi.org/10.1109/NAS.2009.38","url":null,"abstract":"This paper proposes a framework for the application of residutaion theory in network calculus. Min-plus convolution and deconvolution composes a dual-residuated pair, their properties can be studied by using residuation theory. End-to-end performance bounds can also be obtained by residuation method. The application of residuation theory in max-plus network calculus theory and time varying network calculus are also studied.","PeriodicalId":298759,"journal":{"name":"IEEE International Conference on Networking, Architecture and Storages","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129911187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Lin Zhou, Fei Liu, Shuitao Gan, Xiaojun Qin, Wenbao Han
Complex interactions and the distributed nature of network software make automated testing and debugging before deployment a necessity. Symbolic execution is a systematic program analysis technique that has become increasingly popular in network software testing, due to algorithmic advances and availability of computational power and constraint solving technology. However, A main challenge is to detect determining symbolic values for program variables related to library, loops and cryptograph algorithms which are widely used in network software. In this paper, we propose a unit symbolic analysis, a hybrid technique that enables fully automatic symbolic analysis even for the traditionally challenging code. The novelties of this work are threefold: 1) we flexibly employs static symbolic execution to amplify the effect of dynamic symbolic execution on demand, 2) dynamic executions and regression analysis are performed on the unit tests constructed from the code segments to infer program semantics needed by static analysis, and 3) symbolic analysis is utilized to tackle loop structure and cryptograph algorithm module. We developed the Net Sym framework, consisting of a static component that performs symbolic analysis and partitions a program, a dynamic analysis that synthesizes unit tests and automatically infers symbolic values for program variables, and a protocol that enables static and dynamic analyses to be run interactively and concurrently. Our experimental results show that by handling cryptograph algorithms, loops and library calls that a traditional symbolic analysis cannot process, unit symbolic analysis detects more vulnerabilities in less time. The technique is scalable for real-world programs such as GHttpd, SQL Server and GDI.
{"title":"Symbolic Execution of Network Software Based on Unit Testing","authors":"Lin Zhou, Fei Liu, Shuitao Gan, Xiaojun Qin, Wenbao Han","doi":"10.1109/NAS.2014.28","DOIUrl":"https://doi.org/10.1109/NAS.2014.28","url":null,"abstract":"Complex interactions and the distributed nature of network software make automated testing and debugging before deployment a necessity. Symbolic execution is a systematic program analysis technique that has become increasingly popular in network software testing, due to algorithmic advances and availability of computational power and constraint solving technology. However, A main challenge is to detect determining symbolic values for program variables related to library, loops and cryptograph algorithms which are widely used in network software. In this paper, we propose a unit symbolic analysis, a hybrid technique that enables fully automatic symbolic analysis even for the traditionally challenging code. The novelties of this work are threefold: 1) we flexibly employs static symbolic execution to amplify the effect of dynamic symbolic execution on demand, 2) dynamic executions and regression analysis are performed on the unit tests constructed from the code segments to infer program semantics needed by static analysis, and 3) symbolic analysis is utilized to tackle loop structure and cryptograph algorithm module. We developed the Net Sym framework, consisting of a static component that performs symbolic analysis and partitions a program, a dynamic analysis that synthesizes unit tests and automatically infers symbolic values for program variables, and a protocol that enables static and dynamic analyses to be run interactively and concurrently. Our experimental results show that by handling cryptograph algorithms, loops and library calls that a traditional symbolic analysis cannot process, unit symbolic analysis detects more vulnerabilities in less time. The technique is scalable for real-world programs such as GHttpd, SQL Server and GDI.","PeriodicalId":298759,"journal":{"name":"IEEE International Conference on Networking, Architecture and Storages","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117116118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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