Due to increasing demand for reconfigurability in embedded systems, real-time task scheduling is challenged by non-negligible reconfiguration overheads. We introduce the problem of real-time task scheduling under reconfiguration overhead on heterogeneous reconfigurable systems while considering the data dependencies and data communication overhead. We introduce a novel graph representation which captures the delay overhead due to data dependencies and reconfiguration. We formulate the problem as a network flow problem and provide a mixed integer linear programming solution to minimize the completion time so called makespan. Results show that our proposed scheduling improves the makespan by 24.20% (on average) in comparison with maximum-transition-overhead scheduling.
{"title":"Reconfiguration-Aware Task Graph Scheduling","authors":"H. Kooti, E. Bozorgzadeh","doi":"10.1109/EUC.2015.33","DOIUrl":"https://doi.org/10.1109/EUC.2015.33","url":null,"abstract":"Due to increasing demand for reconfigurability in embedded systems, real-time task scheduling is challenged by non-negligible reconfiguration overheads. We introduce the problem of real-time task scheduling under reconfiguration overhead on heterogeneous reconfigurable systems while considering the data dependencies and data communication overhead. We introduce a novel graph representation which captures the delay overhead due to data dependencies and reconfiguration. We formulate the problem as a network flow problem and provide a mixed integer linear programming solution to minimize the completion time so called makespan. Results show that our proposed scheduling improves the makespan by 24.20% (on average) in comparison with maximum-transition-overhead scheduling.","PeriodicalId":299207,"journal":{"name":"2015 IEEE 13th International Conference on Embedded and Ubiquitous Computing","volume":"206 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124621689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Very small autonomous robots could cooperate to solve an almost infinite number of problems. Prototypes of such robots do already exist at the micro scale and even smaller ones are expected. Yet allowing them to wirelessly communicate considerably enhance their possible usages. In this paper, we revisit Vouivre, a nano-wireless simulation library we previously developed. Micro or nano-robots will be possibly be numerous and we needed to integrate new ideas to enhance the scalability of Vouivre. Using the specificities of the Terahertz radio channel as a foundation, we discuss and present an implementation that allows simulation of a larger number of concurrent transmissions between an even larger number of individual elements.
{"title":"Scalable Simulation of Wireless Electro-Magnetic Nanonetworks","authors":"Nicolas Boillot, D. Dhoutaut, J. Bourgeois","doi":"10.1109/EUC.2015.38","DOIUrl":"https://doi.org/10.1109/EUC.2015.38","url":null,"abstract":"Very small autonomous robots could cooperate to solve an almost infinite number of problems. Prototypes of such robots do already exist at the micro scale and even smaller ones are expected. Yet allowing them to wirelessly communicate considerably enhance their possible usages. In this paper, we revisit Vouivre, a nano-wireless simulation library we previously developed. Micro or nano-robots will be possibly be numerous and we needed to integrate new ideas to enhance the scalability of Vouivre. Using the specificities of the Terahertz radio channel as a foundation, we discuss and present an implementation that allows simulation of a larger number of concurrent transmissions between an even larger number of individual elements.","PeriodicalId":299207,"journal":{"name":"2015 IEEE 13th International Conference on Embedded and Ubiquitous Computing","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121194366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Heterogeneous computing is a promising approach to tackle the thermal, power and energy constraints posed by modern desktop and embedded computing systems. However, by also allowing the migration of application threads to the most appropriate cores, significant performance gains and energy efficiency levels can also be attained. Nevertheless, the considerably large overheads usually imposed by software-based thread migration procedures only allow exploiting migrations at a coarse-grained level, thus limiting the effectiveness of using such techniques. Accordingly, this paper proposes a fast and efficient hardware-based thread migration mechanism that can be easily plugged-in into any core architecture. To minimize the thread migration overhead and latency, the proposed approach considers both soft-and hard-migration procedures, and adopts a conventional "most recently used" prediction scheme to identify the cache blocks that should be migrated along with the thread context. Experimental results show that the proposed scheme is lightweight and requires limited hardware resources, while allowing to attain migration latencies below 100 clock cycles and to reduce post-migration overheads in up to 60%, making it particularly appropriate for exploiting short-lived application phases.
{"title":"Fast and Scalable Thread Migration for Multi-core Architectures","authors":"Miguel Rodrigues, N. Roma, P. Tomás","doi":"10.1109/EUC.2015.36","DOIUrl":"https://doi.org/10.1109/EUC.2015.36","url":null,"abstract":"Heterogeneous computing is a promising approach to tackle the thermal, power and energy constraints posed by modern desktop and embedded computing systems. However, by also allowing the migration of application threads to the most appropriate cores, significant performance gains and energy efficiency levels can also be attained. Nevertheless, the considerably large overheads usually imposed by software-based thread migration procedures only allow exploiting migrations at a coarse-grained level, thus limiting the effectiveness of using such techniques. Accordingly, this paper proposes a fast and efficient hardware-based thread migration mechanism that can be easily plugged-in into any core architecture. To minimize the thread migration overhead and latency, the proposed approach considers both soft-and hard-migration procedures, and adopts a conventional \"most recently used\" prediction scheme to identify the cache blocks that should be migrated along with the thread context. Experimental results show that the proposed scheme is lightweight and requires limited hardware resources, while allowing to attain migration latencies below 100 clock cycles and to reduce post-migration overheads in up to 60%, making it particularly appropriate for exploiting short-lived application phases.","PeriodicalId":299207,"journal":{"name":"2015 IEEE 13th International Conference on Embedded and Ubiquitous Computing","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129405881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Tanvir Ahmed, N. Sakamoto, J. Anderson, Yuko Hara-Azumi
We describe a lightweight open-source MIPS-ISA processor, wherein performance and area can be flexibly traded-off with one another. The processor contains an ultra-low-cost co-processor capable of executing programs comprised of SUBLEQ instructions (subtract and branch if the difference is ≤ 0), which recent work has shown to be sufficient for any computation. Area/performance trade-offs are realized by implementing a user-selectable subset of MIPS instructions with functionally equivalent SUBLEQ sub-routines that run on the coprocessor. Silicon area is reduced as more MIPS instructions are implemented with the co-processor, rather than "natively" using functional units within the host MIPS. The processor is described in the C language and synthesized to an FPGA hardware implementation with high-level synthesis (HLS). Since it is specified at a high level of abstraction, it is straightforward to tailor to any application. As such, the processor can be viewed as a family of processors with different area/performance/power characteristics. In an experimental study, we compare a variety of processor variants, wherein different subsets of MIPS instructions are handled by the co-processor. We also compare the proposed synthesizable processor with a hand-designed 5-pipeline-stage MIPS implementation, and achieve area reductions ranging from 2.5 - 4×.
{"title":"Synthesizable-from-C Embedded Processor Based on MIPS-ISA and OISC","authors":"Tanvir Ahmed, N. Sakamoto, J. Anderson, Yuko Hara-Azumi","doi":"10.1109/EUC.2015.23","DOIUrl":"https://doi.org/10.1109/EUC.2015.23","url":null,"abstract":"We describe a lightweight open-source MIPS-ISA processor, wherein performance and area can be flexibly traded-off with one another. The processor contains an ultra-low-cost co-processor capable of executing programs comprised of SUBLEQ instructions (subtract and branch if the difference is ≤ 0), which recent work has shown to be sufficient for any computation. Area/performance trade-offs are realized by implementing a user-selectable subset of MIPS instructions with functionally equivalent SUBLEQ sub-routines that run on the coprocessor. Silicon area is reduced as more MIPS instructions are implemented with the co-processor, rather than \"natively\" using functional units within the host MIPS. The processor is described in the C language and synthesized to an FPGA hardware implementation with high-level synthesis (HLS). Since it is specified at a high level of abstraction, it is straightforward to tailor to any application. As such, the processor can be viewed as a family of processors with different area/performance/power characteristics. In an experimental study, we compare a variety of processor variants, wherein different subsets of MIPS instructions are handled by the co-processor. We also compare the proposed synthesizable processor with a hand-designed 5-pipeline-stage MIPS implementation, and achieve area reductions ranging from 2.5 - 4×.","PeriodicalId":299207,"journal":{"name":"2015 IEEE 13th International Conference on Embedded and Ubiquitous Computing","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123112489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
To deal with fail-operational (FO) requirements in today's safety-critical networked embedded systems (SCNES), engineers have to resort to concepts such as redundancy, monitoring, and special shutdown procedures. Hardware-based redundancy approaches are not applicable to many embedded systems domains (e.g., automotive systems), because of prohibitive costs. In this scenario, adaptability concepts can be used to fulfill these FO requirements while enabling optimized resource utilization. However, the applicability of such concepts highly depends on the support for the engineering during system development. We propose an approach to cope with the challenges of fail-operational behavior of SCNES in which engineers are supported by design concepts for realizing safety, reliability, and adaptability requirements through the use of architectural patterns. The approach allows expressing FO concepts at the software architecture level. This lowers the effort for developing SCNES by utilizing generic patterns for general and reoccurring mechanisms.
{"title":"Pattern-Based Approach for Designing Fail-Operational Safety-Critical Embedded Systems","authors":"D. O. D. Penha, Gereon Weiss, Alexander Stante","doi":"10.1109/EUC.2015.14","DOIUrl":"https://doi.org/10.1109/EUC.2015.14","url":null,"abstract":"To deal with fail-operational (FO) requirements in today's safety-critical networked embedded systems (SCNES), engineers have to resort to concepts such as redundancy, monitoring, and special shutdown procedures. Hardware-based redundancy approaches are not applicable to many embedded systems domains (e.g., automotive systems), because of prohibitive costs. In this scenario, adaptability concepts can be used to fulfill these FO requirements while enabling optimized resource utilization. However, the applicability of such concepts highly depends on the support for the engineering during system development. We propose an approach to cope with the challenges of fail-operational behavior of SCNES in which engineers are supported by design concepts for realizing safety, reliability, and adaptability requirements through the use of architectural patterns. The approach allows expressing FO concepts at the software architecture level. This lowers the effort for developing SCNES by utilizing generic patterns for general and reoccurring mechanisms.","PeriodicalId":299207,"journal":{"name":"2015 IEEE 13th International Conference on Embedded and Ubiquitous Computing","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117310300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Embedded System toolchains are highly customized for a specific System-on-Chip (SoC). When the application needs more performance, the designer is typically forced to adopt a new SoC and possibly another toolchain. The rationale for not scaling performance by using, e.g., two SoCs, is that maintining most of the operations on-chip may allow for higher energy efficiency. We are exploring the feasibility and trade-offs of designing and manufacturing a new Single Board Computer (SBC) that could serve flexibly for a number of current and future applications, by allowing scalability through clusters of SBCs while keeping the same programming model for the SBC. This board is based on FPGAs and embedded processors, and its key points are: i) a fast custom interconnect for board-to-board communication and ii) an easily programmable environment which would allow both the off-loading of code into accelerators (either soft-IP blocks or hard-IP blocks) and, at the same time, the distribution of computation across boards. A key challenge to successfully deploying this paradigm is to properly distribute the threads across several boards without the explicit intervention of the programmer. In this paper we describe how to dynamically and efficiently distribute the computational threads in symbiosis with an appropriate memory model to allow the system scalability, so that we can double the performance by simply connecting two boards without i) changing the basic hardware components (e.g., to a different System-On-Chip) and ii) changing the programming model to follow the vendor specific toolchain. Our approach is to reduce data movement across boards. Our initial experiments have confirmed the feasibility of our approach.
{"title":"Scalable Embedded Systems: Towards the Convergence of High-Performance and Embedded Computing","authors":"R. Giorgi","doi":"10.1109/EUC.2015.34","DOIUrl":"https://doi.org/10.1109/EUC.2015.34","url":null,"abstract":"Embedded System toolchains are highly customized for a specific System-on-Chip (SoC). When the application needs more performance, the designer is typically forced to adopt a new SoC and possibly another toolchain. The rationale for not scaling performance by using, e.g., two SoCs, is that maintining most of the operations on-chip may allow for higher energy efficiency. We are exploring the feasibility and trade-offs of designing and manufacturing a new Single Board Computer (SBC) that could serve flexibly for a number of current and future applications, by allowing scalability through clusters of SBCs while keeping the same programming model for the SBC. This board is based on FPGAs and embedded processors, and its key points are: i) a fast custom interconnect for board-to-board communication and ii) an easily programmable environment which would allow both the off-loading of code into accelerators (either soft-IP blocks or hard-IP blocks) and, at the same time, the distribution of computation across boards. A key challenge to successfully deploying this paradigm is to properly distribute the threads across several boards without the explicit intervention of the programmer. In this paper we describe how to dynamically and efficiently distribute the computational threads in symbiosis with an appropriate memory model to allow the system scalability, so that we can double the performance by simply connecting two boards without i) changing the basic hardware components (e.g., to a different System-On-Chip) and ii) changing the programming model to follow the vendor specific toolchain. Our approach is to reduce data movement across boards. Our initial experiments have confirmed the feasibility of our approach.","PeriodicalId":299207,"journal":{"name":"2015 IEEE 13th International Conference on Embedded and Ubiquitous Computing","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128917332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The theoretical background of real-time scheduling has been studied intensively by researchers in this community. A myriad of scheduling policies and sophisticated variations are principally available to be implemented at an operating system level or a middleware level. However, the number of implementations is far behind the number of publications and in the majority of cases they never reach a status beyond prototypes. This is a pitiful situation given that today there is a generation of processor boards waiting for adventurous developers to design and program time-critical embedded applications. The paragon here may be seen in the Raspberry Pi board, but several others also belong to this category (e.g. Cubietruck, Banana Pi). Offering a ready-to-use real-time programming framework is a basic concern of the MARTOP (Mapping real-time to POSIX) project. In order to address a broad range of platforms the approach is independent of a particular operating system only relying on POSIX as intermediate API. As there is another prominent approach to increase the availability of real-time scheduling we are going to compare both with each other. The already prominent one is the EDF-implementation for Linux called SCHED_DEADLINE which is part of the Linux standard kernel since version 3.14. The application scopes of both approaches are completely different. So, MARTOP principally allows any scheduling strategy and several fixed priority scheduling strategies are already available. However, the exciting is that both meet at the EDF-implementation and will be compared not only under the aspect of performance, but equally respecting overhead and robustness.
{"title":"Linux SCHED DEADLINE vs. MARTOP-EDF","authors":"A. Stahlhofen, Dieter Zöbel","doi":"10.1109/EUC.2015.28","DOIUrl":"https://doi.org/10.1109/EUC.2015.28","url":null,"abstract":"The theoretical background of real-time scheduling has been studied intensively by researchers in this community. A myriad of scheduling policies and sophisticated variations are principally available to be implemented at an operating system level or a middleware level. However, the number of implementations is far behind the number of publications and in the majority of cases they never reach a status beyond prototypes. This is a pitiful situation given that today there is a generation of processor boards waiting for adventurous developers to design and program time-critical embedded applications. The paragon here may be seen in the Raspberry Pi board, but several others also belong to this category (e.g. Cubietruck, Banana Pi). Offering a ready-to-use real-time programming framework is a basic concern of the MARTOP (Mapping real-time to POSIX) project. In order to address a broad range of platforms the approach is independent of a particular operating system only relying on POSIX as intermediate API. As there is another prominent approach to increase the availability of real-time scheduling we are going to compare both with each other. The already prominent one is the EDF-implementation for Linux called SCHED_DEADLINE which is part of the Linux standard kernel since version 3.14. The application scopes of both approaches are completely different. So, MARTOP principally allows any scheduling strategy and several fixed priority scheduling strategies are already available. However, the exciting is that both meet at the EDF-implementation and will be compared not only under the aspect of performance, but equally respecting overhead and robustness.","PeriodicalId":299207,"journal":{"name":"2015 IEEE 13th International Conference on Embedded and Ubiquitous Computing","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114888269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sihyeong Park, Hyungshin Kim, Soo-Yeong Kang, Cheol-hea Koo, Hyunwoo Joe
Mission critical embedded software for autonomous operation requires high development cost due to its long development cycle. One of the potential solutions for reducing the cost is to reuse the software developed at previous missions. Virtual machine platform such as JVM is a good example to provide code portability across various missions. Flight software in aerospace field is adopting this concept to improve reusability and eventually to reduce development cost. In this paper, we propose a Lua-based virtualization environment for spacecraft flight software. Flight software for spacecraft control consists of a few tasks that are highly autonomous. Lua is chosen as the script language for programming the control tasks. Though Lua was designed with simplicity and portability, it only supports multithreading with collaborative coroutines. To support preemptive multitasking, we implement time slicing coroutines as spacecraft control processes. New coroutine scheduler is devised and time slicing functionality is added into the scheduler. Scheduler locking and message passing with external flight software are also implemented. Instead of modifying the Lua interpreter, we have exploited the debug support APIs for our implementation. For evaluation, we have implemented the flight software virtualization environment on the flight computer. Accuracy of the time slicing scheduler is also analyzed.
{"title":"Lua-Based Virtual Machine Platform for Spacecraft On-Board Control Software","authors":"Sihyeong Park, Hyungshin Kim, Soo-Yeong Kang, Cheol-hea Koo, Hyunwoo Joe","doi":"10.1109/EUC.2015.21","DOIUrl":"https://doi.org/10.1109/EUC.2015.21","url":null,"abstract":"Mission critical embedded software for autonomous operation requires high development cost due to its long development cycle. One of the potential solutions for reducing the cost is to reuse the software developed at previous missions. Virtual machine platform such as JVM is a good example to provide code portability across various missions. Flight software in aerospace field is adopting this concept to improve reusability and eventually to reduce development cost. In this paper, we propose a Lua-based virtualization environment for spacecraft flight software. Flight software for spacecraft control consists of a few tasks that are highly autonomous. Lua is chosen as the script language for programming the control tasks. Though Lua was designed with simplicity and portability, it only supports multithreading with collaborative coroutines. To support preemptive multitasking, we implement time slicing coroutines as spacecraft control processes. New coroutine scheduler is devised and time slicing functionality is added into the scheduler. Scheduler locking and message passing with external flight software are also implemented. Instead of modifying the Lua interpreter, we have exploited the debug support APIs for our implementation. For evaluation, we have implemented the flight software virtualization environment on the flight computer. Accuracy of the time slicing scheduler is also analyzed.","PeriodicalId":299207,"journal":{"name":"2015 IEEE 13th International Conference on Embedded and Ubiquitous Computing","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125194148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As the web technology advances, web applications, executable on any devices where a web browser is installed, have become pervasive. However, running heavy web applications in the mobile devices is challenging, because of their resource constraints and poor network environments. One of the trials to overcome such restrictions is computation offloading. Computation offloading is the technique migrating computations from client to server to exploit the powerful resources of the server. We observed some former approaches to the computation offloading, and found out they placed a huge burden on programmers to write annotations and substantially limited the computations to be offloaded. In order to overcome these problems, we propose an offloading system transferring the states without annotations and giving programmers freedom to use JavaScript features and DOM (Document Object Model) API in the offloaded computations. Our approach is based on the technique called snapshot, which safely saves and restores the states of web applications. The snapshot-based approach allows the offloaded computations to use various features such as a closure, and DOM API. In the web applications using open source JavaScript libraries, our offloading system successfully offloaded the event handlers using closure variables and DOM APIs, achieving a speedup up to 7.2.
{"title":"Offloading of Web Application Computations: A Snapshot-Based Approach","authors":"H. Jeong, Soo-Mook Moon","doi":"10.1109/EUC.2015.10","DOIUrl":"https://doi.org/10.1109/EUC.2015.10","url":null,"abstract":"As the web technology advances, web applications, executable on any devices where a web browser is installed, have become pervasive. However, running heavy web applications in the mobile devices is challenging, because of their resource constraints and poor network environments. One of the trials to overcome such restrictions is computation offloading. Computation offloading is the technique migrating computations from client to server to exploit the powerful resources of the server. We observed some former approaches to the computation offloading, and found out they placed a huge burden on programmers to write annotations and substantially limited the computations to be offloaded. In order to overcome these problems, we propose an offloading system transferring the states without annotations and giving programmers freedom to use JavaScript features and DOM (Document Object Model) API in the offloaded computations. Our approach is based on the technique called snapshot, which safely saves and restores the states of web applications. The snapshot-based approach allows the offloaded computations to use various features such as a closure, and DOM API. In the web applications using open source JavaScript libraries, our offloading system successfully offloaded the event handlers using closure variables and DOM APIs, achieving a speedup up to 7.2.","PeriodicalId":299207,"journal":{"name":"2015 IEEE 13th International Conference on Embedded and Ubiquitous Computing","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130873940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Filippo Casamassima, M. Magno, Elisabetta Farella, L. Benini
Wireless body area networks (WBANs) have the huge potential to enhance people's lives. They are already present in many application domains, for instance sport and fitness, but they are wide spreading in particular in health and rehabilitation. However, there are still challenging issues that limit their wide diffusion in real life: primarily, the limited lifetime due to the batteries that usually supply the devices. This limitation affects usability and force the data processing to be simple to match the power constraints. This work tries to address the energy limitation by enabling both efficient and complex signal-processing applications and extension of lifetime. We present a power management strategy combining an ultra-low power wake up radio with context awareness. The context aware power manager based on activity recognition decides which nodes must be activated exploiting a nano-power wake up radio and power management policies. Result shows that by using both approaches it is possible to extend battery life of sensor nodes from few hours to an entire week.
{"title":"Context Aware Power Management Enhanced by Radio Wake Up in Body Area Networks","authors":"Filippo Casamassima, M. Magno, Elisabetta Farella, L. Benini","doi":"10.1109/EUC.2015.22","DOIUrl":"https://doi.org/10.1109/EUC.2015.22","url":null,"abstract":"Wireless body area networks (WBANs) have the huge potential to enhance people's lives. They are already present in many application domains, for instance sport and fitness, but they are wide spreading in particular in health and rehabilitation. However, there are still challenging issues that limit their wide diffusion in real life: primarily, the limited lifetime due to the batteries that usually supply the devices. This limitation affects usability and force the data processing to be simple to match the power constraints. This work tries to address the energy limitation by enabling both efficient and complex signal-processing applications and extension of lifetime. We present a power management strategy combining an ultra-low power wake up radio with context awareness. The context aware power manager based on activity recognition decides which nodes must be activated exploiting a nano-power wake up radio and power management policies. Result shows that by using both approaches it is possible to extend battery life of sensor nodes from few hours to an entire week.","PeriodicalId":299207,"journal":{"name":"2015 IEEE 13th International Conference on Embedded and Ubiquitous Computing","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115017165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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