Transactional memories can radically simplify the programming of mixed-criticality systems by offering atomicity, consistency and isolation guarantees between subsystems of different criticality. A major objective in mixed-criticality systems is a modular safety case where each subsystem is certified to the respective safety assurance level. The prerequisite for this modular certification is the prevention of any effect of low criticality subsystems on the temporal behavior of subsystems of higher criticality. This paper introduces a transactional memory architecture based on a time-triggered network-on-a-chip with fault isolation based on a TDMA scheme. The memory architecture contains a memory gateway for selective conflict resolution when committing transactions. The memory gateway triggers a rollback of a transaction in case higher criticality subsystems would be affected. The proposed transactional memory architecture ensures that the validation and certification of high criticality subsystems does not depend on subsystems with lower criticality.
{"title":"A Predictable Transactional Memory Architecture with Selective Conflict Resolution for Mixed-Criticality Support in MPSoCs","authors":"Zaher Owda, R. Obermaisser","doi":"10.1109/EUC.2015.11","DOIUrl":"https://doi.org/10.1109/EUC.2015.11","url":null,"abstract":"Transactional memories can radically simplify the programming of mixed-criticality systems by offering atomicity, consistency and isolation guarantees between subsystems of different criticality. A major objective in mixed-criticality systems is a modular safety case where each subsystem is certified to the respective safety assurance level. The prerequisite for this modular certification is the prevention of any effect of low criticality subsystems on the temporal behavior of subsystems of higher criticality. This paper introduces a transactional memory architecture based on a time-triggered network-on-a-chip with fault isolation based on a TDMA scheme. The memory architecture contains a memory gateway for selective conflict resolution when committing transactions. The memory gateway triggers a rollback of a transaction in case higher criticality subsystems would be affected. The proposed transactional memory architecture ensures that the validation and certification of high criticality subsystems does not depend on subsystems with lower criticality.","PeriodicalId":299207,"journal":{"name":"2015 IEEE 13th International Conference on Embedded and Ubiquitous Computing","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122899539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
I. Christoforakis, Othon Tomoutzoglou, Dimitrios Bakoyiannis, Georgios Kornaros
In this paper, we describe the design of a heterogeneous island-based network-on-chip to achieve a power-and thermal-aware coherent system. To this end we utilize different management techniques which employ dynamic frequency scaling circuitry and continuous monitoring through power and temperature sensors per node for dynamic control of workloads. Both monitoring functions and response mechanisms can be engaged in distributed and in centralized mode. The developed multi-core architecture on a multi-FPGA platform employes a hierarchical memory model and supports a multi-threaded general-purpose processor together with many soft-core accelerators per node with independent dynamic frequency scaling per core. Utilizing on-line monitoring we propose a novel response mechanism using a distributed power management algorithm to evenly reduce and normalize power transients.
{"title":"Dithering-Based Power and Thermal Management on FPGA-Based Multi-core Embedded Systems","authors":"I. Christoforakis, Othon Tomoutzoglou, Dimitrios Bakoyiannis, Georgios Kornaros","doi":"10.1109/EUC.2015.18","DOIUrl":"https://doi.org/10.1109/EUC.2015.18","url":null,"abstract":"In this paper, we describe the design of a heterogeneous island-based network-on-chip to achieve a power-and thermal-aware coherent system. To this end we utilize different management techniques which employ dynamic frequency scaling circuitry and continuous monitoring through power and temperature sensors per node for dynamic control of workloads. Both monitoring functions and response mechanisms can be engaged in distributed and in centralized mode. The developed multi-core architecture on a multi-FPGA platform employes a hierarchical memory model and supports a multi-threaded general-purpose processor together with many soft-core accelerators per node with independent dynamic frequency scaling per core. Utilizing on-line monitoring we propose a novel response mechanism using a distributed power management algorithm to evenly reduce and normalize power transients.","PeriodicalId":299207,"journal":{"name":"2015 IEEE 13th International Conference on Embedded and Ubiquitous Computing","volume":"105 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132902734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Heterogeneous processors, formed by binary compatible CPU cores with different microarchitectures, enable energy reductions by better matching processing capabilities and software application requirements. This new hardware platform requires novel techniques to manage power and energy to fully utilize its capabilities, particularly regarding the mapping of workloads to appropriate cores. In this paper we validate relevant published work related to power modelling for heterogeneous systems and propose a new approach for developing run-time power models that uses a hybrid set of physical predictors, performance events and CPU state information. We demonstrate the accuracy of this approach compared with the state-of-the-art and its applicability to energy aware scheduling. Our results are obtained on a commercially available platform built around the Samsung Exynos 5 Octa SoC, which features the ARM big.LITTLE heterogeneous architecture.
{"title":"Evaluation of Hybrid Run-Time Power Models for the ARM Big.LITTLE Architecture","authors":"Krastin Nikov, J. Núñez-Yáñez, Matthew Horsnell","doi":"10.1109/EUC.2015.32","DOIUrl":"https://doi.org/10.1109/EUC.2015.32","url":null,"abstract":"Heterogeneous processors, formed by binary compatible CPU cores with different microarchitectures, enable energy reductions by better matching processing capabilities and software application requirements. This new hardware platform requires novel techniques to manage power and energy to fully utilize its capabilities, particularly regarding the mapping of workloads to appropriate cores. In this paper we validate relevant published work related to power modelling for heterogeneous systems and propose a new approach for developing run-time power models that uses a hybrid set of physical predictors, performance events and CPU state information. We demonstrate the accuracy of this approach compared with the state-of-the-art and its applicability to energy aware scheduling. Our results are obtained on a commercially available platform built around the Samsung Exynos 5 Octa SoC, which features the ARM big.LITTLE heterogeneous architecture.","PeriodicalId":299207,"journal":{"name":"2015 IEEE 13th International Conference on Embedded and Ubiquitous Computing","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124730513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Englisch, Felix Hänchen, F. Ullmann, Alejandro Masrur, W. Hardt
When integrating AUTOSAR software on an automotive ECU, errors may occur due to the large number of modules involved and/or improper timing. These errors manifest at the application level complicating the test and verification process. Since AUTOSAR has a layered architecture, it is often cumbersome to identify sources of errors. In this paper, to help integrating software on an ECU, we propose a technique to verify functionality and timing of generated AUTOSAR modules in a semi-automated manner. Our technique consists in defining test cases based on the interface descriptions of AUTOSAR modules and application software. This allows reliably identifying AUTOSAR modules affected by functional and/or timing errors and simplifies the test and verification process. We illustrate the benefits by our technique by means of a case study performed on the real hardware.
{"title":"Application-Driven Evaluation of AUTOSAR Basic Software on Modern ECUs","authors":"N. Englisch, Felix Hänchen, F. Ullmann, Alejandro Masrur, W. Hardt","doi":"10.1109/EUC.2015.31","DOIUrl":"https://doi.org/10.1109/EUC.2015.31","url":null,"abstract":"When integrating AUTOSAR software on an automotive ECU, errors may occur due to the large number of modules involved and/or improper timing. These errors manifest at the application level complicating the test and verification process. Since AUTOSAR has a layered architecture, it is often cumbersome to identify sources of errors. In this paper, to help integrating software on an ECU, we propose a technique to verify functionality and timing of generated AUTOSAR modules in a semi-automated manner. Our technique consists in defining test cases based on the interface descriptions of AUTOSAR modules and application software. This allows reliably identifying AUTOSAR modules affected by functional and/or timing errors and simplifies the test and verification process. We illustrate the benefits by our technique by means of a case study performed on the real hardware.","PeriodicalId":299207,"journal":{"name":"2015 IEEE 13th International Conference on Embedded and Ubiquitous Computing","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131954619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
To provide complete vehicle information protection mechanism, this work proposes a self-adaptive system for vehicle information security applications (SAV). Different from the conventional software-based information access method, in the SAV, the access control policies are designed by the protection matrices and implemented as reconfigurable hardware modules. The information access method becomes specific and not generic, so the risks of illegal access of vehicle information can be reduced. To not only meet real-time requirements but also enhance hardware resource utilization, the cryptographic functions in the SAV are also implemented as reconfigurable hardware modules. Thus, the SAV can adapt its access control policies and cryptographic functions at runtime to different system requirements. Our experiments have also demonstrated the SAV can accelerate by up to 3.78x the processing time required by using the software-based design. Compared to the conventional embedded system design, the SAV can also reduce 27.1% of slice registers and 26.5% of slice LUTs in the Xilinx Virtex-5 XC5VLX110T FPGA.
{"title":"A Self-Adaptive System for Vehicle Information Security Applications","authors":"Chun-Hsian Huang, Huang-Yi Chen, T. Huang, Yao-Ying Tzeng, Peng-Yi Li, Peiqiao Wu","doi":"10.1109/EUC.2015.9","DOIUrl":"https://doi.org/10.1109/EUC.2015.9","url":null,"abstract":"To provide complete vehicle information protection mechanism, this work proposes a self-adaptive system for vehicle information security applications (SAV). Different from the conventional software-based information access method, in the SAV, the access control policies are designed by the protection matrices and implemented as reconfigurable hardware modules. The information access method becomes specific and not generic, so the risks of illegal access of vehicle information can be reduced. To not only meet real-time requirements but also enhance hardware resource utilization, the cryptographic functions in the SAV are also implemented as reconfigurable hardware modules. Thus, the SAV can adapt its access control policies and cryptographic functions at runtime to different system requirements. Our experiments have also demonstrated the SAV can accelerate by up to 3.78x the processing time required by using the software-based design. Compared to the conventional embedded system design, the SAV can also reduce 27.1% of slice registers and 26.5% of slice LUTs in the Xilinx Virtex-5 XC5VLX110T FPGA.","PeriodicalId":299207,"journal":{"name":"2015 IEEE 13th International Conference on Embedded and Ubiquitous Computing","volume":"362 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115577481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Modern computing systems are dealing with a diverse set of complex and dynamic workloads in the presence of varying job arrival rates. This diversity is raising the need for the development of sophisticated run-time mechanisms that efficiently manage system's resources. In addition, moving towards kilo-core processor architectures, centralized resource management approaches will most probably form a severe performance bottleneck, thus the study of Distributed Run-Time Resource Management (DRTRM) schemes is now gaining a lot of attention. In this paper, we propose a job-arrival aware DRTRM framework for applications with malleable characteristics, implemented on top of the Intel Single-Chip Cloud Computer (SCC) many-core platform. We show that resource allocation is highly affected not only by the internal decision mechanisms but also from the incoming application interval rate on the system. Based on this observation, we propose an effective admission control strategy utilizing Voltage and Frequency Scaling (VFS) of parts of the DRTRM which eventually retains the distributed decision making thus improving system performance in combination with significant gains in its consumed energy.
{"title":"Job-Arrival Aware Distributed Run-Time Resource Management on Intel SCC Manycore Platform","authors":"Vasileios Tsoutsouras, S. Xydis, D. Soudris","doi":"10.1109/EUC.2015.13","DOIUrl":"https://doi.org/10.1109/EUC.2015.13","url":null,"abstract":"Modern computing systems are dealing with a diverse set of complex and dynamic workloads in the presence of varying job arrival rates. This diversity is raising the need for the development of sophisticated run-time mechanisms that efficiently manage system's resources. In addition, moving towards kilo-core processor architectures, centralized resource management approaches will most probably form a severe performance bottleneck, thus the study of Distributed Run-Time Resource Management (DRTRM) schemes is now gaining a lot of attention. In this paper, we propose a job-arrival aware DRTRM framework for applications with malleable characteristics, implemented on top of the Intel Single-Chip Cloud Computer (SCC) many-core platform. We show that resource allocation is highly affected not only by the internal decision mechanisms but also from the incoming application interval rate on the system. Based on this observation, we propose an effective admission control strategy utilizing Voltage and Frequency Scaling (VFS) of parts of the DRTRM which eventually retains the distributed decision making thus improving system performance in combination with significant gains in its consumed energy.","PeriodicalId":299207,"journal":{"name":"2015 IEEE 13th International Conference on Embedded and Ubiquitous Computing","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129340309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Corna, Andrea Damiani, M. Ferroni, A. A. Nacci, D. Sciuto, M. Santambrogio
In the last decade we have witnessed the birth and dramatic growth of mobile devices, from cellular-to smart-phones. Despite the huge amount of information achievable from an always-connected reality, researchers that work in the mobile devices field fight against the impossibility to explore, inspect and test their work on such a vast set of possible environments, use case scenarios, hardware and software platforms the smart mobile world is composed of. This pushed the need of a wide open dataset of real world data coming from devices in their real usage context, properly anonymized and conveniently organized to be searchable and accessible. In this paper, we present a platform that brings such a dataset to researchers of the next generation of mobile devices.
{"title":"OpenMPower: An Open and Accessible Database About Real World Mobile Devices","authors":"A. Corna, Andrea Damiani, M. Ferroni, A. A. Nacci, D. Sciuto, M. Santambrogio","doi":"10.1109/EUC.2015.16","DOIUrl":"https://doi.org/10.1109/EUC.2015.16","url":null,"abstract":"In the last decade we have witnessed the birth and dramatic growth of mobile devices, from cellular-to smart-phones. Despite the huge amount of information achievable from an always-connected reality, researchers that work in the mobile devices field fight against the impossibility to explore, inspect and test their work on such a vast set of possible environments, use case scenarios, hardware and software platforms the smart mobile world is composed of. This pushed the need of a wide open dataset of real world data coming from devices in their real usage context, properly anonymized and conveniently organized to be searchable and accessible. In this paper, we present a platform that brings such a dataset to researchers of the next generation of mobile devices.","PeriodicalId":299207,"journal":{"name":"2015 IEEE 13th International Conference on Embedded and Ubiquitous Computing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126177363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：