Pub Date : 2004-03-22DOI: 10.1109/ISQED.2004.1283642
J. Chilton
As the old sales adage goes, “Nothing happens until somebody sells something.” For the semiconductor-based electronics industry, the never-ending challenge is to find and sell the next IC-based new “something” (or “somethings”) that consumers just can’t live without. It’s an immense and extremely expensive undertaking to find/create/deliver a killer app, requiring a single-minded, undistracted business focus and an immense amount of creative design innovation. Fortunately, there is a wealth of business-savvy, creative systems companies able to meet that challenge, as long as they are free to concentrate on what drives their core competency: designing and selling exciting new business systems and consumer devices. What they need from their chip manufacturers is an agreement on specs, models, pricing, and delivery. Simple. Fortunately, there are semiconductor firms up to the challenge, as long as they are free to exercise their core mission: designing and selling faster and slicker chips, often now with software and boards attached. They need to focus on taking their customer’s performance specifications and turning out a system on a chip that does exactly those things, on time and on budget. What they need from their EDA vendors are tightly integrated design tools that allow them to meet their goals of performance, price, and predictability. Simple. Unfortunately, these industries don’t reflect this simplified, rosy picture... yet. The hard reality is, however, that they do have to get there, and soon, or live with dwindling prospects for the future. This presentation will discuss strategies for simplifying the semiconductor value chain, thereby enabling each segment to focus on doing well what it does best, for the sake of the future of the entire electronics industry.
{"title":"Simplify: Enable Quality, Enable Innovation","authors":"J. Chilton","doi":"10.1109/ISQED.2004.1283642","DOIUrl":"https://doi.org/10.1109/ISQED.2004.1283642","url":null,"abstract":"As the old sales adage goes, “Nothing happens until somebody sells something.” For the semiconductor-based electronics industry, the never-ending challenge is to find and sell the next IC-based new “something” (or “somethings”) that consumers just can’t live without. It’s an immense and extremely expensive undertaking to find/create/deliver a killer app, requiring a single-minded, undistracted business focus and an immense amount of creative design innovation. Fortunately, there is a wealth of business-savvy, creative systems companies able to meet that challenge, as long as they are free to concentrate on what drives their core competency: designing and selling exciting new business systems and consumer devices. What they need from their chip manufacturers is an agreement on specs, models, pricing, and delivery. Simple. Fortunately, there are semiconductor firms up to the challenge, as long as they are free to exercise their core mission: designing and selling faster and slicker chips, often now with software and boards attached. They need to focus on taking their customer’s performance specifications and turning out a system on a chip that does exactly those things, on time and on budget. What they need from their EDA vendors are tightly integrated design tools that allow them to meet their goals of performance, price, and predictability. Simple. Unfortunately, these industries don’t reflect this simplified, rosy picture... yet. The hard reality is, however, that they do have to get there, and soon, or live with dwindling prospects for the future. This presentation will discuss strategies for simplifying the semiconductor value chain, thereby enabling each segment to focus on doing well what it does best, for the sake of the future of the entire electronics industry.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132054319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-22DOI: 10.1109/ISQED.2004.1283695
K. Saraswat
For over three decades, there has been a quadrupling of transistor density and a doubling of electrical performance every 2 to 3 years. Si transistor technology, in particular CMOS has played a pivotal role in this. It is believed that continued scaling will take the industry down to the 35-nm technology node, at the limit of the ”long-term” range of the International Technology Roadmap for Semiconductors (ITRS). However, it is also well accepted that this long-term range of the 70-nm to 35-nm nodes remains solidly in the “no-known solution” category. The difficulty in scaling the conventional MOSFET makes it prudent to search for alternative device structures. This will require new structural, material and fabrication technology solutions that are generally compatible with current and forecasted installed Semiconductor Manufacturing. In addition, new and revolutionary device concepts need to be discovered and evolved. These can be split into two categories: one is the continued used of silicon FET-type devices but with additional materials, e.g., Ge and innovative structural aspects that deviate from the classical planar/bulk MOSFET, e.g., double gate MOSFET. The second category is a set of potentially entirely different information processing and transmission devices from the transistor as we know it, e.g. silicon-based quantum-effect devices, nano-tube electronics and molecular and organic semiconductor electronics. Continuous scaling of VLSI circuits can pose significant problems for interconnects, especially for those responsible for long distance communication on a high performance chip. Our modeling predicts that the situation is worse than anticipated in the ITRS, which assumes that the resistivity of copper will not change appreciably with scaling in the future. We show that resistance of interconnect wires in light of scaling induced increase in electron surface scattering, fractional cross section area occupied by the high resistivity barrier and realistic interconnect operation temperature will lead to a significant rise in the effective resistivity of Cu. As a result both power and delay of these interconnects is likely to rise significantly in the future. In the light of various metal interconnect limitations, alternate solutions need to be pursued. We focus on two such solutions, optical interconnects and three-dimensional (3-D) ICs with multiplicative Si layers.
{"title":"Performance Limitations of Devices and Interconnects and Possible Alternatives for Nanoelectronics","authors":"K. Saraswat","doi":"10.1109/ISQED.2004.1283695","DOIUrl":"https://doi.org/10.1109/ISQED.2004.1283695","url":null,"abstract":"For over three decades, there has been a quadrupling of transistor density and a doubling of electrical performance every 2 to 3 years. Si transistor technology, in particular CMOS has played a pivotal role in this. It is believed that continued scaling will take the industry down to the 35-nm technology node, at the limit of the ”long-term” range of the International Technology Roadmap for Semiconductors (ITRS). However, it is also well accepted that this long-term range of the 70-nm to 35-nm nodes remains solidly in the “no-known solution” category. The difficulty in scaling the conventional MOSFET makes it prudent to search for alternative device structures. This will require new structural, material and fabrication technology solutions that are generally compatible with current and forecasted installed Semiconductor Manufacturing. In addition, new and revolutionary device concepts need to be discovered and evolved. These can be split into two categories: one is the continued used of silicon FET-type devices but with additional materials, e.g., Ge and innovative structural aspects that deviate from the classical planar/bulk MOSFET, e.g., double gate MOSFET. The second category is a set of potentially entirely different information processing and transmission devices from the transistor as we know it, e.g. silicon-based quantum-effect devices, nano-tube electronics and molecular and organic semiconductor electronics. Continuous scaling of VLSI circuits can pose significant problems for interconnects, especially for those responsible for long distance communication on a high performance chip. Our modeling predicts that the situation is worse than anticipated in the ITRS, which assumes that the resistivity of copper will not change appreciably with scaling in the future. We show that resistance of interconnect wires in light of scaling induced increase in electron surface scattering, fractional cross section area occupied by the high resistivity barrier and realistic interconnect operation temperature will lead to a significant rise in the effective resistivity of Cu. As a result both power and delay of these interconnects is likely to rise significantly in the future. In the light of various metal interconnect limitations, alternate solutions need to be pursued. We focus on two such solutions, optical interconnects and three-dimensional (3-D) ICs with multiplicative Si layers.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114309596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-22DOI: 10.1109/ISQED.2004.1283644
Larry Bock
Nanotechnology is dramatically changing electronics, through the development of nano-enabled systems. These systems incorporate novel nanostructures that integrate functional complexity directly into each individual nanoparticle, enabling the low-cost fabrication of revolutionary high-value, high-performance applications in a broad range of industries from life and physical sciences to information technology and communications to renewable energy to defense. These nanostructures include nanowires, nanorods, nanotetrapods and nanodots formed from all of the industrially important semiconductor materials (Group II-VI, III-V and IV) as their principal active elements. These systems exploit the fundamentally new and unique electronic, optical, magnetic, interface and integration properties associated with materials on the nanometer-scale. The initial applications include exquisitely sensitive chemical and biological sensors, high performance large area macroelectronics and lightweight high efficiency conformal photovoltaics. This talk will describe why now is the right time to focus on nanotechnology and how one company is using these ideas to revolutionize electronics.
{"title":"Why Nano Technology? Why Now? And What Might Its Impact on Electronics","authors":"Larry Bock","doi":"10.1109/ISQED.2004.1283644","DOIUrl":"https://doi.org/10.1109/ISQED.2004.1283644","url":null,"abstract":"Nanotechnology is dramatically changing electronics, through the development of nano-enabled systems. These systems incorporate novel nanostructures that integrate functional complexity directly into each individual nanoparticle, enabling the low-cost fabrication of revolutionary high-value, high-performance applications in a broad range of industries from life and physical sciences to information technology and communications to renewable energy to defense. These nanostructures include nanowires, nanorods, nanotetrapods and nanodots formed from all of the industrially important semiconductor materials (Group II-VI, III-V and IV) as their principal active elements. These systems exploit the fundamentally new and unique electronic, optical, magnetic, interface and integration properties associated with materials on the nanometer-scale. The initial applications include exquisitely sensitive chemical and biological sensors, high performance large area macroelectronics and lightweight high efficiency conformal photovoltaics. This talk will describe why now is the right time to focus on nanotechnology and how one company is using these ideas to revolutionize electronics.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123629413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-22DOI: 10.1109/ISQED.2004.1283694
P. Paulin
Today’s SoC’s combine an increasingly wide range of heterogenous processing elements, consisting of general purpose RISC’s, DSP’s, application-specific processors, and fixed or configurable hardware. Five to ten processors on an SoC is now common. A bottom-up assembly of these heterogeneous components using an ad-hoc interconnect topology, different instruction sets and embedded S/W development tools leads to unmanageable complexity and low quality. This talk will present an approach to effectively integrate heterogenous parallel components – H/W or S/W – into a homogeneous programming environment. This leads to higher quality designs through encapsulation and abstraction. This approach, supported by ST’s MultiFlex multi-processing SoC tools, allows for the combination of a range of heterogeneous processing elements, supported by high-level programming models. Two programming models are supported: a distributed system object component (DSOC) message passing model, and a symmetrical multi-processing (SMP) model using shared memory. We present the results of mapping an Internet traffic management application, running at 2.5Gb/s. We demonstrate the combined use of the MultiFlex multi-processor compilation tools, supported by high-speed hardware-assisted messaging, context-switching and dynamic task allocation in the StepNP platform.
{"title":"Designing High Quality, Scaleable SoC??s with Heterogeneous Components","authors":"P. Paulin","doi":"10.1109/ISQED.2004.1283694","DOIUrl":"https://doi.org/10.1109/ISQED.2004.1283694","url":null,"abstract":"Today’s SoC’s combine an increasingly wide range of heterogenous processing elements, consisting of general purpose RISC’s, DSP’s, application-specific processors, and fixed or configurable hardware. Five to ten processors on an SoC is now common. A bottom-up assembly of these heterogeneous components using an ad-hoc interconnect topology, different instruction sets and embedded S/W development tools leads to unmanageable complexity and low quality. This talk will present an approach to effectively integrate heterogenous parallel components – H/W or S/W – into a homogeneous programming environment. This leads to higher quality designs through encapsulation and abstraction. This approach, supported by ST’s MultiFlex multi-processing SoC tools, allows for the combination of a range of heterogeneous processing elements, supported by high-level programming models. Two programming models are supported: a distributed system object component (DSOC) message passing model, and a symmetrical multi-processing (SMP) model using shared memory. We present the results of mapping an Internet traffic management application, running at 2.5Gb/s. We demonstrate the combined use of the MultiFlex multi-processor compilation tools, supported by high-speed hardware-assisted messaging, context-switching and dynamic task allocation in the StepNP platform.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131930867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-22DOI: 10.1109/ISQED.2004.1283654
D. Venuto
A new solution to improve the testability of high resolution /spl Sigma//spl Delta/ analogue to digital converters (/spl Sigma//spl Delta/ ADCs) using the quantizer input as a test node is described. Both the theory of the method and results from high level simulations for a 16 bit audio ADC example are presented. The analysis demonstrates the potential to reduce the computation overhead associated with test response analysis versus conventional techniques.
{"title":"New Test Access for High Resolution SD ADC's by Using the Noise Transfer Function Evaluation","authors":"D. Venuto","doi":"10.1109/ISQED.2004.1283654","DOIUrl":"https://doi.org/10.1109/ISQED.2004.1283654","url":null,"abstract":"A new solution to improve the testability of high resolution /spl Sigma//spl Delta/ analogue to digital converters (/spl Sigma//spl Delta/ ADCs) using the quantizer input as a test node is described. Both the theory of the method and results from high level simulations for a 16 bit audio ADC example are presented. The analysis demonstrates the potential to reduce the computation overhead associated with test response analysis versus conventional techniques.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122191581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-22DOI: 10.1109/ISQED.2004.10009
T. Maniwa, P. Chatterjee
{"title":"Evening Panel Discussion: DFM PDK's: Where Do They Belong To? Are Process Design Kits (PDKs) the Answer for Modern Design for Manufacturing (DFM) Issues?","authors":"T. Maniwa, P. Chatterjee","doi":"10.1109/ISQED.2004.10009","DOIUrl":"https://doi.org/10.1109/ISQED.2004.10009","url":null,"abstract":"","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127989918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-22DOI: 10.1109/ISQED.2004.1283643
M. Levitt
Today’s nanometer-scale designs are two orders-of-magnitude more complex than designs were in the early 1990s and are commonly manufactured with processes at or below the 130nm feature size. This has brought about a fundamental change in the way design teams must approach the release for their design data to their manufacturing partners. In the past, once a design was taped out and proven to be functional, the responsibility for ramping yield and enhancing the profitability of a design was primarily the responsibility of the manufacturing partner. This is no longer possible at 130nm and below. Once a manufacturing process has stabilized, direct action must be taken by each and every design team to “tune” their design for yield. Design-specific yield enhancement is the new frontier in EDA and while it includes the traditional Design for Manufacturing (DFM) technologies, it also covers much more. Failure to consider yield-degrading effects in IR drop, signal integrity, electro migration, and process variation will result is severe downstream problems in timing closure, functional errors during system bring-up, and the inability to achieve silicon yield and quality targets. In this talk Marc Levitt will discuss what is needed in a new generation design-for-yield tool suite to address the quality of silicon at its source.
{"title":"Design for Manufacturing? Design for Yield!!!","authors":"M. Levitt","doi":"10.1109/ISQED.2004.1283643","DOIUrl":"https://doi.org/10.1109/ISQED.2004.1283643","url":null,"abstract":"Today’s nanometer-scale designs are two orders-of-magnitude more complex than designs were in the early 1990s and are commonly manufactured with processes at or below the 130nm feature size. This has brought about a fundamental change in the way design teams must approach the release for their design data to their manufacturing partners. In the past, once a design was taped out and proven to be functional, the responsibility for ramping yield and enhancing the profitability of a design was primarily the responsibility of the manufacturing partner. This is no longer possible at 130nm and below. Once a manufacturing process has stabilized, direct action must be taken by each and every design team to “tune” their design for yield. Design-specific yield enhancement is the new frontier in EDA and while it includes the traditional Design for Manufacturing (DFM) technologies, it also covers much more. Failure to consider yield-degrading effects in IR drop, signal integrity, electro migration, and process variation will result is severe downstream problems in timing closure, functional errors during system bring-up, and the inability to achieve silicon yield and quality targets. In this talk Marc Levitt will discuss what is needed in a new generation design-for-yield tool suite to address the quality of silicon at its source.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125950605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-01DOI: 10.1109/ISQED.2004.1283693
H. Yasuura
introduced in social infrastructures, which are supporting our daily lives. Since the information technologies have progressed very rapidly, the basic structure of each social infrastructure, which was mostly designed in the 19th or the beginning of 20th centuries with few possibility of information technology, should be redesigned with an assumption of the existence of the advanced information technologies. Based on the high-performance SoCs (System-on-a-Chips) connected by wide-band networks, we can design next generation of social systems, which are directly related with quality of our society including individual rights and national security. In this talk, two social infrastructure information technologies are introduced. Personal Identifier (PID) system is an infrastructure for bidirectional mutual authentication, which will be used for electric commerce and governmental services. An RF-ID tag system is also important technology to implement efficient management of products and economic activities. Using PID and RF-ID tags, we can bridge a gap between the real world and the virtual one on computers automatically. We call the society, in which all persons and goods have their own digital names (identifiers) and are recognizable both in the real and virtual world, Digitally Named World. The systems require advanced technologies of SoC, networking, security and software. Here, technical challenges and social requirements for the new technologies are discussed. Some people are afraid of the infringement of their privacy in the digitally named world. Our discussions also include the technology to protect privacy and individual rights as well as efficiency and stability of our society.
{"title":"Digitally Named World: Challenges for New Social Infrastructures","authors":"H. Yasuura","doi":"10.1109/ISQED.2004.1283693","DOIUrl":"https://doi.org/10.1109/ISQED.2004.1283693","url":null,"abstract":"introduced in social infrastructures, which are supporting our daily lives. Since the information technologies have progressed very rapidly, the basic structure of each social infrastructure, which was mostly designed in the 19th or the beginning of 20th centuries with few possibility of information technology, should be redesigned with an assumption of the existence of the advanced information technologies. Based on the high-performance SoCs (System-on-a-Chips) connected by wide-band networks, we can design next generation of social systems, which are directly related with quality of our society including individual rights and national security. In this talk, two social infrastructure information technologies are introduced. Personal Identifier (PID) system is an infrastructure for bidirectional mutual authentication, which will be used for electric commerce and governmental services. An RF-ID tag system is also important technology to implement efficient management of products and economic activities. Using PID and RF-ID tags, we can bridge a gap between the real world and the virtual one on computers automatically. We call the society, in which all persons and goods have their own digital names (identifiers) and are recognizable both in the real and virtual world, Digitally Named World. The systems require advanced technologies of SoC, networking, security and software. Here, technical challenges and social requirements for the new technologies are discussed. Some people are afraid of the infringement of their privacy in the digitally named world. Our discussions also include the technology to protect privacy and individual rights as well as efficiency and stability of our society.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121579683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-03-24DOI: 10.1109/ISQED.2003.1194730
Chung-Kuan Tsai, M. Marek-Sadowska
The amplitude of coupled noise is often used in estimating the crosstalk effect. Coupling noise-induced delay measures the impact of crosstalk on circuit performance. Efficient computation of worst case noise-induced delays are essential, because such calculations are performed a huge number of times during timing analysis. In this paper we analyze the problem of crosstalk noise-induced delay in one logic stage. We observe that the popular method of crosstalk delay computation based on superposition of the victim's switching waveform and the noise waveform determined when the victim is quiet, produces an underestimation of delay. To capture the crosstalk noise-induced delay, we introduce the concept of dynamic coupling noise waveform. We propose a method of synthesizing the dynamic noise waveform and using it to estimate the delay change.
{"title":"Modeling Crosstalk Induced Delay","authors":"Chung-Kuan Tsai, M. Marek-Sadowska","doi":"10.1109/ISQED.2003.1194730","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194730","url":null,"abstract":"The amplitude of coupled noise is often used in estimating the crosstalk effect. Coupling noise-induced delay measures the impact of crosstalk on circuit performance. Efficient computation of worst case noise-induced delays are essential, because such calculations are performed a huge number of times during timing analysis. In this paper we analyze the problem of crosstalk noise-induced delay in one logic stage. We observe that the popular method of crosstalk delay computation based on superposition of the victim's switching waveform and the noise waveform determined when the victim is quiet, produces an underestimation of delay. To capture the crosstalk noise-induced delay, we introduce the concept of dynamic coupling noise waveform. We propose a method of synthesizing the dynamic noise waveform and using it to estimate the delay change.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132410201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-03-24DOI: 10.1109/ISQED.2003.1194754
Ming-Fu Hsiao, M. Marek-Sadowska, Sao-Jie Chen
Crosstalk noise is a crucial factor affecting chip performance in deep submicron technologies. Among all possible crosstalk noise sources, clock is the most common aggressor as well as victim. Crosstalk on clock nets can increase clock jitter, which may degrade significantly the system performance. Besides, in modern chip designs, there is usually more than one clock net, and some-times even tens of them. It is therefore imperative to design clock topologies to prevent possible crosstalk among them. In this paper, we address the inter-clock crosstalk. We propose algorithms to design clock topology and to perform routing minimizing the effective crosstalk. Our experimental results show a significant reduction of clock jitter compared to the conventional clock tree synthesis which does not take into account the inter-clock crosstalk effects.
{"title":"Minimizing Inter-Clock Coupling Jitter","authors":"Ming-Fu Hsiao, M. Marek-Sadowska, Sao-Jie Chen","doi":"10.1109/ISQED.2003.1194754","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194754","url":null,"abstract":"Crosstalk noise is a crucial factor affecting chip performance in deep submicron technologies. Among all possible crosstalk noise sources, clock is the most common aggressor as well as victim. Crosstalk on clock nets can increase clock jitter, which may degrade significantly the system performance. Besides, in modern chip designs, there is usually more than one clock net, and some-times even tens of them. It is therefore imperative to design clock topologies to prevent possible crosstalk among them. In this paper, we address the inter-clock crosstalk. We propose algorithms to design clock topology and to perform routing minimizing the effective crosstalk. Our experimental results show a significant reduction of clock jitter compared to the conventional clock tree synthesis which does not take into account the inter-clock crosstalk effects.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116613055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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