Pub Date : 2019-10-01DOI: 10.1109/EPEPS47316.2019.193231
B. Silva, Y. F. Shen
A simplified method for quickly characterizing the inductance of power planes, vias, balls, and similar structures is presented. The methodology is centered on characterizing the fundamental building blocks of power distribution networks and using these blocks to discretize geometries without the need for a simulator or computer. A correlation study is performed comparing the method to a full wave simulation and some possible applications are discussed.
{"title":"Intuitive PI: Simulator-less Analysis Methodology","authors":"B. Silva, Y. F. Shen","doi":"10.1109/EPEPS47316.2019.193231","DOIUrl":"https://doi.org/10.1109/EPEPS47316.2019.193231","url":null,"abstract":"A simplified method for quickly characterizing the inductance of power planes, vias, balls, and similar structures is presented. The methodology is centered on characterizing the fundamental building blocks of power distribution networks and using these blocks to discretize geometries without the need for a simulator or computer. A correlation study is performed comparing the method to a full wave simulation and some possible applications are discussed.","PeriodicalId":304228,"journal":{"name":"2019 IEEE 28th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"206 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123061072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/EPEPS47316.2019.193228
A. Manukovsky, Y. Shlepnev
Measured S-parameters and cross-sections of PCB interconnects are used in this paper to identify parameters of electrical models suitable for statistical analysis of interconnects with manufacturing variations. The constructed models reproduce observed effects of geometry and material properties variations on the loss, delay and impedance, and are suitable for yield analysis of interconnects with up to 56 Gbps signals. This is the first attempt to build such models for PCB interconnects.
{"title":"Measurement-assisted extraction of PCB interconnect model parameters with fabrication variations","authors":"A. Manukovsky, Y. Shlepnev","doi":"10.1109/EPEPS47316.2019.193228","DOIUrl":"https://doi.org/10.1109/EPEPS47316.2019.193228","url":null,"abstract":"Measured S-parameters and cross-sections of PCB interconnects are used in this paper to identify parameters of electrical models suitable for statistical analysis of interconnects with manufacturing variations. The constructed models reproduce observed effects of geometry and material properties variations on the loss, delay and impedance, and are suitable for yield analysis of interconnects with up to 56 Gbps signals. This is the first attempt to build such models for PCB interconnects.","PeriodicalId":304228,"journal":{"name":"2019 IEEE 28th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127503094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/EPEPS47316.2019.193211
Daehwan Lho, Junyong Park, Hyunwook Park, Shinyoung Park, Seongguk Kim, Hyungmin Kang, Subin Kim, Gapyeol Park, Kyungjune Son, Joungho Kim
As technology advanced, the demand for data bandwidth has been increasing. To meet this demand, the data rate of the channel has been increased, which causes a lot of signal integrity problems. Optimization of the channel is important to solve these problems. Channels are usually optimized with the empirical knowledge of signal integrity designers. However, it is not accurate and requires numerous iterations. On the other hand, a Bayesian optimization method can quickly find optimized parameter values without relying on empirical knowledge. Therefore, this paper proposes a method for optimizing high-speed channel using Bayesian optimization. The proposed method optimizes the frequency response result such as insertion loss, and find the optimal physical dimension parameters. Finally, the optimized results of the proposed method were verified by comparing all the simulation results in the range of the channel.
{"title":"Bayesian Optimization of High-Speed Channel for Signal Integrity Analysis","authors":"Daehwan Lho, Junyong Park, Hyunwook Park, Shinyoung Park, Seongguk Kim, Hyungmin Kang, Subin Kim, Gapyeol Park, Kyungjune Son, Joungho Kim","doi":"10.1109/EPEPS47316.2019.193211","DOIUrl":"https://doi.org/10.1109/EPEPS47316.2019.193211","url":null,"abstract":"As technology advanced, the demand for data bandwidth has been increasing. To meet this demand, the data rate of the channel has been increased, which causes a lot of signal integrity problems. Optimization of the channel is important to solve these problems. Channels are usually optimized with the empirical knowledge of signal integrity designers. However, it is not accurate and requires numerous iterations. On the other hand, a Bayesian optimization method can quickly find optimized parameter values without relying on empirical knowledge. Therefore, this paper proposes a method for optimizing high-speed channel using Bayesian optimization. The proposed method optimizes the frequency response result such as insertion loss, and find the optimal physical dimension parameters. Finally, the optimized results of the proposed method were verified by comparing all the simulation results in the range of the channel.","PeriodicalId":304228,"journal":{"name":"2019 IEEE 28th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124845777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/EPEPS47316.2019.193235
Y. Uematsu, H. Taniguchi, M. Toyama
As a technology for simulating power-delivery network (PDN) impedance of a system-in-package (SiP) structure, a method that uses a partial-element-equivalent-circuit (PEEC) model—whose mesh size is varied according to the hierarchy of the PDN—is proposed.
{"title":"Analysis of Impedance of Power-delivery Network with SiP Structure by using Hierarchical PEEC","authors":"Y. Uematsu, H. Taniguchi, M. Toyama","doi":"10.1109/EPEPS47316.2019.193235","DOIUrl":"https://doi.org/10.1109/EPEPS47316.2019.193235","url":null,"abstract":"As a technology for simulating power-delivery network (PDN) impedance of a system-in-package (SiP) structure, a method that uses a partial-element-equivalent-circuit (PEEC) model—whose mesh size is varied according to the hierarchy of the PDN—is proposed.","PeriodicalId":304228,"journal":{"name":"2019 IEEE 28th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124932530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/EPEPS47316.2019.193236
Pei-Yang Weng, Chi-Hsuan Cheng, Tzong-Lin Wu, C. Chen, James Chen, E. Kuo, Chun-Lin Liao, B. Mutnury
In high-speed systems, large switching current drawn from power supply seriously degrades the system performance. This paper discloses a signal integrity (SI) issue related to power integrity (PI). A high-speed memory subsystem is used to evaluate the impact of switching current on SI using eye diagrams. Several test cases are studied to clarify the signal susceptibility from the voltage variation of power due to switching current. Full-wave and circuit simulations are used to validate the hypothesis of noise immunity.
{"title":"Improvement of Power and Signal Integrity through Layer Assignment in High-Speed Memory Systems","authors":"Pei-Yang Weng, Chi-Hsuan Cheng, Tzong-Lin Wu, C. Chen, James Chen, E. Kuo, Chun-Lin Liao, B. Mutnury","doi":"10.1109/EPEPS47316.2019.193236","DOIUrl":"https://doi.org/10.1109/EPEPS47316.2019.193236","url":null,"abstract":"In high-speed systems, large switching current drawn from power supply seriously degrades the system performance. This paper discloses a signal integrity (SI) issue related to power integrity (PI). A high-speed memory subsystem is used to evaluate the impact of switching current on SI using eye diagrams. Several test cases are studied to clarify the signal susceptibility from the voltage variation of power due to switching current. Full-wave and circuit simulations are used to validate the hypothesis of noise immunity.","PeriodicalId":304228,"journal":{"name":"2019 IEEE 28th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"107 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114133729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/EPEPS47316.2019.193237
Biancun Xie, Jianyong Xie
The embedded multi-die interconnect bridge (EMIB) is a novel packaging technology that can provide high density interconnects between heterogeneous dies on a single package by embedding a small silicon bridge in the package substrate. This paper investigates the power delivery decoupling schemes for EMIB package for IO to IO communication interfaces, and also compared with EMIB packages for HBM application. The difference between the power delivery decoupling schemes for IO to IO communication interfaces and HBM application has been studied in this paper. A novel approach to implement MIM capacitors in the embedded bridge die which can significantly increase the decoupling capacitance is also proposed.
{"title":"Power Delivery Decoupling Scheme for EMIB Packages","authors":"Biancun Xie, Jianyong Xie","doi":"10.1109/EPEPS47316.2019.193237","DOIUrl":"https://doi.org/10.1109/EPEPS47316.2019.193237","url":null,"abstract":"The embedded multi-die interconnect bridge (EMIB) is a novel packaging technology that can provide high density interconnects between heterogeneous dies on a single package by embedding a small silicon bridge in the package substrate. This paper investigates the power delivery decoupling schemes for EMIB package for IO to IO communication interfaces, and also compared with EMIB packages for HBM application. The difference between the power delivery decoupling schemes for IO to IO communication interfaces and HBM application has been studied in this paper. A novel approach to implement MIM capacitors in the embedded bridge die which can significantly increase the decoupling capacitance is also proposed.","PeriodicalId":304228,"journal":{"name":"2019 IEEE 28th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122200031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/epeps47316.2019.9073373
{"title":"EPEPS 2019 Welcome Message","authors":"","doi":"10.1109/epeps47316.2019.9073373","DOIUrl":"https://doi.org/10.1109/epeps47316.2019.9073373","url":null,"abstract":"","PeriodicalId":304228,"journal":{"name":"2019 IEEE 28th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116611343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/EPEPS47316.2019.193226
Sunil Pathania, Mallikarjun Vasa, B. Mutnury, Rohit Sharma
As signal speeds increase, small imperfections start to dictate the performance of interconnects. Thermal effects are an inseparable aspect of interconnects due to self-heating caused by the flow of current, and due to environmental heating in high speed designs. This paper presents in detail, thermal effects and their impact on insertion loss, crosstalk and phase of high-speed signals. The paper also describes the thermal sensitivity on various aspects of interconnect design such as inter pair spacing, trace height, and dielectric thickness. For our analysis, simulations were performed using field solvers for temperatures ranging from 20°C to 100°C. Finally, results are analyzed with percentage variation in copper loss versus dielectric losses.
{"title":"Thermal Impact on High Speed PCB Interconnects","authors":"Sunil Pathania, Mallikarjun Vasa, B. Mutnury, Rohit Sharma","doi":"10.1109/EPEPS47316.2019.193226","DOIUrl":"https://doi.org/10.1109/EPEPS47316.2019.193226","url":null,"abstract":"As signal speeds increase, small imperfections start to dictate the performance of interconnects. Thermal effects are an inseparable aspect of interconnects due to self-heating caused by the flow of current, and due to environmental heating in high speed designs. This paper presents in detail, thermal effects and their impact on insertion loss, crosstalk and phase of high-speed signals. The paper also describes the thermal sensitivity on various aspects of interconnect design such as inter pair spacing, trace height, and dielectric thickness. For our analysis, simulations were performed using field solvers for temperatures ranging from 20°C to 100°C. Finally, results are analyzed with percentage variation in copper loss versus dielectric losses.","PeriodicalId":304228,"journal":{"name":"2019 IEEE 28th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134503861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/EPEPS47316.2019.9073294
Provides an abstract for each of the tutorial presentations and may include a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings.
{"title":"EPEPS 2019 Tutorials","authors":"","doi":"10.1109/EPEPS47316.2019.9073294","DOIUrl":"https://doi.org/10.1109/EPEPS47316.2019.9073294","url":null,"abstract":"Provides an abstract for each of the tutorial presentations and may include a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings.","PeriodicalId":304228,"journal":{"name":"2019 IEEE 28th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"344 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133911118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/EPEPS47316.2019.193238
Yanyan Zhang, J. Hejase, M. Bohra, P. Paladhi, Lei Shan, S. Chun, J. Audet, W. Becker, D. Dreps
A novel edge card connector design approach with tunable signal integrity (SI) properties is proposed. The tunability is achieved through the presence or absence of a grounded conductive fixture in between the connector pin rows. The main purpose of the tunability is to take an existing connector having a certain impedance intended to work in a high-speed link channel and be able to adjust the impedance of that connector for another channel requiring a different impedance. In this paper, the fixture is designed with a thin metal layer sheet expanding beneath a connector’s pins to provide tunable capacitive coupling between the signal and the ground in order to effectively drop the connector’s impedance from 100ohm to 85ohm. Additionally, it was observed that not only was the impedance tunability achieved for the assumed connector but also improvements in crosstalk and loss potentially extending the operational bandwidth of the connector to higher frequencies. The benefits of the proposed approach are verified by simulations in both frequency-domain and time-domain. A time domain eye simulation of a typical PCIe gen4 SerDes channel designed for 85ohm impedance to work at 16 Gbps shows eye opening improvements of 10.7% and 5.2%, respectively, for the eye height and the eye width when using the tuned connector with the proposed approach.
{"title":"An Approach For Tuning Signal Integrity Properties Of Edge Card Connectors With Conductive Fixture In High-Speed Link Channels","authors":"Yanyan Zhang, J. Hejase, M. Bohra, P. Paladhi, Lei Shan, S. Chun, J. Audet, W. Becker, D. Dreps","doi":"10.1109/EPEPS47316.2019.193238","DOIUrl":"https://doi.org/10.1109/EPEPS47316.2019.193238","url":null,"abstract":"A novel edge card connector design approach with tunable signal integrity (SI) properties is proposed. The tunability is achieved through the presence or absence of a grounded conductive fixture in between the connector pin rows. The main purpose of the tunability is to take an existing connector having a certain impedance intended to work in a high-speed link channel and be able to adjust the impedance of that connector for another channel requiring a different impedance. In this paper, the fixture is designed with a thin metal layer sheet expanding beneath a connector’s pins to provide tunable capacitive coupling between the signal and the ground in order to effectively drop the connector’s impedance from 100ohm to 85ohm. Additionally, it was observed that not only was the impedance tunability achieved for the assumed connector but also improvements in crosstalk and loss potentially extending the operational bandwidth of the connector to higher frequencies. The benefits of the proposed approach are verified by simulations in both frequency-domain and time-domain. A time domain eye simulation of a typical PCIe gen4 SerDes channel designed for 85ohm impedance to work at 16 Gbps shows eye opening improvements of 10.7% and 5.2%, respectively, for the eye height and the eye width when using the tuned connector with the proposed approach.","PeriodicalId":304228,"journal":{"name":"2019 IEEE 28th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131525411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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