Pub Date : 2023-04-05DOI: 10.1109/ISQED57927.2023.10129404
Shalabh Jain, Pradeep Pappachan, J. Guajardo, Sven Trieflinger, Indrasen Raghupatruni, T. Huber
Increasing complexity of systems and software in the automotive industry, coupled with distributed development environments has intensified adoption of Software in the Loop (SIL) systems, i.e. setup where traditional hardware components are designed and tested in pure virtual PC/IT environment consisting of virtualized hardware and networks. Cloud-based SiL simulation systems involving multiple contributors and orchestrators create huge risks for organizations due to potential for leakage of confidential model-IP to adversaries within the distributed infrastructure. This can create a bottleneck for wide-scale adoption of SiL-systems. We propose a data-flow architecture using trusted-computing technologies (e.g. Intel-SGX) to protect models and IP in cloud-based SiL environments. We illustrate that these protections can be designed to be compatible with existing SiL tools and workflows with minimal modifications. Further, we highlight the need for future standardization efforts of such security architectures in the SiL domain.
{"title":"CMP-SiL: Confidential Multi Party Software-in-the-Loop Simulation Frameworks","authors":"Shalabh Jain, Pradeep Pappachan, J. Guajardo, Sven Trieflinger, Indrasen Raghupatruni, T. Huber","doi":"10.1109/ISQED57927.2023.10129404","DOIUrl":"https://doi.org/10.1109/ISQED57927.2023.10129404","url":null,"abstract":"Increasing complexity of systems and software in the automotive industry, coupled with distributed development environments has intensified adoption of Software in the Loop (SIL) systems, i.e. setup where traditional hardware components are designed and tested in pure virtual PC/IT environment consisting of virtualized hardware and networks. Cloud-based SiL simulation systems involving multiple contributors and orchestrators create huge risks for organizations due to potential for leakage of confidential model-IP to adversaries within the distributed infrastructure. This can create a bottleneck for wide-scale adoption of SiL-systems. We propose a data-flow architecture using trusted-computing technologies (e.g. Intel-SGX) to protect models and IP in cloud-based SiL environments. We illustrate that these protections can be designed to be compatible with existing SiL tools and workflows with minimal modifications. Further, we highlight the need for future standardization efforts of such security architectures in the SiL domain.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128559613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-05DOI: 10.1109/ISQED57927.2023.10129354
Zhe Gao, Sheqin Dong, Zhicong Tang, Wenjian Yu
Ordered escape routing (OER) is an important research topic in PCB design, which means the wires need to be routed in a given order at the boundary of pin array. Although OER has been widely investigated, most works assume the routing capacity between two adjacent pins is just 1. In this paper, we focus on multi-capacity OER (MC-OER), which means multiple wires are allowed to pass through between two adjacent pins. We first analyze the limitation of existing model based on min-cost multi-commodity flow graph, i.e. MMCF model, and point out the reason why it cannot support multi-capacity. Based on the MMCF model, a multi-capacity multi-commodity flow (MC-MCF) model is proposed for the MC-OER problem. To accelerate the solution based on MC-MCF model, a wiring resource driven partition strategy is further proposed which results in an accelerated MC-MCF algorithm for the MC-OER problem with objective of minimizing wiring length. Experiments on various grid pin array cases (with up to 308 pins) show that the proposed method achieves 100% routability within reasonable time. And, it performs similarly well or better than existing methods when solving single-capacity OER problem.
{"title":"MC-MCF: A Multi-Capacity Model for Ordered Escape Routing","authors":"Zhe Gao, Sheqin Dong, Zhicong Tang, Wenjian Yu","doi":"10.1109/ISQED57927.2023.10129354","DOIUrl":"https://doi.org/10.1109/ISQED57927.2023.10129354","url":null,"abstract":"Ordered escape routing (OER) is an important research topic in PCB design, which means the wires need to be routed in a given order at the boundary of pin array. Although OER has been widely investigated, most works assume the routing capacity between two adjacent pins is just 1. In this paper, we focus on multi-capacity OER (MC-OER), which means multiple wires are allowed to pass through between two adjacent pins. We first analyze the limitation of existing model based on min-cost multi-commodity flow graph, i.e. MMCF model, and point out the reason why it cannot support multi-capacity. Based on the MMCF model, a multi-capacity multi-commodity flow (MC-MCF) model is proposed for the MC-OER problem. To accelerate the solution based on MC-MCF model, a wiring resource driven partition strategy is further proposed which results in an accelerated MC-MCF algorithm for the MC-OER problem with objective of minimizing wiring length. Experiments on various grid pin array cases (with up to 308 pins) show that the proposed method achieves 100% routability within reasonable time. And, it performs similarly well or better than existing methods when solving single-capacity OER problem.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132406465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-05DOI: 10.1109/ISQED57927.2023.10129376
Bindu G. Gowda, C. PrashanthH., M. Rao
Introducing approximation has shown significant benefits in the performance and throughput, besides lowering on-chip power consumption and silicon footprint requirement. Approximation in digital computing was designed and targeted towards error-resilient applications primarily involving image or signal processing modules. Previous works focus on approximating various arithmetic operator designs, including dividers, multipliers, adders, subtractors and multiply-and-accumulate units. Approximating compressor designs for multipliers was found to improve performance, power and area effectively. In addition, they offer regularity in cascading the partial product bits. Conventional multiplier designs employ compressors of the same kind throughout the partial product reduction stages, leading to the accumulation of errors. This paper proposes to utilize two different types of compressors: positive and negative compressors, subsequently in partial product reduction stages, with the intention to reduce the accumulated error. The proposed multiplier designs with appropriately placed positive and negative compressors along the stages and columns of the Partial Product Matrix (PPM) are investigated and characterized for hardware and error metrics. These designs were further evaluated for Image smoothing and Convolutional Neural Network (CNN) applications. The CNN built for four datasets using proposed approximate multipliers demonstrated comparable accuracy to that of exact multiplier-based CNN in the Lenet-5 architecture.
{"title":"Error Diluted Approximate Multipliers Using Positive And Negative Compressors","authors":"Bindu G. Gowda, C. PrashanthH., M. Rao","doi":"10.1109/ISQED57927.2023.10129376","DOIUrl":"https://doi.org/10.1109/ISQED57927.2023.10129376","url":null,"abstract":"Introducing approximation has shown significant benefits in the performance and throughput, besides lowering on-chip power consumption and silicon footprint requirement. Approximation in digital computing was designed and targeted towards error-resilient applications primarily involving image or signal processing modules. Previous works focus on approximating various arithmetic operator designs, including dividers, multipliers, adders, subtractors and multiply-and-accumulate units. Approximating compressor designs for multipliers was found to improve performance, power and area effectively. In addition, they offer regularity in cascading the partial product bits. Conventional multiplier designs employ compressors of the same kind throughout the partial product reduction stages, leading to the accumulation of errors. This paper proposes to utilize two different types of compressors: positive and negative compressors, subsequently in partial product reduction stages, with the intention to reduce the accumulated error. The proposed multiplier designs with appropriately placed positive and negative compressors along the stages and columns of the Partial Product Matrix (PPM) are investigated and characterized for hardware and error metrics. These designs were further evaluated for Image smoothing and Convolutional Neural Network (CNN) applications. The CNN built for four datasets using proposed approximate multipliers demonstrated comparable accuracy to that of exact multiplier-based CNN in the Lenet-5 architecture.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"107 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130508089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-05DOI: 10.1109/ISQED57927.2023.10129304
Sourav Roy, Shahin Tajik, Domenic Forte
Laser Logic State Imaging (LLSI) is a failure analysis (FA) technique which is conducted from the chip backside. LLSI provides an unlimited number of contactless probes to observe static signals, such as security critical assets, which in the hand of an attacker poses a significant threat. Countermeasures that have been proposed so far to prevent backside optical attacks have limitations, such as additional fabrication steps, large area overhead, incompatibility with digital circuits, which makes their implementation challenging. In this paper, we propose all-digital polymorphic gate sensors for the first time in hardware security to detect LLSI attacks. Polymorphic gates change their behavior depending on environmental conditions, e.g., variations in supply voltage and temperature. Freezing the system clock and modulation of supply voltage are the main requirements of mounting an LLSI attack. With these two attack requirements in mind, we design and simulate a polymorphic gate-based sensor that behaves as a NOR gate when there is no supply voltage modulation and switches behavior between NAND gate and NOR gate in the presence of modulation. The sensor is able to detect LLSI attacks 100% of the time at room temperature even considering manufacturing variation and with a detection rate of more than98% for a temperature range of 0°C to 85°C.
{"title":"Polymorphic Sensor to Detect Laser Logic State Imaging Attack","authors":"Sourav Roy, Shahin Tajik, Domenic Forte","doi":"10.1109/ISQED57927.2023.10129304","DOIUrl":"https://doi.org/10.1109/ISQED57927.2023.10129304","url":null,"abstract":"Laser Logic State Imaging (LLSI) is a failure analysis (FA) technique which is conducted from the chip backside. LLSI provides an unlimited number of contactless probes to observe static signals, such as security critical assets, which in the hand of an attacker poses a significant threat. Countermeasures that have been proposed so far to prevent backside optical attacks have limitations, such as additional fabrication steps, large area overhead, incompatibility with digital circuits, which makes their implementation challenging. In this paper, we propose all-digital polymorphic gate sensors for the first time in hardware security to detect LLSI attacks. Polymorphic gates change their behavior depending on environmental conditions, e.g., variations in supply voltage and temperature. Freezing the system clock and modulation of supply voltage are the main requirements of mounting an LLSI attack. With these two attack requirements in mind, we design and simulate a polymorphic gate-based sensor that behaves as a NOR gate when there is no supply voltage modulation and switches behavior between NAND gate and NOR gate in the presence of modulation. The sensor is able to detect LLSI attacks 100% of the time at room temperature even considering manufacturing variation and with a detection rate of more than98% for a temperature range of 0°C to 85°C.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128977145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-05DOI: 10.1109/ISQED57927.2023.10129370
Mayank Kabra, C. PrashanthH., Kedar Deshpande, M. Rao
In-memory and near-memory computing allows for placing the processing elements around the periphery or inside the memory blocks. Performing the computation as soon as the data is made available in the memory sub-blocks avoids the need to wait for the processor to manage the data movement. The paper focuses on a new 11 transistor (11T) computing design and a novel operation with energy savings and performance improvement when compared to the current state-of-the-art (SOTA) available single-instruction- multiple-data in-DRAM (SIMDRAM) computing. The novel 11T pass transistor design is structured to offer logical AND, OR, XNOR and its complement operations. These are sequenced to generate desired operational output with a minuscule change of 4 row circuitry that corresponds to footprint expense of 0.05% when compared to the existing DRAM architecture. Based on these logical operations, 13 scalar instructions covering arithmetic, predication, reduction, and relational function types are characterized. These scalar operations is a mix of logarithmic, quadratic, and linear functions applied on either a single or multiple operand. With respect to single-instruction- multiple-data (SIMD) topology, vector operations comprising addition, multiplication, sparse multiplication, selection, unique, reduction, and prefix summation are also realized. All these operations were compared with the current SOTA SIMDRAM architectural design to showcase profound computing time benefits and energy savings. The proposed 11T in-DRAM-compute design offers 5.18% to 50.57% improvement in computing latency and energy across 10 scalar operations, over SIMDRAM architecture. The novel high performance and efficient in-DRAM computing (HIE-DRAM) implementation is a step towards utilizing real-time in-memory vector data processing for autonomous applications.
{"title":"HIE-DRAM: High Performance Efficient In-DRAM Computing Architecture for SIMD","authors":"Mayank Kabra, C. PrashanthH., Kedar Deshpande, M. Rao","doi":"10.1109/ISQED57927.2023.10129370","DOIUrl":"https://doi.org/10.1109/ISQED57927.2023.10129370","url":null,"abstract":"In-memory and near-memory computing allows for placing the processing elements around the periphery or inside the memory blocks. Performing the computation as soon as the data is made available in the memory sub-blocks avoids the need to wait for the processor to manage the data movement. The paper focuses on a new 11 transistor (11T) computing design and a novel operation with energy savings and performance improvement when compared to the current state-of-the-art (SOTA) available single-instruction- multiple-data in-DRAM (SIMDRAM) computing. The novel 11T pass transistor design is structured to offer logical AND, OR, XNOR and its complement operations. These are sequenced to generate desired operational output with a minuscule change of 4 row circuitry that corresponds to footprint expense of 0.05% when compared to the existing DRAM architecture. Based on these logical operations, 13 scalar instructions covering arithmetic, predication, reduction, and relational function types are characterized. These scalar operations is a mix of logarithmic, quadratic, and linear functions applied on either a single or multiple operand. With respect to single-instruction- multiple-data (SIMD) topology, vector operations comprising addition, multiplication, sparse multiplication, selection, unique, reduction, and prefix summation are also realized. All these operations were compared with the current SOTA SIMDRAM architectural design to showcase profound computing time benefits and energy savings. The proposed 11T in-DRAM-compute design offers 5.18% to 50.57% improvement in computing latency and energy across 10 scalar operations, over SIMDRAM architecture. The novel high performance and efficient in-DRAM computing (HIE-DRAM) implementation is a step towards utilizing real-time in-memory vector data processing for autonomous applications.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115502419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-05DOI: 10.1109/ISQED57927.2023.10129293
Kwondo Ma, C. Amarnath, A. Chatterjee, Jacob A. Abraham
There has been increased interest in detection of adversarial security attacks on control functions of autonomous systems. In this research, we propose the use of low-cost state space checks for detection of security attacks on sensors, actuators and control software of autonomous systems. These attacks are assumed to be initiated by intrusions, malware, or embedded hardware Trojans. Checks consist of predicting sensor (actuator) values from prior values of actuators (sensors) and external control inputs. The associated nonlinear predictors are learned in real time using Gaussian Process regressors (GPs). Recovery from sensor and actuator attacks is performed by sensor-actuator data restoration. Recovery from control software attacks is performed by reverting to a lightweight linearized controller that prevents short-term catastrophic system malfunction. Experimental results on a brake-by-wire, steer-by-wire system, and a traveling robot (hardware) prove the viability of the proposed approach.
{"title":"Secure Control Loop Execution of Cyber-Physical Devices Using Predictive State Space Checks","authors":"Kwondo Ma, C. Amarnath, A. Chatterjee, Jacob A. Abraham","doi":"10.1109/ISQED57927.2023.10129293","DOIUrl":"https://doi.org/10.1109/ISQED57927.2023.10129293","url":null,"abstract":"There has been increased interest in detection of adversarial security attacks on control functions of autonomous systems. In this research, we propose the use of low-cost state space checks for detection of security attacks on sensors, actuators and control software of autonomous systems. These attacks are assumed to be initiated by intrusions, malware, or embedded hardware Trojans. Checks consist of predicting sensor (actuator) values from prior values of actuators (sensors) and external control inputs. The associated nonlinear predictors are learned in real time using Gaussian Process regressors (GPs). Recovery from sensor and actuator attacks is performed by sensor-actuator data restoration. Recovery from control software attacks is performed by reverting to a lightweight linearized controller that prevents short-term catastrophic system malfunction. Experimental results on a brake-by-wire, steer-by-wire system, and a traveling robot (hardware) prove the viability of the proposed approach.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125331203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-05DOI: 10.1109/ISQED57927.2023.10129368
Jordan Maynard, Amin Rezaei
The semiconductor industry must deal with different hardware threats like piracy and overproduction as a result of outsourcing manufacturing. While there are many proposals to lock the circuit using a global protected key only known to the designer, there exist numerous oracle-guided attacks that can examine the locked netlist with the assistance of an activated IC and extract the correct key. In this paper, by adopting a low-overhead structural method, we propose DK Lock, a novel Dual Key locking method that securely protects sequential circuits with two different keys that are applied to one set of key inputs at different times. DK Lock structurally adds an activation phase to the sequential circuit, and a correct key must be applied for several cycles to exit this phase. Once the circuit has been successfully activated, a new functional key must be applied to the same set of inputs to resume normal operation. DK Lock opens up new avenues for hardware IP protection by simultaneously refuting the single static key assumption of the existing attacks and overcoming the state explosion problem of state-of-the-art sequential logic locking methods. Our experiments confirm that DK Lock maintains a high degree of security with reasonable power and area overheads.
{"title":"DK Lock: Dual Key Logic Locking Against Oracle-Guided Attacks","authors":"Jordan Maynard, Amin Rezaei","doi":"10.1109/ISQED57927.2023.10129368","DOIUrl":"https://doi.org/10.1109/ISQED57927.2023.10129368","url":null,"abstract":"The semiconductor industry must deal with different hardware threats like piracy and overproduction as a result of outsourcing manufacturing. While there are many proposals to lock the circuit using a global protected key only known to the designer, there exist numerous oracle-guided attacks that can examine the locked netlist with the assistance of an activated IC and extract the correct key. In this paper, by adopting a low-overhead structural method, we propose DK Lock, a novel Dual Key locking method that securely protects sequential circuits with two different keys that are applied to one set of key inputs at different times. DK Lock structurally adds an activation phase to the sequential circuit, and a correct key must be applied for several cycles to exit this phase. Once the circuit has been successfully activated, a new functional key must be applied to the same set of inputs to resume normal operation. DK Lock opens up new avenues for hardware IP protection by simultaneously refuting the single static key assumption of the existing attacks and overcoming the state explosion problem of state-of-the-art sequential logic locking methods. Our experiments confirm that DK Lock maintains a high degree of security with reasonable power and area overheads.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125874097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-05DOI: 10.1109/ISQED57927.2023.10129327
Dhanasekar V, Vinodhini Gunasekaran, Anusha Challa, Bama Srinivasan, J. D. Devi, Selvi Ravindran, R. Parthasarathi, P. Ramakrishna, Gopika Geetha Kumar, Venkateswaran Padmanabhan, G. Lakshmanan, Lakshmanan Balasubramanian
Pre-silicon analog and mixed signal (AMS) design verification involves exorbitant computing and manual effort and time to verify the design against the specification of an IC. This paper proposes a Machine Learning (ML) based behavioural model to predict the output response of AMS circuits that can be used in the automated verification process including automation of waveform review sign-off, and fast simulation models. The ML based behaviour model is constructed using the time domain features. To address both linear and non-linear behaviours of the circuit, this paper proposes a framework with statistical processing, waveform segmentation and circuit partitioning approaches as a divide and conquer strategy to identify the appropriate suite of ML algorithms. The best performing ML models in each segment are concatenated to stitch the complete response. We also propose SNR as a metric to evaluate the prediction accuracy. An Operational Amplifier (OpAmp) benchmark circuit has been used as a proof of concept to demonstrate this approach. An average SNR of 32 dB has been obtained in the prediction of the output waveform.
{"title":"Analysis of Machine Learning Techniques for Time Domain Waveform Prediction in Analog and Mixed Signal Integrated Circuit Verification","authors":"Dhanasekar V, Vinodhini Gunasekaran, Anusha Challa, Bama Srinivasan, J. D. Devi, Selvi Ravindran, R. Parthasarathi, P. Ramakrishna, Gopika Geetha Kumar, Venkateswaran Padmanabhan, G. Lakshmanan, Lakshmanan Balasubramanian","doi":"10.1109/ISQED57927.2023.10129327","DOIUrl":"https://doi.org/10.1109/ISQED57927.2023.10129327","url":null,"abstract":"Pre-silicon analog and mixed signal (AMS) design verification involves exorbitant computing and manual effort and time to verify the design against the specification of an IC. This paper proposes a Machine Learning (ML) based behavioural model to predict the output response of AMS circuits that can be used in the automated verification process including automation of waveform review sign-off, and fast simulation models. The ML based behaviour model is constructed using the time domain features. To address both linear and non-linear behaviours of the circuit, this paper proposes a framework with statistical processing, waveform segmentation and circuit partitioning approaches as a divide and conquer strategy to identify the appropriate suite of ML algorithms. The best performing ML models in each segment are concatenated to stitch the complete response. We also propose SNR as a metric to evaluate the prediction accuracy. An Operational Amplifier (OpAmp) benchmark circuit has been used as a proof of concept to demonstrate this approach. An average SNR of 32 dB has been obtained in the prediction of the output waveform.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121665287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-05DOI: 10.1109/ISQED57927.2023.10129378
Rakibul Hassan, Charan Bandi, Meng-Tien Tsai, Shahriar Golchin, Sai Manoj P D, S. Rafatirad, Soheil Salehi
The number of publicly known cyber-security vulnerabilities (CVEs) submitted to the National Vulnerability Database (NVD) has increased significantly due to the increasing complexity of modern computing systems. The NVD database is a remarkable source of the latest reported vulnerable information for Cyber-Physical-System. However, it is cumbersome to extract useful information from this large corpus of unstructured data to find meaningful trends over time without the proper tools. Prior works with this purpose have mainly focused on software vulnerabilities and failed to provide a storytelling framework that can extract useful information about the relationship and trends within the CVE and Common Weakness Enumeration (CWE) databases over time. Additionally, hardware attacks on IoT devices are evolving rapidly due to the recent proliferation of computing devices in mobile and IoT domains. In this work, we present a Machine Learning-based framework for vulnerability and its impact vector classification focusing on the hardware vulnerabilities in the IoT domain. Our proposed framework is equipped with an Ontology-driven Storytelling Framework (OSF) and updates the ontology in an automated fashion, aiming to identify similar patterns of vulnerabilities over time. This helps to mitigate the impacts of vulnerabilities or, from another perspective, predicts and prevents future exposures.
{"title":"Automated Supervised Topic Modeling Framework for Hardware Weaknesses","authors":"Rakibul Hassan, Charan Bandi, Meng-Tien Tsai, Shahriar Golchin, Sai Manoj P D, S. Rafatirad, Soheil Salehi","doi":"10.1109/ISQED57927.2023.10129378","DOIUrl":"https://doi.org/10.1109/ISQED57927.2023.10129378","url":null,"abstract":"The number of publicly known cyber-security vulnerabilities (CVEs) submitted to the National Vulnerability Database (NVD) has increased significantly due to the increasing complexity of modern computing systems. The NVD database is a remarkable source of the latest reported vulnerable information for Cyber-Physical-System. However, it is cumbersome to extract useful information from this large corpus of unstructured data to find meaningful trends over time without the proper tools. Prior works with this purpose have mainly focused on software vulnerabilities and failed to provide a storytelling framework that can extract useful information about the relationship and trends within the CVE and Common Weakness Enumeration (CWE) databases over time. Additionally, hardware attacks on IoT devices are evolving rapidly due to the recent proliferation of computing devices in mobile and IoT domains. In this work, we present a Machine Learning-based framework for vulnerability and its impact vector classification focusing on the hardware vulnerabilities in the IoT domain. Our proposed framework is equipped with an Ontology-driven Storytelling Framework (OSF) and updates the ontology in an automated fashion, aiming to identify similar patterns of vulnerabilities over time. This helps to mitigate the impacts of vulnerabilities or, from another perspective, predicts and prevents future exposures.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131472916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-05DOI: 10.1109/ISQED57927.2023.10129314
Shamiul Alam, Kazi Asifuzzaman, A. Aziz
The dream of achieving a universal memory that can provide robust non-volatile memory states along with low-energy operation has been the key driving force of memory research. Despite dominating the memory market, conventional charge-based memories cannot satisfy these requirements. However, UltraRAM, an oxide-free charge-based memory cell, aims to achieve both of these requirements. This device achieves non-volatility (with an endurance of over 107 cycles and a retention of over 1000 years) along with switching at low-voltage (±2.3 V) utilizing a triple-barrier resonant tunneling (TBRT) structure made of InAs/AlSb. In this work, we propose an array design for UltraRAM-based memory devices. Our proposed memory array features separate read-write path and eliminates the possibility of accidentally switching the memory states stored in the array. Moreover, our design allows us to read all the cells in a column in one cycle without imposing any limit on the scalability. Besides, since the read operation in our proposed design is independent of the write mechanism, there is flexibility to optimize the read operation for memory and in-memory computing applications.
{"title":"A Novel Scalable Array Design for III-V Compound Semiconductor-based Nonvolatile Memory (UltraRAM) with Separate Read-Write Paths","authors":"Shamiul Alam, Kazi Asifuzzaman, A. Aziz","doi":"10.1109/ISQED57927.2023.10129314","DOIUrl":"https://doi.org/10.1109/ISQED57927.2023.10129314","url":null,"abstract":"The dream of achieving a universal memory that can provide robust non-volatile memory states along with low-energy operation has been the key driving force of memory research. Despite dominating the memory market, conventional charge-based memories cannot satisfy these requirements. However, UltraRAM, an oxide-free charge-based memory cell, aims to achieve both of these requirements. This device achieves non-volatility (with an endurance of over 107 cycles and a retention of over 1000 years) along with switching at low-voltage (±2.3 V) utilizing a triple-barrier resonant tunneling (TBRT) structure made of InAs/AlSb. In this work, we propose an array design for UltraRAM-based memory devices. Our proposed memory array features separate read-write path and eliminates the possibility of accidentally switching the memory states stored in the array. Moreover, our design allows us to read all the cells in a column in one cycle without imposing any limit on the scalability. Besides, since the read operation in our proposed design is independent of the write mechanism, there is flexibility to optimize the read operation for memory and in-memory computing applications.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131378887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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