Pub Date : 2023-04-05DOI: 10.1109/ISQED57927.2023.10129350
A. Kahng, Shreyas Thumathy, M. Woo
In global routing of relatively large nets, particularly clock subnets, obtaining a good cost-skew tradeoff has remained beyond the reach of efficient heuristics. This is in contrast to obtaining a good cost-radius tradeoff, which has been well-addressed by a series of methods. We propose a simple heuristic for optimizing the cost-skew tradeoff, based on a "multi-source" variation of the well-known Prim-Dijkstra (PD) construction [1]. Our experiments demonstrate the effectiveness of the multi-source PD heuristic compared to existing alternatives including H-tree [5], bounded-skew DME [10], and original Prim-Dijkstra constructions. We additionally develop characterization data for PD with respect to instance parameters to aid future research.
{"title":"An Effective Cost-Skew Tradeoff Heuristic for VLSI Global Routing","authors":"A. Kahng, Shreyas Thumathy, M. Woo","doi":"10.1109/ISQED57927.2023.10129350","DOIUrl":"https://doi.org/10.1109/ISQED57927.2023.10129350","url":null,"abstract":"In global routing of relatively large nets, particularly clock subnets, obtaining a good cost-skew tradeoff has remained beyond the reach of efficient heuristics. This is in contrast to obtaining a good cost-radius tradeoff, which has been well-addressed by a series of methods. We propose a simple heuristic for optimizing the cost-skew tradeoff, based on a \"multi-source\" variation of the well-known Prim-Dijkstra (PD) construction [1]. Our experiments demonstrate the effectiveness of the multi-source PD heuristic compared to existing alternatives including H-tree [5], bounded-skew DME [10], and original Prim-Dijkstra constructions. We additionally develop characterization data for PD with respect to instance parameters to aid future research.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"365 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116320132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-05DOI: 10.1109/ISQED57927.2023.10129337
Ece Nur Demirhan Coskun, Muhammad Hassan, Mehran Goli, R. Drechsler
Ubiquitousness of modern feature-rich heterogeneous systems has significantly increased their security requirements. One weak point of entry might spread catastrophically over large areas, blocking the accessibility of different Intellectual Properties (IPs), and thereby disabling the system’s functionality. Hence, it becomes vital to consider the trust and security implications during the design phase of these heterogeneous systems and identify possible security breaches due to the system design itself. Recently, various security validation methods have been successfully employed very early in the design phase at the system level using Virtual Prototypes (VPs). These methods have facilitated the investigation of digital systems with a focus on data leakage and untrusted access. However, modern systems are heterogeneous with heavy reliance on sensor inputs. Hence, similar security validation methods should also be considered from the analog/mixed-signal (AMS) perspective using SystemC AMS, to ensure availability security properties.In this paper, we propose VAST, a novel validation tool for VP-based heterogeneous systems against availability security properties. VAST employs static Information Flow Tracking (IFT) at the system-level to ensure the availability, i.e. timely accessibility, of IPs. In this regard, VAST analyzes analog-to-digital, digital-to-analog, as well as digital-to-digital behaviors of the underlying heterogeneous system. We demonstrate the applicability and scalability of the proposed tool on two real-world VPs with different sizes of complexity, a car anti-trap window system, and a thermal house system.
{"title":"VAST: Validation of VP-based Heterogeneous Systems against Availability Security Properties using Static Information Flow Tracking","authors":"Ece Nur Demirhan Coskun, Muhammad Hassan, Mehran Goli, R. Drechsler","doi":"10.1109/ISQED57927.2023.10129337","DOIUrl":"https://doi.org/10.1109/ISQED57927.2023.10129337","url":null,"abstract":"Ubiquitousness of modern feature-rich heterogeneous systems has significantly increased their security requirements. One weak point of entry might spread catastrophically over large areas, blocking the accessibility of different Intellectual Properties (IPs), and thereby disabling the system’s functionality. Hence, it becomes vital to consider the trust and security implications during the design phase of these heterogeneous systems and identify possible security breaches due to the system design itself. Recently, various security validation methods have been successfully employed very early in the design phase at the system level using Virtual Prototypes (VPs). These methods have facilitated the investigation of digital systems with a focus on data leakage and untrusted access. However, modern systems are heterogeneous with heavy reliance on sensor inputs. Hence, similar security validation methods should also be considered from the analog/mixed-signal (AMS) perspective using SystemC AMS, to ensure availability security properties.In this paper, we propose VAST, a novel validation tool for VP-based heterogeneous systems against availability security properties. VAST employs static Information Flow Tracking (IFT) at the system-level to ensure the availability, i.e. timely accessibility, of IPs. In this regard, VAST analyzes analog-to-digital, digital-to-analog, as well as digital-to-digital behaviors of the underlying heterogeneous system. We demonstrate the applicability and scalability of the proposed tool on two real-world VPs with different sizes of complexity, a car anti-trap window system, and a thermal house system.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"385 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121780928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-05DOI: 10.1109/ISQED57927.2023.10129334
Garret Cunningham, H. Chenji, D. Juedes, Gordon Stewart, Avinash Karanth
Without the isolation abstractions of operating systems, low-level embedded systems are especially vulnerable to attacks that exploit flaws in either software or hardware to gain control of program behavior. Runtime monitors at the hardware level have shown promise towards by identifying malicious instructions and enforcing programmer-defined policy at runtime. However, the efficiency of monitors comes at the cost of ease of implementation, as policies for ensuring the safe execution of software must be defined at the hardware level. To bridge the abstraction gap, high-level security policy languages have been defined with the ability to be synthesized into hardware monitors, but are limited by semantics that only define policies whose behavior remains static throughout a program’s execution, which limits the practical use case.In this paper, we enable dynamically reconfigurable security policies through a high-level language named DAGGER. Alongside static policies, DAGGER’s semantics support policies that dynamically change behavior in response to expert-defined conditions at runtime. Additionally, we introduce a Verilog compiler to support realizing policies as hardware monitors. DAGGERis developed using the Coq proof assistant, enabling the formal verification of policy correctness and other properties. This approach takes advantage of the abstractions and expressiveness of a higher-level language while minimizing the overhead that comes with other general-purpose approaches implemented purely in hardware, as well as offering the groundwork for a formally verified tool chain.
{"title":"DAGGER: Exploiting Language Semantics for Program Security in Embedded Systems","authors":"Garret Cunningham, H. Chenji, D. Juedes, Gordon Stewart, Avinash Karanth","doi":"10.1109/ISQED57927.2023.10129334","DOIUrl":"https://doi.org/10.1109/ISQED57927.2023.10129334","url":null,"abstract":"Without the isolation abstractions of operating systems, low-level embedded systems are especially vulnerable to attacks that exploit flaws in either software or hardware to gain control of program behavior. Runtime monitors at the hardware level have shown promise towards by identifying malicious instructions and enforcing programmer-defined policy at runtime. However, the efficiency of monitors comes at the cost of ease of implementation, as policies for ensuring the safe execution of software must be defined at the hardware level. To bridge the abstraction gap, high-level security policy languages have been defined with the ability to be synthesized into hardware monitors, but are limited by semantics that only define policies whose behavior remains static throughout a program’s execution, which limits the practical use case.In this paper, we enable dynamically reconfigurable security policies through a high-level language named DAGGER. Alongside static policies, DAGGER’s semantics support policies that dynamically change behavior in response to expert-defined conditions at runtime. Additionally, we introduce a Verilog compiler to support realizing policies as hardware monitors. DAGGERis developed using the Coq proof assistant, enabling the formal verification of policy correctness and other properties. This approach takes advantage of the abstractions and expressiveness of a higher-level language while minimizing the overhead that comes with other general-purpose approaches implemented purely in hardware, as well as offering the groundwork for a formally verified tool chain.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116339121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-05DOI: 10.1109/ISQED57927.2023.10129366
Yuan Wang, Jian Xin, Haixu Liu, Qian Qin, Chenkai Chai, Yukai Lu, Jinglei Hao, Jianhao Xiao, Zuochang Ye, Yan Wang
Both in academia and industry, a series of design methodologies based on evolutionary algorithms or machine learning techniques have been proposed to solve the problem of analog device sizing. However, these methods typically need a large number of circuit simulations during the optimization process and these simulations significantly increase the learning and computational costs. To tackle this problem, in this work, we propose DC-Model, a DC simulation-based neural network model that can greatly reduce the whole simulation time while being applied in the field of analog circuit optimization. DC-Model is inspired by the relationship between MOSFET dc operating point output parameters and circuit performances.
{"title":"DC-Model: A New Method for Assisting the Analog Circuit Optimization","authors":"Yuan Wang, Jian Xin, Haixu Liu, Qian Qin, Chenkai Chai, Yukai Lu, Jinglei Hao, Jianhao Xiao, Zuochang Ye, Yan Wang","doi":"10.1109/ISQED57927.2023.10129366","DOIUrl":"https://doi.org/10.1109/ISQED57927.2023.10129366","url":null,"abstract":"Both in academia and industry, a series of design methodologies based on evolutionary algorithms or machine learning techniques have been proposed to solve the problem of analog device sizing. However, these methods typically need a large number of circuit simulations during the optimization process and these simulations significantly increase the learning and computational costs. To tackle this problem, in this work, we propose DC-Model, a DC simulation-based neural network model that can greatly reduce the whole simulation time while being applied in the field of analog circuit optimization. DC-Model is inspired by the relationship between MOSFET dc operating point output parameters and circuit performances.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114468989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-05DOI: 10.1109/ISQED57927.2023.10129349
Wei Zhou, Aijiao Cui, Cassi Chen, Gang Qu
Scan-based side-channel attacks have become a severe threat to the security of cryptographic chips and locking mechanisms are one of the most effective methods against these attacks. However, securing the test key that locks the scan but must be shared among test engineers arises as a new challenge. In this paper, we solve this challenge by adopting the physical unclonable function (PUF) design to generate test keys that are unique for each chip. A one-time programming structure (OTPS) is used when the PUF response is first generated to improve its reliability. The security of the PUF response is achieved by obfuscation such that it can be retrieved only when a specific validation test vector presents. We implement the proposed secure scan design by reusing the original scan chain to reduce overhead. We demonstrate that the proposed secure scan design can protect the crypto chips against all existing scan-based side-channel attacks while incurring negligibly low overhead.
{"title":"A Low-overhead PUF-based Secure Scan Design","authors":"Wei Zhou, Aijiao Cui, Cassi Chen, Gang Qu","doi":"10.1109/ISQED57927.2023.10129349","DOIUrl":"https://doi.org/10.1109/ISQED57927.2023.10129349","url":null,"abstract":"Scan-based side-channel attacks have become a severe threat to the security of cryptographic chips and locking mechanisms are one of the most effective methods against these attacks. However, securing the test key that locks the scan but must be shared among test engineers arises as a new challenge. In this paper, we solve this challenge by adopting the physical unclonable function (PUF) design to generate test keys that are unique for each chip. A one-time programming structure (OTPS) is used when the PUF response is first generated to improve its reliability. The security of the PUF response is achieved by obfuscation such that it can be retrieved only when a specific validation test vector presents. We implement the proposed secure scan design by reusing the original scan chain to reduce overhead. We demonstrate that the proposed secure scan design can protect the crypto chips against all existing scan-based side-channel attacks while incurring negligibly low overhead.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128837728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-05DOI: 10.1109/ISQED57927.2023.10129315
Nishant Bharti, Arijit Nath, Swati Upadhyay, H. Kapoor
Emerging Non-Volatile memories (NVM) offer immense possibilities to be considered as an alternative to DRAM in the main memory. However, adoption of NVMs in the memory hierarchy faces challenges due to their costly writes and poor write endurance. In this connection, developing policies to improve the endurance of NVMs has paramount importance. This paper presents a low overhead scheme based on compression and encoding to improve the lifetime of PCM-based main memory. We propose a compression technique by removing chains of zero-valued data bits that are prevalent in the cache blocks coming to PCM. On top of it, we encode the compressed blocks at finer encoding granularity, utilizing only a few tag bits. The overall procedure, called ZOCHEN improves PCM lifetime by reducing bit-flips in the PCM cells. We get a substantial reduction in bit-flips and improvement in lifetime compared to baseline and state-of-the-art policies.
{"title":"ZOCHEN: Compression Using Zero Chain Elimination and Encoding to Improve Endurance of Non-Volatile Memories","authors":"Nishant Bharti, Arijit Nath, Swati Upadhyay, H. Kapoor","doi":"10.1109/ISQED57927.2023.10129315","DOIUrl":"https://doi.org/10.1109/ISQED57927.2023.10129315","url":null,"abstract":"Emerging Non-Volatile memories (NVM) offer immense possibilities to be considered as an alternative to DRAM in the main memory. However, adoption of NVMs in the memory hierarchy faces challenges due to their costly writes and poor write endurance. In this connection, developing policies to improve the endurance of NVMs has paramount importance. This paper presents a low overhead scheme based on compression and encoding to improve the lifetime of PCM-based main memory. We propose a compression technique by removing chains of zero-valued data bits that are prevalent in the cache blocks coming to PCM. On top of it, we encode the compressed blocks at finer encoding granularity, utilizing only a few tag bits. The overall procedure, called ZOCHEN improves PCM lifetime by reducing bit-flips in the PCM cells. We get a substantial reduction in bit-flips and improvement in lifetime compared to baseline and state-of-the-art policies.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122191663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-05DOI: 10.1109/ISQED57927.2023.10129398
Tasnuva Farheen, Shahin Tajik, Domenic Forte
Computing systems’ hardware implementation is vulnerable to physical attacks. One of the most powerful tools in the arsenal of physical attacks is laser fault injection (LFI), which can successfully compromise an embedded cryptographic implementation even with a single fault. Several countermeasures have been proposed to prevent and detect LFI attacks. However, these schemes cannot protect a multi-spot laser fault injection setup alone. Vulnerabilities can be addressed in such circumstances using a multi-layer or defense-in-depth approach. Defense-in-depth refers to implementing several independent countermeasures within a device to provide aggregated protection against various attack vectors. In this paper, we introduce a multi-layer countermeasure where the proposed approach protects an LFI attack detector against multi-spot LFI attacks. We design and simulate a spatially distributed multi-gate driven design, called SPRED, to prevent single and multi-spot LFI attacks. Simulation results show that the distribution of gates in SPRED forces an attacker to use higher laser power and a thinner wafer to inject a fault.
{"title":"SPRED: Spatially Distributed Laser Fault Injection Resilient Design","authors":"Tasnuva Farheen, Shahin Tajik, Domenic Forte","doi":"10.1109/ISQED57927.2023.10129398","DOIUrl":"https://doi.org/10.1109/ISQED57927.2023.10129398","url":null,"abstract":"Computing systems’ hardware implementation is vulnerable to physical attacks. One of the most powerful tools in the arsenal of physical attacks is laser fault injection (LFI), which can successfully compromise an embedded cryptographic implementation even with a single fault. Several countermeasures have been proposed to prevent and detect LFI attacks. However, these schemes cannot protect a multi-spot laser fault injection setup alone. Vulnerabilities can be addressed in such circumstances using a multi-layer or defense-in-depth approach. Defense-in-depth refers to implementing several independent countermeasures within a device to provide aggregated protection against various attack vectors. In this paper, we introduce a multi-layer countermeasure where the proposed approach protects an LFI attack detector against multi-spot LFI attacks. We design and simulate a spatially distributed multi-gate driven design, called SPRED, to prevent single and multi-spot LFI attacks. Simulation results show that the distribution of gates in SPRED forces an attacker to use higher laser power and a thinner wafer to inject a fault.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"293 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115022904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-05DOI: 10.1109/ISQED57927.2023.10129306
Shiya Liu, Y. Yi
Building accurate and efficient deep neural network (DNN) models for intelligent sensing systems to process data locally is essential. Spiking neural networks (SNNs) have gained significant popularity in recent years because they are more biological-plausible and energy-efficient than DNNs. However, SNNs usually have lower accuracy than DNNs. In this paper, we propose to use SNNs for image sensing applications. Moreover, we introduce the DNN-SNN knowledge distillation algorithm to reduce the accuracy gap between DNNs and SNNs. Our DNNSNN knowledge distillation improves the accuracy of an SNN by transferring knowledge between a DNN and an SNN. To better transfer the knowledge, our algorithm creates two learning paths from a DNN to an SNN. One path is between the output layer and another path is between the intermediate layer. DNNs use real numbers to propagate information between neurons while SNNs use 1-bit spikes. To empower the communication between DNNs and SNNs, we utilize a decoder to decode spikes into real numbers. Also, our algorithm creates a learning path from an SNN to a DNN. This learning path better adapts the DNN to the SNN by allowing the DNN to learn the knowledge from the SNN. Our SNN models are deployed on Loihi, which is a specialized chip for SNN models. On the MNIST dataset, our SNN models trained by the DNN-SNN knowledge distillation achieve better accuracy than the SNN models on GPU trained by other training algorithms with much lower energy consumption per image.
{"title":"Knowledge Distillation between DNN and SNN for Intelligent Sensing Systems on Loihi Chip","authors":"Shiya Liu, Y. Yi","doi":"10.1109/ISQED57927.2023.10129306","DOIUrl":"https://doi.org/10.1109/ISQED57927.2023.10129306","url":null,"abstract":"Building accurate and efficient deep neural network (DNN) models for intelligent sensing systems to process data locally is essential. Spiking neural networks (SNNs) have gained significant popularity in recent years because they are more biological-plausible and energy-efficient than DNNs. However, SNNs usually have lower accuracy than DNNs. In this paper, we propose to use SNNs for image sensing applications. Moreover, we introduce the DNN-SNN knowledge distillation algorithm to reduce the accuracy gap between DNNs and SNNs. Our DNNSNN knowledge distillation improves the accuracy of an SNN by transferring knowledge between a DNN and an SNN. To better transfer the knowledge, our algorithm creates two learning paths from a DNN to an SNN. One path is between the output layer and another path is between the intermediate layer. DNNs use real numbers to propagate information between neurons while SNNs use 1-bit spikes. To empower the communication between DNNs and SNNs, we utilize a decoder to decode spikes into real numbers. Also, our algorithm creates a learning path from an SNN to a DNN. This learning path better adapts the DNN to the SNN by allowing the DNN to learn the knowledge from the SNN. Our SNN models are deployed on Loihi, which is a specialized chip for SNN models. On the MNIST dataset, our SNN models trained by the DNN-SNN knowledge distillation achieve better accuracy than the SNN models on GPU trained by other training algorithms with much lower energy consumption per image.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"341 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115888481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-05DOI: 10.1109/ISQED57927.2023.10129296
Vishesh Mishra, Sparsh Mittal, Rekha Singhal, M. Nambiar
By exploiting the gap between the user’s accuracy requirement and the hardware’s accuracy capability, approximate circuit design offers enormous gains in efficiency for a minor accuracy loss. In this paper, we propose two approximate floating point multipliers (AxFPMs), named DTCL (decomposition, truncation and chunk-level leading-one quantization) and TDIL (truncation, decomposition and ignoring LSBs). Both AxFPMs introduce approximation in mantissa multiplication. DTCL works by rounding and truncating LSBs and quantizing each chunk. TDIL works by truncating LSBs and ignoring the least important terms in the multiplication. Further, both techniques multiply more significant terms by simply exponent addition or shift-and-add operations. These AxFPMs are configurable and allow trading off accuracy with hardware overhead. Compared to exact floating-point multiplier (FPM), DTCL(4,8,8) reduces area, energy and delay by 11.0%, 69% and 61%, respectively, while incurring a mean relative error of only 2.37%. On a range of approximate applications from machine learning, deep learning and image processing domains, our AxFPMs greatly improve efficiency with only minor loss in accuracy. For example, for image sharpening and Gaussian smoothing, all DTCL and TDIL variants achieve a PSNR of more than 30dB. The source-code is available at https://github.com/CandleLabAI/ApproxFloatingPointMultiplier.
{"title":"Novel, Configurable Approximate Floating-point Multipliers for Error-Resilient Applications","authors":"Vishesh Mishra, Sparsh Mittal, Rekha Singhal, M. Nambiar","doi":"10.1109/ISQED57927.2023.10129296","DOIUrl":"https://doi.org/10.1109/ISQED57927.2023.10129296","url":null,"abstract":"By exploiting the gap between the user’s accuracy requirement and the hardware’s accuracy capability, approximate circuit design offers enormous gains in efficiency for a minor accuracy loss. In this paper, we propose two approximate floating point multipliers (AxFPMs), named DTCL (decomposition, truncation and chunk-level leading-one quantization) and TDIL (truncation, decomposition and ignoring LSBs). Both AxFPMs introduce approximation in mantissa multiplication. DTCL works by rounding and truncating LSBs and quantizing each chunk. TDIL works by truncating LSBs and ignoring the least important terms in the multiplication. Further, both techniques multiply more significant terms by simply exponent addition or shift-and-add operations. These AxFPMs are configurable and allow trading off accuracy with hardware overhead. Compared to exact floating-point multiplier (FPM), DTCL(4,8,8) reduces area, energy and delay by 11.0%, 69% and 61%, respectively, while incurring a mean relative error of only 2.37%. On a range of approximate applications from machine learning, deep learning and image processing domains, our AxFPMs greatly improve efficiency with only minor loss in accuracy. For example, for image sharpening and Gaussian smoothing, all DTCL and TDIL variants achieve a PSNR of more than 30dB. The source-code is available at https://github.com/CandleLabAI/ApproxFloatingPointMultiplier.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125648148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-05DOI: 10.1109/isqed57927.2023.10129386
{"title":"Welcome to ISQED 2023","authors":"","doi":"10.1109/isqed57927.2023.10129386","DOIUrl":"https://doi.org/10.1109/isqed57927.2023.10129386","url":null,"abstract":"","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129220422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：