Pub Date : 1995-08-07DOI: 10.1109/MTDT.1995.518092
B. Cockburn
Describes four new test algorithms that detect different classes of physical neighborhood pattern-sensitive faults (PNPSFs) in n/spl times/1 random-access memories (RAMs). All four tests assume that the storage cells are arranged in a rectangular grid. The first two tests assume further that the mapping from logical cell addresses to physical cell locations is known, whereas the second two tests allow the row and column addresses for the square grid to be separately scrambled in any arbitrary way unknown to the tester. The first test has length (97 /sup 5///sub 9/)n and detects all single active PNPSFs. The second test has length 121 /sup 5///sub 9/ and detects all single active, static and passive PNPSFs. The third test has a length of approximately 8.0n(log/sub 2/n)/sup 2/ and detects all single scrambled active PNPSFs. The fourth test has a length of roughly 8.4n(log/sub 2/n)/sup 2.322/ and detects all single scrambled active, static and passive PNPSFs.
{"title":"Deterministic tests for detecting scrambled pattern-sensitive faults in RAMs","authors":"B. Cockburn","doi":"10.1109/MTDT.1995.518092","DOIUrl":"https://doi.org/10.1109/MTDT.1995.518092","url":null,"abstract":"Describes four new test algorithms that detect different classes of physical neighborhood pattern-sensitive faults (PNPSFs) in n/spl times/1 random-access memories (RAMs). All four tests assume that the storage cells are arranged in a rectangular grid. The first two tests assume further that the mapping from logical cell addresses to physical cell locations is known, whereas the second two tests allow the row and column addresses for the square grid to be separately scrambled in any arbitrary way unknown to the tester. The first test has length (97 /sup 5///sub 9/)n and detects all single active PNPSFs. The second test has length 121 /sup 5///sub 9/ and detects all single active, static and passive PNPSFs. The third test has a length of approximately 8.0n(log/sub 2/n)/sup 2/ and detects all single scrambled active PNPSFs. The fourth test has a length of roughly 8.4n(log/sub 2/n)/sup 2.322/ and detects all single scrambled active, static and passive PNPSFs.","PeriodicalId":318070,"journal":{"name":"Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing","volume":"922 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125110229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-07DOI: 10.1109/MTDT.1995.518077
C. Calligaro, V. Daniele, R. Gastaldi, A. Manstretta, G. Torelli
This paper presents a novel serial sensing method for multistorage non-volatile memories. The method is based on a dichotomic algorithm to detect the level stored in the memory cell selected. While maintaining the main advantage of the serial approach (the use of a single sense amplifier), the method proposed also reduces to a minimum the overall time needed to read the cell content. Sensing time is independent of the memory cell content.
{"title":"A new serial sensing approach for multistorage non-volatile memories","authors":"C. Calligaro, V. Daniele, R. Gastaldi, A. Manstretta, G. Torelli","doi":"10.1109/MTDT.1995.518077","DOIUrl":"https://doi.org/10.1109/MTDT.1995.518077","url":null,"abstract":"This paper presents a novel serial sensing method for multistorage non-volatile memories. The method is based on a dichotomic algorithm to detect the level stored in the memory cell selected. While maintaining the main advantage of the serial approach (the use of a single sense amplifier), the method proposed also reduces to a minimum the overall time needed to read the cell content. Sensing time is independent of the memory cell content.","PeriodicalId":318070,"journal":{"name":"Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing","volume":"28 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120872099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-07DOI: 10.1109/MTDT.1995.518076
W. Kao, X. Gao, R. Hamazaki, H. Kikuchi
As DRAM circuit densities increase and feature sizes decrease, circuit simulation of these circuits is becoming increasingly more critical and challenging in order to handle the large circuit capacity (millions of transistors), together with the accuracy required to take into account submicron effects. This paper presents a modeling and circuit reduction methodology and a DRAM modeling tool that lets the user configure the model architecture, parameterize and generate reduced macromodels, select and switch between different-level models, link the different models, and define circuit stimulus signals for the circuit simulation of the entire DRAM design.
{"title":"A modeling and circuit reduction methodology for circuit simulation of DRAM circuits","authors":"W. Kao, X. Gao, R. Hamazaki, H. Kikuchi","doi":"10.1109/MTDT.1995.518076","DOIUrl":"https://doi.org/10.1109/MTDT.1995.518076","url":null,"abstract":"As DRAM circuit densities increase and feature sizes decrease, circuit simulation of these circuits is becoming increasingly more critical and challenging in order to handle the large circuit capacity (millions of transistors), together with the accuracy required to take into account submicron effects. This paper presents a modeling and circuit reduction methodology and a DRAM modeling tool that lets the user configure the model architecture, parameterize and generate reduced macromodels, select and switch between different-level models, link the different models, and define circuit stimulus signals for the circuit simulation of the entire DRAM design.","PeriodicalId":318070,"journal":{"name":"Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126125240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-07DOI: 10.1109/MTDT.1995.518088
J.A. Gasbarro
This paper describes a revolutionary new technology for building high-performance DRAM memory systems that operate up to 10 times faster than conventional systems. With only a 9-bit wide interface, devices are capable of transferring data at over 500 MBytes per second. This technology is implemented using standard CMOS process, packaging and printed circuit fabrication techniques, and is suitable for cost-sensitive volume applications.
{"title":"The Rambus memory system","authors":"J.A. Gasbarro","doi":"10.1109/MTDT.1995.518088","DOIUrl":"https://doi.org/10.1109/MTDT.1995.518088","url":null,"abstract":"This paper describes a revolutionary new technology for building high-performance DRAM memory systems that operate up to 10 times faster than conventional systems. With only a 9-bit wide interface, devices are capable of transferring data at over 500 MBytes per second. This technology is implemented using standard CMOS process, packaging and printed circuit fabrication techniques, and is suitable for cost-sensitive volume applications.","PeriodicalId":318070,"journal":{"name":"Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127707957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-07DOI: 10.1109/MTDT.1995.518081
S. Menon, Arne Nymoen
Bipolar emitter-coupled logic (ECL) devices can be fabricated at very high densities and much lower power consumption. Analysis of faulty behavior of ECL storage elements shows they exhibit stuck-at behavior, loss of complementarity, delay faults and enhanced current being drawn by the device. Detection of the above behavior under faults using logic monitoring requires careful and systematic generation of input vectors. Testing for delay faults is even more difficult. A fault causing a delay fault as well as enhanced power supply current is shown. A current monitor for the detection of the enhanced power supply current is presented.
{"title":"Detection of faults in ECL storage elements","authors":"S. Menon, Arne Nymoen","doi":"10.1109/MTDT.1995.518081","DOIUrl":"https://doi.org/10.1109/MTDT.1995.518081","url":null,"abstract":"Bipolar emitter-coupled logic (ECL) devices can be fabricated at very high densities and much lower power consumption. Analysis of faulty behavior of ECL storage elements shows they exhibit stuck-at behavior, loss of complementarity, delay faults and enhanced current being drawn by the device. Detection of the above behavior under faults using logic monitoring requires careful and systematic generation of input vectors. Testing for delay faults is even more difficult. A fault causing a delay fault as well as enhanced power supply current is shown. A current monitor for the detection of the enhanced power supply current is presented.","PeriodicalId":318070,"journal":{"name":"Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132793211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-07DOI: 10.1109/MTDT.1995.518078
M. Franklin, K. Saluja
Embedded RAMs are RAMs whose address, data and read/write controls can not be directly controlled or observed through the chip's I/O pins. Testing these memories, which are incorporated on a large percentage of VLSI devices, is naturally harder because of the lack of controllability of its inputs and observability of its outputs. Testing such RAMs is the theme of this paper. It brings to light the challenges involved in testing embedded RAMs, and discusses techniques such as design for testability (DFT) and built-in self test (BIST), which help in improving the testability of these RAMs.
{"title":"Embedded RAM testing","authors":"M. Franklin, K. Saluja","doi":"10.1109/MTDT.1995.518078","DOIUrl":"https://doi.org/10.1109/MTDT.1995.518078","url":null,"abstract":"Embedded RAMs are RAMs whose address, data and read/write controls can not be directly controlled or observed through the chip's I/O pins. Testing these memories, which are incorporated on a large percentage of VLSI devices, is naturally harder because of the lack of controllability of its inputs and observability of its outputs. Testing such RAMs is the theme of this paper. It brings to light the challenges involved in testing embedded RAMs, and discusses techniques such as design for testability (DFT) and built-in self test (BIST), which help in improving the testability of these RAMs.","PeriodicalId":318070,"journal":{"name":"Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122918597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-07DOI: 10.1109/MTDT.1995.518083
T. Matsumura
The read/write disturb test is as indispensable for multi-port RAM testing as the functional memory test. This due to the need to check the influence of both a write operation under the read condition and a concurrent read operation upon the same memory cell through different ports. This paper describes novel algorithmic test patterns that are suitable for embedded multi-port RAM with BIST (built-in self-test) circuitry that realizes, for all ports, the functional memory test and the read/write disturb test concurrently while enabling memory operation. It is shown that these patterns can also detect BIST malfunctions even though they have about the same pattern length as the standard functional test patterns for single-port RAMs.
{"title":"An efficient test method for embedded multi-port RAM with BIST circuitry","authors":"T. Matsumura","doi":"10.1109/MTDT.1995.518083","DOIUrl":"https://doi.org/10.1109/MTDT.1995.518083","url":null,"abstract":"The read/write disturb test is as indispensable for multi-port RAM testing as the functional memory test. This due to the need to check the influence of both a write operation under the read condition and a concurrent read operation upon the same memory cell through different ports. This paper describes novel algorithmic test patterns that are suitable for embedded multi-port RAM with BIST (built-in self-test) circuitry that realizes, for all ports, the functional memory test and the read/write disturb test concurrently while enabling memory operation. It is shown that these patterns can also detect BIST malfunctions even though they have about the same pattern length as the standard functional test patterns for single-port RAMs.","PeriodicalId":318070,"journal":{"name":"Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121938967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-07DOI: 10.1109/MTDT.1995.518075
D.V. Das, R. Kumar, M. Lauria
Manufacturers' data sheets express the functionality of memory devices using timing diagrams. The relative time ordering of events can easily be captured in a Hasse diagram, which can then be used as a suitable model to automate behavioral model development.
{"title":"Modeling application specific memories","authors":"D.V. Das, R. Kumar, M. Lauria","doi":"10.1109/MTDT.1995.518075","DOIUrl":"https://doi.org/10.1109/MTDT.1995.518075","url":null,"abstract":"Manufacturers' data sheets express the functionality of memory devices using timing diagrams. The relative time ordering of events can easily be captured in a Hasse diagram, which can then be used as a suitable model to automate behavioral model development.","PeriodicalId":318070,"journal":{"name":"Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131691546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-07DOI: 10.1109/MTDT.1995.518084
S.W. Wood, G. Gibson, S. Adham, B. Nadeau-Dostie
Describes the architecture of a time-slot interchange (TSI) SRAM for a SONET switching application and its associated BIST architecture. To reduce the number of data RAMs required for full switching, the memory throughput is boosted by providing multiplexed access to the core at twice the system clock rate. The nature of the memory requires a novel BIST architecture to ensure full test coverage and ensure easy access of the BIST function at different levels of system integration.
{"title":"A 5 Gb/s 9-port application specific SRAM with built-in self test","authors":"S.W. Wood, G. Gibson, S. Adham, B. Nadeau-Dostie","doi":"10.1109/MTDT.1995.518084","DOIUrl":"https://doi.org/10.1109/MTDT.1995.518084","url":null,"abstract":"Describes the architecture of a time-slot interchange (TSI) SRAM for a SONET switching application and its associated BIST architecture. To reduce the number of data RAMs required for full switching, the memory throughput is boosted by providing multiplexed access to the core at twice the system clock rate. The nature of the memory requires a novel BIST architecture to ensure full test coverage and ensure easy access of the BIST function at different levels of system integration.","PeriodicalId":318070,"journal":{"name":"Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126374483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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