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2009 NASA/ESA Conference on Adaptive Hardware and Systems最新文献

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Self-Testable and Self-Repairable Bio-Inspired Configurable Circuits 自我测试和自我修复的仿生可配置电路
Pub Date : 2009-07-29 DOI: 10.1109/AHS.2009.19
A. Stauffer, J. Rossier
Inspired by the basic processes of molecular biology, our previous studies resulted in configurable circuits endowed with self-organizing properties like configuration, cloning, cicatrization, and regeneration. Among these properties, the activation of the two last ones is triggered by the existence of a fault detected by a built-in self-test mechanism. The goal of our paper is to implement such test mechanisms in the bio-inspired configurable circuits in order to make them self-testable and self-repairable.
受分子生物学基本过程的启发,我们之前的研究产生了具有自组织特性的可配置电路,如配置、克隆、愈合和再生。在这些属性中,后两个属性的激活是由内置自检机制检测到的故障触发的。本文的目标是在生物启发的可配置电路中实现这种测试机制,以使其自我测试和自我修复。
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引用次数: 8
Implementation of Highly Pipelined Datapaths on a Reconfigurable Asynchronous Substrate 在可重构异步基板上实现高度流水线化的数据路径
Pub Date : 2009-07-29 DOI: 10.1109/AHS.2009.56
Khodor Ahmad Fawaz, T. Arslan, Iain A. B. Lindsay
In programmable logic devices, the timing requirements change depending on what datapath is being mapped and the level of pipelining required. The added flexibility of such architectures translates to complexity in the design of their clocking scheme, both on the silicon and software level. Using asynchronous techniques to design the programmable elements and interconnects simplifies this problem by replacing the global clock signal with local handshaking. In asynchronous programmable devices, the handshaking protocol implements communication and synchronisation among the components of any mapped datapath irrespective of its length. This paper describes the design of an asynchronous substrate for implementing highly pipelined datapaths. A novel technique for conditional acknowledge synchronisation was used in the interconnect design. Two asynchronous arrays of coarse-grain adders and multipliers were built and compared with an equivalent clocked architecture. For a sample FFT, our asynchronous designs showed a reduction of up to 10% in energy consumption and 4.5% in area, which came at a cost of a 2.5% reduction in throughput over the equivalent synchronous implementation.
在可编程逻辑器件中,时序要求根据所映射的数据路径和所需的流水线级别而变化。这种架构增加的灵活性转化为其时钟方案设计的复杂性,无论是在芯片还是软件层面。采用异步技术设计可编程元件和互连,用本地握手代替全局时钟信号,从而简化了这一问题。在异步可编程设备中,握手协议实现了任意映射数据路径组件之间的通信和同步,而不考虑其长度。本文描述了实现高度流水线数据路径的异步基板的设计。在互连设计中采用了一种新的条件确认同步技术。构建了两个粗粒度加法器和乘法器异步阵列,并与等效的时钟结构进行了比较。对于一个示例FFT,我们的异步设计显示能耗减少了10%,面积减少了4.5%,与同等的同步实现相比,吞吐量减少了2.5%。
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引用次数: 4
Comparison of the Uniform and Non-Uniform Cellular Automata-Based Approach to the Development of Combinational Circuits 基于均匀和非均匀元胞自动机的组合电路开发方法的比较
Pub Date : 2009-07-29 DOI: 10.1109/AHS.2009.42
Michal Bidlo, Z. Vašíček
Cellular automata-based model has been shown as a useful developmental model in the evolutionary design of digital circuits at the gate level. Uniform one-dimensional cellular automata have been successfully applied to the circuit design task so far. Moreover, the initial experiments performed during our previous research have demonstrated the possibility of applying non-uniform cellular automata to the circuits design which is the main objective of the proposed paper. We will investigate this approach considering several classes of combinational circuits, provide an analysis of the obtained results and their comparison with the results of the uniform cellular automata-based model. It will be shown that evolution is able to find (in general a different) local transition function for each cell of the automaton according to which the target circuit is developed. Two different case studies will be presented in order to demonstrate the abilities of the proposed method. The first case study deals with the development of combinational multipliers and the second one is intended to develop combinational dividers. The obtained experimental results will be compared to our previous approach in which uniform cellular automata were applied. The proposed non-uniform approach enables to design circuits that we were not able to develop successfully using the uniform cellular automata.
基于元胞自动机的模型在门级数字电路的进化设计中已被证明是一种有用的发展模型。均匀一维元胞自动机目前已成功地应用于电路设计任务。此外,在我们之前的研究中进行的初步实验已经证明了将非均匀元胞自动机应用于电路设计的可能性,这是本文的主要目标。我们将考虑几类组合电路来研究这种方法,对所获得的结果进行分析,并将其与基于统一元胞自动机的模型的结果进行比较。它将表明,进化能够为自动机的每个细胞找到(通常是不同的)局部过渡函数,目标电路是根据这些细胞发展的。为了证明所提出的方法的能力,将提出两个不同的案例研究。第一个案例研究涉及组合乘数的发展,第二个案例研究旨在发展组合除数。得到的实验结果将与我们以前使用均匀元胞自动机的方法进行比较。提出的非均匀方法能够设计我们无法使用均匀元胞自动机成功开发的电路。
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引用次数: 2
Evolution of Impulse Bursts Noise Filters 脉冲突发噪声滤波器的发展
Pub Date : 2009-07-29 DOI: 10.1109/AHS.2009.33
Z. Vašíček, Michal Bidlo, L. Sekanina, J. Tørresen, K. Glette, M. Furuholmen
The paper deals with evolutionary design of impulse burst noise filters. As proposed filters utilize the filtering window of 5x5 pixels, the design method has to be able to manage 25 eight-bit inputs. The large number of inputs results in an evolutionary algorithm not able to produce reasonably working filters because of the so-called scalability problem of evolutionary circuit design. However, the filters are designed using an extended version of Cartesian Genetic Programming which enables to reduce the number of inputs by selecting the most important of them. Experimental evaluation of the method has shown that evolved filters exhibit better results than conventional solutions based on various median filters.
本文研究了脉冲突发噪声滤波器的进化设计。由于提议的滤波器利用5x5像素的滤波窗口,设计方法必须能够管理25个8位输入。由于进化电路设计的可扩展性问题,大量的输入导致进化算法无法产生合理的工作滤波器。然而,过滤器的设计使用了笛卡尔遗传规划的扩展版本,通过选择最重要的输入来减少输入的数量。实验结果表明,进化滤波器比基于各种中值滤波器的传统解决方案具有更好的效果。
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引用次数: 10
Nominal-Yield-Area Tradeoff in Automatic Synthesis of Analog Circuits: A Genetic Programming Approach Using Immune-Inspired Operators 模拟电路自动合成中的名义产出面积权衡:一种使用免疫激励算子的遗传规划方法
Pub Date : 2009-07-29 DOI: 10.1109/AHS.2009.32
P. Conca, Giuseppe Nicosia, Giovanni Stracquadanio, J. Timmis
The synthesis of analog circuits is a complex and expensive task; whilst there are various approaches for the synthesis of digital circuits, analog design is intrinsically more difficult since analog circuits process voltages in a continuous range. In the field of analog circuit design, the genetic programming approach has received great attention, affording the possibility to design and optimize a circuit at the same time. However, these algorithms have limited industrial relevance, since they work with ideal components. Starting from the well known results of Koza and co-authors, we introduce a new evolutionary algorithm, called elitist Immune Programming (EIP), that is able to synthesize an analog circuit using industrial components series in order to produce reliable and low cost circuits. The algorithm has been used for the synthesis of low-pass filters; the results were compared with the genetic programming, and the analysis shows that EIP is able to design better circuits in terms of frequency response and number of components. In addition we conduct a complete yield analysis of the discovered circuits, and discover that EIP circuits attain a higher yield than the circuits generated via a genetic programming approach, and, in particular, the algorithm discovers a Pareto Front which respects nominal performance (sizing), number of components (area) and yield (robustness).
模拟电路的合成是一项复杂而昂贵的任务;虽然有各种方法来合成数字电路,模拟设计本质上是更困难的,因为模拟电路处理电压在一个连续的范围内。在模拟电路设计领域,遗传规划方法受到了广泛的关注,它提供了同时设计和优化电路的可能性。然而,这些算法具有有限的工业相关性,因为它们与理想的组件一起工作。从Koza和合著者的众所周知的结果开始,我们引入了一种新的进化算法,称为精英免疫规划(EIP),它能够使用工业元件系列合成模拟电路,以生产可靠和低成本的电路。该算法已用于低通滤波器的合成;结果与遗传规划方法进行了比较,分析表明,遗传规划方法在频率响应和元件数量方面都能设计出更好的电路。此外,我们对所发现的电路进行了完整的良率分析,发现EIP电路比通过遗传规划方法生成的电路获得更高的良率,特别是,算法发现了一个Pareto Front,它尊重标称性能(尺寸)、组件数量(面积)和良率(鲁棒性)。
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引用次数: 17
Implementation of an IEEE802.11a Transmitter Module for a Reconfigurable System-on-a-Chip Design 用于可重构片上系统设计的IEEE802.11a发送模块的实现
Pub Date : 2009-07-29 DOI: 10.1109/AHS.2009.61
T. Vladimirova, J. Paul
Future formation flying satellite missions are being developed for a number of applications including Earth observation, space weather monitoring, etc. To carry out such missions effectively, intersatellite communication and on-board computing systems with adaptable processing capabilities will be needed. The underlying communication parameters and the satellite network topology will vary as a result of orbital dynamics and perturbations. In such a context, a flexible and reconfigurable on-board computing system becomes necessary. In this paper a system-on-a-chip design is proposed comprising of a general purpose processor and an IEEE 802.11 wireless network transceiver core, adapted to the space environment. Initial results on a novel implementation of the IEEE802.11a transmitter module are presented.
未来的编队飞行卫星任务正在开发,用于包括地球观测、空间天气监测等在内的许多应用。为了有效地执行这种任务,将需要具有适应性处理能力的卫星间通信和机载计算系统。潜在的通信参数和卫星网络拓扑结构将因轨道动力学和扰动而变化。在这种情况下,一个灵活的、可重构的机载计算系统变得非常必要。本文提出了一种适应空间环境的单片系统设计方案,该方案由一个通用处理器和一个IEEE 802.11无线网络收发核心组成。给出了IEEE802.11a发送模块的一种新实现的初步结果。
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引用次数: 6
Self-Scaling Stream Processing: A Bio-Inspired Approach to Resource Allocation through Dynamic Task Replication 自扩展流处理:通过动态任务复制实现资源分配的仿生方法
Pub Date : 2009-07-29 DOI: 10.1109/AHS.2009.25
Pierre-André Mudry, G. Tempesti
In this article, we show how the use of a bio-inspired dynamic task replication algorithm, in the context of stream processing, can be used to significantly improve the performance of embedded programs. We also show that this programming methodology, which is not tied to a particular implementation, can also be used as an heuristic for task mapping in the context of embedded multiprocessors systems. The technique was applied to a 36-processor system implemented on a scalable mesh of FPGAS for two different case studies: for AES encryption, it resulted in a ten-fold speedup compared to a static implementation, while for MJPEG compression a throughput multiplication of 11 was obtained.
在本文中,我们展示了如何在流处理的背景下使用生物启发的动态任务复制算法来显着提高嵌入式程序的性能。我们还展示了这种编程方法,它与特定的实现无关,也可以用作嵌入式多处理器系统上下文中任务映射的启发式方法。该技术应用于一个36处理器的系统,该系统在可扩展的fpga网格上实现,用于两个不同的案例研究:对于AES加密,与静态实现相比,它的速度提高了10倍,而对于MJPEG压缩,吞吐量增加了11倍。
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引用次数: 6
Effect of a Central Antenna Element on the Directivity, Half-Power Beamwidth and Side-Lobe Level of Circular Antenna Arrays 中心天线单元对圆形天线阵列方向性、半功率波束宽度和旁瓣电平的影响
Pub Date : 2009-07-29 DOI: 10.1109/AHS.2009.63
Virgilio Zúñiga, N. Haridas, A. Erdogan, T. Arslan
This paper analyses the effect of a central antenna element on the radiation pattern in a uniform circular antenna array. A modification of the array geometry is considered in which one of the antenna elements is placed in the center of the array. The corresponding array factor is adjusted to describe the geometric configuration that includes the central antenna element. This distribution alters the radiation pattern in such a way that the array directivity and half-power beamwidth are affected. An increase on the directivity and a decrease of the half-power beamwidth are obtained by adjusting the phase of the central element. A reduction of the side-lobe levels is also achieved. Array configurations with different number of antenna elements were tested as well, and the results on directivity and half-power beamwidth are presented. Using Microstripes, a software tool that enables the simulation of antennas, a 6-element circular antenna array was designed and the directivity for a range of frequencies was obtained.
本文分析了均匀圆形天线阵中中心天线单元对辐射方向图的影响。考虑了阵列几何形状的修改,其中一个天线单元放置在阵列的中心。调整相应的阵列因子以描述包括中心天线元件的几何结构。这种分布改变了辐射方向图,从而影响了阵列的方向性和半功率波束宽度。通过调整中心元件的相位,可以提高波导的指向性,减小半功率波束宽度。还实现了副瓣电平的降低。对不同天线单元数的阵列配置进行了测试,给出了指向性和半功率波束宽度的测试结果。利用天线仿真软件Microstripes设计了一个6元圆形天线阵列,得到了该阵列在一定频率范围内的指向性。
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引用次数: 10
Mersenne Twister Random Number Generation on FPGA, CPU and GPU 基于FPGA、CPU和GPU的梅森扭扭随机数生成
Pub Date : 2009-07-29 DOI: 10.1109/AHS.2009.11
Xiang Tian, K. Benkrid
Random number generation is a very important operation in computational science e.g. in Monte Carlo simulations methods. It is also a computationally intensive operation especially for high quality random number generation. In this paper, we present the design and implementation of a parallel implementation of one of the most widely used random number generators, namely the Mersenne Twister. The latter is very widely used in high performance computing applications such as financial computing. Implementations of our parallel Mersenne Twister number generator core on Xilinx Virtex4 FPGAs achieve a throughput of 26.13 billion random samples per second. The paper also reports equivalent parallel software implementations running on an Intel Core 2 Quad Q9300 CPU with 8 GB RAM, using multi-threading technology and the Intel® Math Kernel Library (MKL), as well as on an NVIDIA 8800 GTX GPU. Comparative results show that our FPGA-based implementation outperforms equivalent CPU and GPU implementations by ~25x and ~9x respectively. Moreover, when using the same amount of energy, the FPGA can generate 37x and 35x more Mersenne Twister random samples than the CPU and the GPU, respectively.
随机数生成是计算科学中非常重要的操作,例如在蒙特卡罗模拟方法中。它也是一个计算密集型的操作,特别是对于高质量的随机数生成。在本文中,我们提出了一个最广泛使用的随机数生成器,即Mersenne Twister的并行实现的设计和实现。后者广泛用于高性能计算应用,如金融计算。我们在Xilinx Virtex4 fpga上的并行Mersenne Twister数字生成器内核实现了每秒261.3亿个随机样本的吞吐量。本文还报告了在具有8 GB RAM的英特尔酷睿2 Quad Q9300 CPU上运行的等效并行软件实现,使用多线程技术和英特尔®数学内核库(MKL),以及在NVIDIA 8800 GTX GPU上运行。对比结果表明,基于fpga的实现比同等的CPU和GPU实现分别高出25倍和9倍。此外,在使用相同能量的情况下,FPGA产生的Mersenne Twister随机样本分别是CPU和GPU的37倍和35倍。
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引用次数: 54
Adapting a Genotype-phenotype Mapping to Phenotypic Complexity 适应基因型-表型定位的表型复杂性
Pub Date : 2009-07-29 DOI: 10.1109/AHS.2009.47
Morten Hartmann, Tim Goedeweeck
The marvel of biological development has motivated researchers to apply artificial development in bio-inspired systems. Among the possible features of artificial development that are being investigated is the potential for improving scalability of evolutionary optimization techniques,by applying artificial development as an indirect mapping.Currently, few guidelines exist as to when development is likely to achieve such improvements. We investigate one guideline based on the complexity of the phenotypic objective and propose a grammatical mapping which can adapt to this complexity. Earlier findings on the correlation between the performance of indirect mappings and phenotypic complexity are confirmed in a new context. Adaptation of an indirect mapping to phenotypic complexity is shown to work well given certain conditions.
生物发展的奇迹促使研究人员在仿生系统中应用人工发展。正在研究的人工开发的可能特征之一是通过将人工开发作为间接映射应用于改进进化优化技术的可扩展性的潜力。目前,几乎没有关于发展何时可能实现这种改进的指导方针。我们研究了一个基于表型目标复杂性的指导方针,并提出了一个可以适应这种复杂性的语法映射。在一个新的背景下,关于间接映射的表现和表型复杂性之间的相关性的早期发现得到了证实。间接映射对表型复杂性的适应在一定条件下表现良好。
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引用次数: 1
期刊
2009 NASA/ESA Conference on Adaptive Hardware and Systems
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