Inspired by the basic processes of molecular biology, our previous studies resulted in configurable circuits endowed with self-organizing properties like configuration, cloning, cicatrization, and regeneration. Among these properties, the activation of the two last ones is triggered by the existence of a fault detected by a built-in self-test mechanism. The goal of our paper is to implement such test mechanisms in the bio-inspired configurable circuits in order to make them self-testable and self-repairable.
{"title":"Self-Testable and Self-Repairable Bio-Inspired Configurable Circuits","authors":"A. Stauffer, J. Rossier","doi":"10.1109/AHS.2009.19","DOIUrl":"https://doi.org/10.1109/AHS.2009.19","url":null,"abstract":"Inspired by the basic processes of molecular biology, our previous studies resulted in configurable circuits endowed with self-organizing properties like configuration, cloning, cicatrization, and regeneration. Among these properties, the activation of the two last ones is triggered by the existence of a fault detected by a built-in self-test mechanism. The goal of our paper is to implement such test mechanisms in the bio-inspired configurable circuits in order to make them self-testable and self-repairable.","PeriodicalId":318989,"journal":{"name":"2009 NASA/ESA Conference on Adaptive Hardware and Systems","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127151190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In programmable logic devices, the timing requirements change depending on what datapath is being mapped and the level of pipelining required. The added flexibility of such architectures translates to complexity in the design of their clocking scheme, both on the silicon and software level. Using asynchronous techniques to design the programmable elements and interconnects simplifies this problem by replacing the global clock signal with local handshaking. In asynchronous programmable devices, the handshaking protocol implements communication and synchronisation among the components of any mapped datapath irrespective of its length. This paper describes the design of an asynchronous substrate for implementing highly pipelined datapaths. A novel technique for conditional acknowledge synchronisation was used in the interconnect design. Two asynchronous arrays of coarse-grain adders and multipliers were built and compared with an equivalent clocked architecture. For a sample FFT, our asynchronous designs showed a reduction of up to 10% in energy consumption and 4.5% in area, which came at a cost of a 2.5% reduction in throughput over the equivalent synchronous implementation.
{"title":"Implementation of Highly Pipelined Datapaths on a Reconfigurable Asynchronous Substrate","authors":"Khodor Ahmad Fawaz, T. Arslan, Iain A. B. Lindsay","doi":"10.1109/AHS.2009.56","DOIUrl":"https://doi.org/10.1109/AHS.2009.56","url":null,"abstract":"In programmable logic devices, the timing requirements change depending on what datapath is being mapped and the level of pipelining required. The added flexibility of such architectures translates to complexity in the design of their clocking scheme, both on the silicon and software level. Using asynchronous techniques to design the programmable elements and interconnects simplifies this problem by replacing the global clock signal with local handshaking. In asynchronous programmable devices, the handshaking protocol implements communication and synchronisation among the components of any mapped datapath irrespective of its length. This paper describes the design of an asynchronous substrate for implementing highly pipelined datapaths. A novel technique for conditional acknowledge synchronisation was used in the interconnect design. Two asynchronous arrays of coarse-grain adders and multipliers were built and compared with an equivalent clocked architecture. For a sample FFT, our asynchronous designs showed a reduction of up to 10% in energy consumption and 4.5% in area, which came at a cost of a 2.5% reduction in throughput over the equivalent synchronous implementation.","PeriodicalId":318989,"journal":{"name":"2009 NASA/ESA Conference on Adaptive Hardware and Systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127988848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Cellular automata-based model has been shown as a useful developmental model in the evolutionary design of digital circuits at the gate level. Uniform one-dimensional cellular automata have been successfully applied to the circuit design task so far. Moreover, the initial experiments performed during our previous research have demonstrated the possibility of applying non-uniform cellular automata to the circuits design which is the main objective of the proposed paper. We will investigate this approach considering several classes of combinational circuits, provide an analysis of the obtained results and their comparison with the results of the uniform cellular automata-based model. It will be shown that evolution is able to find (in general a different) local transition function for each cell of the automaton according to which the target circuit is developed. Two different case studies will be presented in order to demonstrate the abilities of the proposed method. The first case study deals with the development of combinational multipliers and the second one is intended to develop combinational dividers. The obtained experimental results will be compared to our previous approach in which uniform cellular automata were applied. The proposed non-uniform approach enables to design circuits that we were not able to develop successfully using the uniform cellular automata.
{"title":"Comparison of the Uniform and Non-Uniform Cellular Automata-Based Approach to the Development of Combinational Circuits","authors":"Michal Bidlo, Z. Vašíček","doi":"10.1109/AHS.2009.42","DOIUrl":"https://doi.org/10.1109/AHS.2009.42","url":null,"abstract":"Cellular automata-based model has been shown as a useful developmental model in the evolutionary design of digital circuits at the gate level. Uniform one-dimensional cellular automata have been successfully applied to the circuit design task so far. Moreover, the initial experiments performed during our previous research have demonstrated the possibility of applying non-uniform cellular automata to the circuits design which is the main objective of the proposed paper. We will investigate this approach considering several classes of combinational circuits, provide an analysis of the obtained results and their comparison with the results of the uniform cellular automata-based model. It will be shown that evolution is able to find (in general a different) local transition function for each cell of the automaton according to which the target circuit is developed. Two different case studies will be presented in order to demonstrate the abilities of the proposed method. The first case study deals with the development of combinational multipliers and the second one is intended to develop combinational dividers. The obtained experimental results will be compared to our previous approach in which uniform cellular automata were applied. The proposed non-uniform approach enables to design circuits that we were not able to develop successfully using the uniform cellular automata.","PeriodicalId":318989,"journal":{"name":"2009 NASA/ESA Conference on Adaptive Hardware and Systems","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123259837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Z. Vašíček, Michal Bidlo, L. Sekanina, J. Tørresen, K. Glette, M. Furuholmen
The paper deals with evolutionary design of impulse burst noise filters. As proposed filters utilize the filtering window of 5x5 pixels, the design method has to be able to manage 25 eight-bit inputs. The large number of inputs results in an evolutionary algorithm not able to produce reasonably working filters because of the so-called scalability problem of evolutionary circuit design. However, the filters are designed using an extended version of Cartesian Genetic Programming which enables to reduce the number of inputs by selecting the most important of them. Experimental evaluation of the method has shown that evolved filters exhibit better results than conventional solutions based on various median filters.
{"title":"Evolution of Impulse Bursts Noise Filters","authors":"Z. Vašíček, Michal Bidlo, L. Sekanina, J. Tørresen, K. Glette, M. Furuholmen","doi":"10.1109/AHS.2009.33","DOIUrl":"https://doi.org/10.1109/AHS.2009.33","url":null,"abstract":"The paper deals with evolutionary design of impulse burst noise filters. As proposed filters utilize the filtering window of 5x5 pixels, the design method has to be able to manage 25 eight-bit inputs. The large number of inputs results in an evolutionary algorithm not able to produce reasonably working filters because of the so-called scalability problem of evolutionary circuit design. However, the filters are designed using an extended version of Cartesian Genetic Programming which enables to reduce the number of inputs by selecting the most important of them. Experimental evaluation of the method has shown that evolved filters exhibit better results than conventional solutions based on various median filters.","PeriodicalId":318989,"journal":{"name":"2009 NASA/ESA Conference on Adaptive Hardware and Systems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124450680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Conca, Giuseppe Nicosia, Giovanni Stracquadanio, J. Timmis
The synthesis of analog circuits is a complex and expensive task; whilst there are various approaches for the synthesis of digital circuits, analog design is intrinsically more difficult since analog circuits process voltages in a continuous range. In the field of analog circuit design, the genetic programming approach has received great attention, affording the possibility to design and optimize a circuit at the same time. However, these algorithms have limited industrial relevance, since they work with ideal components. Starting from the well known results of Koza and co-authors, we introduce a new evolutionary algorithm, called elitist Immune Programming (EIP), that is able to synthesize an analog circuit using industrial components series in order to produce reliable and low cost circuits. The algorithm has been used for the synthesis of low-pass filters; the results were compared with the genetic programming, and the analysis shows that EIP is able to design better circuits in terms of frequency response and number of components. In addition we conduct a complete yield analysis of the discovered circuits, and discover that EIP circuits attain a higher yield than the circuits generated via a genetic programming approach, and, in particular, the algorithm discovers a Pareto Front which respects nominal performance (sizing), number of components (area) and yield (robustness).
{"title":"Nominal-Yield-Area Tradeoff in Automatic Synthesis of Analog Circuits: A Genetic Programming Approach Using Immune-Inspired Operators","authors":"P. Conca, Giuseppe Nicosia, Giovanni Stracquadanio, J. Timmis","doi":"10.1109/AHS.2009.32","DOIUrl":"https://doi.org/10.1109/AHS.2009.32","url":null,"abstract":"The synthesis of analog circuits is a complex and expensive task; whilst there are various approaches for the synthesis of digital circuits, analog design is intrinsically more difficult since analog circuits process voltages in a continuous range. In the field of analog circuit design, the genetic programming approach has received great attention, affording the possibility to design and optimize a circuit at the same time. However, these algorithms have limited industrial relevance, since they work with ideal components. Starting from the well known results of Koza and co-authors, we introduce a new evolutionary algorithm, called elitist Immune Programming (EIP), that is able to synthesize an analog circuit using industrial components series in order to produce reliable and low cost circuits. The algorithm has been used for the synthesis of low-pass filters; the results were compared with the genetic programming, and the analysis shows that EIP is able to design better circuits in terms of frequency response and number of components. In addition we conduct a complete yield analysis of the discovered circuits, and discover that EIP circuits attain a higher yield than the circuits generated via a genetic programming approach, and, in particular, the algorithm discovers a Pareto Front which respects nominal performance (sizing), number of components (area) and yield (robustness).","PeriodicalId":318989,"journal":{"name":"2009 NASA/ESA Conference on Adaptive Hardware and Systems","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121029905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Future formation flying satellite missions are being developed for a number of applications including Earth observation, space weather monitoring, etc. To carry out such missions effectively, intersatellite communication and on-board computing systems with adaptable processing capabilities will be needed. The underlying communication parameters and the satellite network topology will vary as a result of orbital dynamics and perturbations. In such a context, a flexible and reconfigurable on-board computing system becomes necessary. In this paper a system-on-a-chip design is proposed comprising of a general purpose processor and an IEEE 802.11 wireless network transceiver core, adapted to the space environment. Initial results on a novel implementation of the IEEE802.11a transmitter module are presented.
{"title":"Implementation of an IEEE802.11a Transmitter Module for a Reconfigurable System-on-a-Chip Design","authors":"T. Vladimirova, J. Paul","doi":"10.1109/AHS.2009.61","DOIUrl":"https://doi.org/10.1109/AHS.2009.61","url":null,"abstract":"Future formation flying satellite missions are being developed for a number of applications including Earth observation, space weather monitoring, etc. To carry out such missions effectively, intersatellite communication and on-board computing systems with adaptable processing capabilities will be needed. The underlying communication parameters and the satellite network topology will vary as a result of orbital dynamics and perturbations. In such a context, a flexible and reconfigurable on-board computing system becomes necessary. In this paper a system-on-a-chip design is proposed comprising of a general purpose processor and an IEEE 802.11 wireless network transceiver core, adapted to the space environment. Initial results on a novel implementation of the IEEE802.11a transmitter module are presented.","PeriodicalId":318989,"journal":{"name":"2009 NASA/ESA Conference on Adaptive Hardware and Systems","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126192122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this article, we show how the use of a bio-inspired dynamic task replication algorithm, in the context of stream processing, can be used to significantly improve the performance of embedded programs. We also show that this programming methodology, which is not tied to a particular implementation, can also be used as an heuristic for task mapping in the context of embedded multiprocessors systems. The technique was applied to a 36-processor system implemented on a scalable mesh of FPGAS for two different case studies: for AES encryption, it resulted in a ten-fold speedup compared to a static implementation, while for MJPEG compression a throughput multiplication of 11 was obtained.
{"title":"Self-Scaling Stream Processing: A Bio-Inspired Approach to Resource Allocation through Dynamic Task Replication","authors":"Pierre-André Mudry, G. Tempesti","doi":"10.1109/AHS.2009.25","DOIUrl":"https://doi.org/10.1109/AHS.2009.25","url":null,"abstract":"In this article, we show how the use of a bio-inspired dynamic task replication algorithm, in the context of stream processing, can be used to significantly improve the performance of embedded programs. We also show that this programming methodology, which is not tied to a particular implementation, can also be used as an heuristic for task mapping in the context of embedded multiprocessors systems. The technique was applied to a 36-processor system implemented on a scalable mesh of FPGAS for two different case studies: for AES encryption, it resulted in a ten-fold speedup compared to a static implementation, while for MJPEG compression a throughput multiplication of 11 was obtained.","PeriodicalId":318989,"journal":{"name":"2009 NASA/ESA Conference on Adaptive Hardware and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130577851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Virgilio Zúñiga, N. Haridas, A. Erdogan, T. Arslan
This paper analyses the effect of a central antenna element on the radiation pattern in a uniform circular antenna array. A modification of the array geometry is considered in which one of the antenna elements is placed in the center of the array. The corresponding array factor is adjusted to describe the geometric configuration that includes the central antenna element. This distribution alters the radiation pattern in such a way that the array directivity and half-power beamwidth are affected. An increase on the directivity and a decrease of the half-power beamwidth are obtained by adjusting the phase of the central element. A reduction of the side-lobe levels is also achieved. Array configurations with different number of antenna elements were tested as well, and the results on directivity and half-power beamwidth are presented. Using Microstripes, a software tool that enables the simulation of antennas, a 6-element circular antenna array was designed and the directivity for a range of frequencies was obtained.
{"title":"Effect of a Central Antenna Element on the Directivity, Half-Power Beamwidth and Side-Lobe Level of Circular Antenna Arrays","authors":"Virgilio Zúñiga, N. Haridas, A. Erdogan, T. Arslan","doi":"10.1109/AHS.2009.63","DOIUrl":"https://doi.org/10.1109/AHS.2009.63","url":null,"abstract":"This paper analyses the effect of a central antenna element on the radiation pattern in a uniform circular antenna array. A modification of the array geometry is considered in which one of the antenna elements is placed in the center of the array. The corresponding array factor is adjusted to describe the geometric configuration that includes the central antenna element. This distribution alters the radiation pattern in such a way that the array directivity and half-power beamwidth are affected. An increase on the directivity and a decrease of the half-power beamwidth are obtained by adjusting the phase of the central element. A reduction of the side-lobe levels is also achieved. Array configurations with different number of antenna elements were tested as well, and the results on directivity and half-power beamwidth are presented. Using Microstripes, a software tool that enables the simulation of antennas, a 6-element circular antenna array was designed and the directivity for a range of frequencies was obtained.","PeriodicalId":318989,"journal":{"name":"2009 NASA/ESA Conference on Adaptive Hardware and Systems","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131481156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Random number generation is a very important operation in computational science e.g. in Monte Carlo simulations methods. It is also a computationally intensive operation especially for high quality random number generation. In this paper, we present the design and implementation of a parallel implementation of one of the most widely used random number generators, namely the Mersenne Twister. The latter is very widely used in high performance computing applications such as financial computing. Implementations of our parallel Mersenne Twister number generator core on Xilinx Virtex4 FPGAs achieve a throughput of 26.13 billion random samples per second. The paper also reports equivalent parallel software implementations running on an Intel Core 2 Quad Q9300 CPU with 8 GB RAM, using multi-threading technology and the Intel® Math Kernel Library (MKL), as well as on an NVIDIA 8800 GTX GPU. Comparative results show that our FPGA-based implementation outperforms equivalent CPU and GPU implementations by ~25x and ~9x respectively. Moreover, when using the same amount of energy, the FPGA can generate 37x and 35x more Mersenne Twister random samples than the CPU and the GPU, respectively.
{"title":"Mersenne Twister Random Number Generation on FPGA, CPU and GPU","authors":"Xiang Tian, K. Benkrid","doi":"10.1109/AHS.2009.11","DOIUrl":"https://doi.org/10.1109/AHS.2009.11","url":null,"abstract":"Random number generation is a very important operation in computational science e.g. in Monte Carlo simulations methods. It is also a computationally intensive operation especially for high quality random number generation. In this paper, we present the design and implementation of a parallel implementation of one of the most widely used random number generators, namely the Mersenne Twister. The latter is very widely used in high performance computing applications such as financial computing. Implementations of our parallel Mersenne Twister number generator core on Xilinx Virtex4 FPGAs achieve a throughput of 26.13 billion random samples per second. The paper also reports equivalent parallel software implementations running on an Intel Core 2 Quad Q9300 CPU with 8 GB RAM, using multi-threading technology and the Intel® Math Kernel Library (MKL), as well as on an NVIDIA 8800 GTX GPU. Comparative results show that our FPGA-based implementation outperforms equivalent CPU and GPU implementations by ~25x and ~9x respectively. Moreover, when using the same amount of energy, the FPGA can generate 37x and 35x more Mersenne Twister random samples than the CPU and the GPU, respectively.","PeriodicalId":318989,"journal":{"name":"2009 NASA/ESA Conference on Adaptive Hardware and Systems","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129310939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The marvel of biological development has motivated researchers to apply artificial development in bio-inspired systems. Among the possible features of artificial development that are being investigated is the potential for improving scalability of evolutionary optimization techniques,by applying artificial development as an indirect mapping.Currently, few guidelines exist as to when development is likely to achieve such improvements. We investigate one guideline based on the complexity of the phenotypic objective and propose a grammatical mapping which can adapt to this complexity. Earlier findings on the correlation between the performance of indirect mappings and phenotypic complexity are confirmed in a new context. Adaptation of an indirect mapping to phenotypic complexity is shown to work well given certain conditions.
{"title":"Adapting a Genotype-phenotype Mapping to Phenotypic Complexity","authors":"Morten Hartmann, Tim Goedeweeck","doi":"10.1109/AHS.2009.47","DOIUrl":"https://doi.org/10.1109/AHS.2009.47","url":null,"abstract":"The marvel of biological development has motivated researchers to apply artificial development in bio-inspired systems. Among the possible features of artificial development that are being investigated is the potential for improving scalability of evolutionary optimization techniques,by applying artificial development as an indirect mapping.Currently, few guidelines exist as to when development is likely to achieve such improvements. We investigate one guideline based on the complexity of the phenotypic objective and propose a grammatical mapping which can adapt to this complexity. Earlier findings on the correlation between the performance of indirect mappings and phenotypic complexity are confirmed in a new context. Adaptation of an indirect mapping to phenotypic complexity is shown to work well given certain conditions.","PeriodicalId":318989,"journal":{"name":"2009 NASA/ESA Conference on Adaptive Hardware and Systems","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125123903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}