M. Samie, G. Dragffy, A. Popescu, A. Pipe, J. Kiely
This paper presents a novel bio-inspired artificial system that is based on biological prokaryotic organisms and their artificial model, and proposes a new type of fault tolerant, self-healing architecture. The system comprises of a sea of bio-inspired cells, arranged in a rectangular array with a topology that is similar to that employed by FPGAs. A key feature of the array is its high level of fault tolerance, achieved with only minimal amount of hardware overhead. Inspired by similar biological processes, the technique is based on direct-correlated redundancy, where the redundant (stand-by) configuration bits, as extrinsic experience, are shared between blocks and cells of a colony in the artificial system. Bio-inspired array implementation is particularly advantageous in applications where the system is subject to extreme environmental conditions such as temperature, radiation, SEU (Single Event Upset) etc. and where fault tolerance is of particular importance.
{"title":"Prokaryotic Bio-Inspired System","authors":"M. Samie, G. Dragffy, A. Popescu, A. Pipe, J. Kiely","doi":"10.1109/AHS.2009.36","DOIUrl":"https://doi.org/10.1109/AHS.2009.36","url":null,"abstract":"This paper presents a novel bio-inspired artificial system that is based on biological prokaryotic organisms and their artificial model, and proposes a new type of fault tolerant, self-healing architecture. The system comprises of a sea of bio-inspired cells, arranged in a rectangular array with a topology that is similar to that employed by FPGAs. A key feature of the array is its high level of fault tolerance, achieved with only minimal amount of hardware overhead. Inspired by similar biological processes, the technique is based on direct-correlated redundancy, where the redundant (stand-by) configuration bits, as extrinsic experience, are shared between blocks and cells of a colony in the artificial system. Bio-inspired array implementation is particularly advantageous in applications where the system is subject to extreme environmental conditions such as temperature, radiation, SEU (Single Event Upset) etc. and where fault tolerance is of particular importance.","PeriodicalId":318989,"journal":{"name":"2009 NASA/ESA Conference on Adaptive Hardware and Systems","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121068146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
HuaQiu Yang, Liguang Chen, Shaoteng Liu, HaiXiang Bu, Y. Wang, Jinmei Lai
A flexible bit-stream level evolvable hardware (EHW) platform is proposed in order to efficiently utilize the programmable logic resources of FPGA when evolving digital circuits. This platform is based on the FuDan FPGA device. An adaptive variable-size look-up-table (LUT) array structure is proposed with the optimal Genetic Algorithm to evolvable circuits. The experiment results showed that the proposed platform is more flexible, and it not only can make good use of FPGA logic resources, but also has a quick evolving speed.
{"title":"A Flexible Bit-Stream Level Evolvable Hardware Platform Based on FPGA","authors":"HuaQiu Yang, Liguang Chen, Shaoteng Liu, HaiXiang Bu, Y. Wang, Jinmei Lai","doi":"10.1109/AHS.2009.44","DOIUrl":"https://doi.org/10.1109/AHS.2009.44","url":null,"abstract":"A flexible bit-stream level evolvable hardware (EHW) platform is proposed in order to efficiently utilize the programmable logic resources of FPGA when evolving digital circuits. This platform is based on the FuDan FPGA device. An adaptive variable-size look-up-table (LUT) array structure is proposed with the optimal Genetic Algorithm to evolvable circuits. The experiment results showed that the proposed platform is more flexible, and it not only can make good use of FPGA logic resources, but also has a quick evolving speed.","PeriodicalId":318989,"journal":{"name":"2009 NASA/ESA Conference on Adaptive Hardware and Systems","volume":"253 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121323556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. L. Beux, G. Nicolescu, G. Bois, Y. Bouchebaba, M. Langevin, P. Paulin
Networks on Chip (NoCs) have emerged as the key paradigm for designing a scalable communication infrastructure for future Multi-Processors Systems on Chip(MPSoCs). An important issue in NoC design is how to configure a NoC-based architecture and how to map an application on this architecture in order to satisfy the performance and cost requirements. In this paper, we propose an approach that concurrently optimizes the configuration of NoC-based architectures and the mapping of streaming applications. The proposed approach exploits multiobjective evolutionary algorithms that are fed by execution performances scores corresponding to the evaluated MPSoC configurations and mappings ability to pipeline execution of the streaming application. As an optimization result, most promising configurations and mappings are highlighted. We show results for mapping an image processing application onto a configurable MPSoC architecture. These results highlight MPSoC architectures configured to interconnect up to 12 processors using Crossbar, Mesh and Ring topologies.
{"title":"Optimizing Configuration and Application Mapping for MPSoC Architectures","authors":"S. L. Beux, G. Nicolescu, G. Bois, Y. Bouchebaba, M. Langevin, P. Paulin","doi":"10.1109/AHS.2009.35","DOIUrl":"https://doi.org/10.1109/AHS.2009.35","url":null,"abstract":"Networks on Chip (NoCs) have emerged as the key paradigm for designing a scalable communication infrastructure for future Multi-Processors Systems on Chip(MPSoCs). An important issue in NoC design is how to configure a NoC-based architecture and how to map an application on this architecture in order to satisfy the performance and cost requirements. In this paper, we propose an approach that concurrently optimizes the configuration of NoC-based architectures and the mapping of streaming applications. The proposed approach exploits multiobjective evolutionary algorithms that are fed by execution performances scores corresponding to the evaluated MPSoC configurations and mappings ability to pipeline execution of the streaming application. As an optimization result, most promising configurations and mappings are highlighted. We show results for mapping an image processing application onto a configurable MPSoC architecture. These results highlight MPSoC architectures configured to interconnect up to 12 processors using Crossbar, Mesh and Ring topologies.","PeriodicalId":318989,"journal":{"name":"2009 NASA/ESA Conference on Adaptive Hardware and Systems","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126961408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Mabuchi, K. Miyashiro, Minoru Watanabe, A. Ogiwara
Optically reconfigurable gate arrays (ORGAs) have been developed as a type of multi-context field programmable gate array to realize fast reconfiguration and numerous reconfiguration contexts. Along with such advantages, ORGAs have high defect tolerance. They consist simply of a holographic memory, a laser diode array, and a gate array VLSI. Even if a gate array VLSI includes defective areas, the ORGAs capability of perfectly parallel programmability enables avoidance of those defective areas through alternative use of other non-defective areas. Moreover, a holographic memory to store contexts is known to have high defect tolerance because each bit of a reconfiguration context can be generated from the entire holographic memory.Consequently, damage of a holographic memory rarely affects its diffraction pattern or a reconfiguration context. For that reason, ORGAs are extremely robust against component defects in devices such as a laser array, a gate array, and a holographic memory, and are particularly useful for space applications, which require high reliability.This paper presents experimentation related to the defect tolerance of new optically reconfigurable gate array with a one-time easily writable volume holographic memory.
{"title":"Defect Tolerance of an Optically Reconfigurable Gate Array with a One-time Writable Volume Holographic Memory","authors":"T. Mabuchi, K. Miyashiro, Minoru Watanabe, A. Ogiwara","doi":"10.1109/AHS.2009.62","DOIUrl":"https://doi.org/10.1109/AHS.2009.62","url":null,"abstract":"Optically reconfigurable gate arrays (ORGAs) have been developed as a type of multi-context field programmable gate array to realize fast reconfiguration and numerous reconfiguration contexts. Along with such advantages, ORGAs have high defect tolerance. They consist simply of a holographic memory, a laser diode array, and a gate array VLSI. Even if a gate array VLSI includes defective areas, the ORGAs capability of perfectly parallel programmability enables avoidance of those defective areas through alternative use of other non-defective areas. Moreover, a holographic memory to store contexts is known to have high defect tolerance because each bit of a reconfiguration context can be generated from the entire holographic memory.Consequently, damage of a holographic memory rarely affects its diffraction pattern or a reconfiguration context. For that reason, ORGAs are extremely robust against component defects in devices such as a laser array, a gate array, and a holographic memory, and are particularly useful for space applications, which require high reliability.This paper presents experimentation related to the defect tolerance of new optically reconfigurable gate array with a one-time easily writable volume holographic memory.","PeriodicalId":318989,"journal":{"name":"2009 NASA/ESA Conference on Adaptive Hardware and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123899426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Evangelos Papoutsis, W. Howells, Andrew B. T. Hopkins, K. Mcdonald-Maier
This paper investigates the practicalities of combining values derived from measurable features of given integrated electronic circuits in order to derive a robust encryption key, a technique termed ICmetrics. Specifically the paper explores options for the precise techniques required to combine the derived feature values in order to ensure key stability. Key stability is an essential component of any encryption system but this must be combined with a guarantee of key diversity between devices.
{"title":"Integrating Feature Values for Key Generation in an ICmetric System","authors":"Evangelos Papoutsis, W. Howells, Andrew B. T. Hopkins, K. Mcdonald-Maier","doi":"10.1109/AHS.2009.30","DOIUrl":"https://doi.org/10.1109/AHS.2009.30","url":null,"abstract":"This paper investigates the practicalities of combining values derived from measurable features of given integrated electronic circuits in order to derive a robust encryption key, a technique termed ICmetrics. Specifically the paper explores options for the precise techniques required to combine the derived feature values in order to ensure key stability. Key stability is an essential component of any encryption system but this must be combined with a guarantee of key diversity between devices.","PeriodicalId":318989,"journal":{"name":"2009 NASA/ESA Conference on Adaptive Hardware and Systems","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126485318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yang Yang, Sanyou Zeng, Haoqiu Long, Zu Yan, Danpin Yu, Lishan Kang
Antenna design problems are complex multi-objective optimization problems. It is difficult to solve such problems using traditional methods. This paper creates a new model to solve antenna problems. In this new model, antennas' requirements are reflected not only in problems' constraints, but also in their objectives. It means feasible solutions are solutions that satisfy antennas' requirements. So if we find out a feasible solution, antenna design problems would have been solved. After that, with the evolution going on, feasible solution would be optimized, and global optimal solution would be found out. This paper uses a new algorithm, dynamic dominances evolutionary algorithm (DDEA), to solve antenna problems. DDEA has been tested by 22 benchmark problems. DDEA can consistently find the global optimum of all test problems with success rate 100%, while any other algorithm can't achieve such high success rate. This paper takes lower earth orbit ST5 antenna designed problem as a real world test problem. The experimental result shows: using this new model and DDEA, ST5 antenna design problem can be solved effectively. In addition the simulation result shows our evolved antennas are quite competitive with NASA's.
{"title":"Automated Wire Antennas Design using Dynamic Dominance Evolutionary Algorithm","authors":"Yang Yang, Sanyou Zeng, Haoqiu Long, Zu Yan, Danpin Yu, Lishan Kang","doi":"10.1109/AHS.2009.7","DOIUrl":"https://doi.org/10.1109/AHS.2009.7","url":null,"abstract":"Antenna design problems are complex multi-objective optimization problems. It is difficult to solve such problems using traditional methods. This paper creates a new model to solve antenna problems. In this new model, antennas' requirements are reflected not only in problems' constraints, but also in their objectives. It means feasible solutions are solutions that satisfy antennas' requirements. So if we find out a feasible solution, antenna design problems would have been solved. After that, with the evolution going on, feasible solution would be optimized, and global optimal solution would be found out. This paper uses a new algorithm, dynamic dominances evolutionary algorithm (DDEA), to solve antenna problems. DDEA has been tested by 22 benchmark problems. DDEA can consistently find the global optimum of all test problems with success rate 100%, while any other algorithm can't achieve such high success rate. This paper takes lower earth orbit ST5 antenna designed problem as a real world test problem. The experimental result shows: using this new model and DDEA, ST5 antenna design problem can be solved effectively. In addition the simulation result shows our evolved antennas are quite competitive with NASA's.","PeriodicalId":318989,"journal":{"name":"2009 NASA/ESA Conference on Adaptive Hardware and Systems","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114838287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We propose a field programmable gate array (FPGA) implementation for a run-time adaptable evolvable hardware classifier system. Previous implementations have been based on a high-level virtual reconfigurable circuit technique which requires many FPGA resources. We therefore apply an intermediate level reconfiguration technique which consists of using the FPGA lookup tables as shift registers for reconfiguration purposes. This leads to significant resource savings, reducing the classifier circuit size to less than one third of the original implementation. This in turn has made it possible to implement a larger, more accurate classifier than before, giving 97.5% recognition accuracy for a face image application. Experiments also show that a reduction of data element resolution can lead to further resource savings while still maintaining high classification accuracy.
{"title":"Intermediate Level FPGA Reconfiguration for an Online EHW Pattern Recognition System","authors":"K. Glette, J. Tørresen, M. Høvin","doi":"10.1109/AHS.2009.46","DOIUrl":"https://doi.org/10.1109/AHS.2009.46","url":null,"abstract":"We propose a field programmable gate array (FPGA) implementation for a run-time adaptable evolvable hardware classifier system. Previous implementations have been based on a high-level virtual reconfigurable circuit technique which requires many FPGA resources. We therefore apply an intermediate level reconfiguration technique which consists of using the FPGA lookup tables as shift registers for reconfiguration purposes. This leads to significant resource savings, reducing the classifier circuit size to less than one third of the original implementation. This in turn has made it possible to implement a larger, more accurate classifier than before, giving 97.5% recognition accuracy for a face image application. Experiments also show that a reduction of data element resolution can lead to further resource savings while still maintaining high classification accuracy.","PeriodicalId":318989,"journal":{"name":"2009 NASA/ESA Conference on Adaptive Hardware and Systems","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125436482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Kentaro Matsuo, T. Hamada, Masayuki Miyoshi, Yuichiro Shibata, K. Oguri
In this paper, we present a comparison study about implementations of phase correlation function using GPUs, ASIC and FPGAs. The Phase Only Correlation(POC) method demonstrates high robustness and subpixel accuracy in the pattern matching and the image registration. However, there is a disadvantage in computational speed because of the calculation of 2D-FFT etc. We have proposed a novel approach to accelerate POC method using GPU to solve the calculation cost problem. Using our GPU-based POC implementation, each POC calculation can be done within 2.36 milli seconds using a GPU for 256 x 256 pixels, on the other hand, within 27.15 milli seconds for Cinderella II 100 MHz (ASIC), 4.51 milli seconds for Xilinx XC2V6000 66 MHz(FPGA). These results show that, for POC calculation and FFT-based computations in general, GPUs are very competitive in terms of performance and performance figures, whereas FPGAs are competitive in terms of performance per frequency figures.
在本文中，我们比较研究了用gpu、ASIC和fpga实现相位相关函数。纯相位相关(POC)方法在模式匹配和图像配准方面具有较高的鲁棒性和亚像素精度。但是，由于二维快速傅里叶变换等问题，在计算速度上存在一定的劣势。为了解决计算成本问题，我们提出了一种利用GPU加速POC方法的新方法。使用我们基于GPU的POC实现，使用256 x 256像素的GPU，每个POC计算可以在2.36毫秒内完成，另一方面，Cinderella II 100 MHz(ASIC)在27.15毫秒内完成，Xilinx XC2V6000 66 MHz(FPGA)在4.51毫秒内完成。这些结果表明，对于POC计算和基于fft的计算，gpu在性能和性能数据方面非常有竞争力，而fpga在每频率数据方面具有竞争力。
{"title":"Accelerating Phase Correlation Functions Using GPU and FPGA","authors":"Kentaro Matsuo, T. Hamada, Masayuki Miyoshi, Yuichiro Shibata, K. Oguri","doi":"10.1109/AHS.2009.53","DOIUrl":"https://doi.org/10.1109/AHS.2009.53","url":null,"abstract":"In this paper, we present a comparison study about implementations of phase correlation function using GPUs, ASIC and FPGAs. The Phase Only Correlation(POC) method demonstrates high robustness and subpixel accuracy in the pattern matching and the image registration. However, there is a disadvantage in computational speed because of the calculation of 2D-FFT etc. We have proposed a novel approach to accelerate POC method using GPU to solve the calculation cost problem. Using our GPU-based POC implementation, each POC calculation can be done within 2.36 milli seconds using a GPU for 256 x 256 pixels, on the other hand, within 27.15 milli seconds for Cinderella II 100 MHz (ASIC), 4.51 milli seconds for Xilinx XC2V6000 66 MHz(FPGA). These results show that, for POC calculation and FFT-based computations in general, GPUs are very competitive in terms of performance and performance figures, whereas FPGAs are competitive in terms of performance per frequency figures.","PeriodicalId":318989,"journal":{"name":"2009 NASA/ESA Conference on Adaptive Hardware and Systems","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117198476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The ultimate research goal for unmanned aerial vehicles (UAVs) is to facilitate autonomy of operation.Research in the last decade has highlighted the potential of vision sensing in this regard. Although vital for accomplishment of missions assigned to any type of unmanned aerial vehicles, vision sensing is more critical for small aerial vehicles due to lack of high precision inertial sensors. In addition, uncertainty of GPS signal in indoor and urban environments calls for more reliance on vision sensing for such small vehicles. With off-line processing does not offer an attractive option in terms of autonomy, these vehicles have been challenging platforms to implement vision processing on-board due to their strict payload capacity and power budget. The strict constraints drive the need for new vision processing architectures for small unmanned aerial vehicles. Recent research has shown encouraging results with FPGA based hardware architectures. This paper reviews the bottle necks involved in implementing vision processing on-board,advocates the potential of hardware based solutions to tackle strict constraints of small unmanned aerial vehicles and finally analyzes feasibility of ASICs, Structured ASICs and FPGAs for use on future systems.
{"title":"On-Board Vision Processing for Small UAVs: Time to Rethink Strategy","authors":"Shoaib Ehsan, K. Mcdonald-Maier","doi":"10.1109/AHS.2009.6","DOIUrl":"https://doi.org/10.1109/AHS.2009.6","url":null,"abstract":"The ultimate research goal for unmanned aerial vehicles (UAVs) is to facilitate autonomy of operation.Research in the last decade has highlighted the potential of vision sensing in this regard. Although vital for accomplishment of missions assigned to any type of unmanned aerial vehicles, vision sensing is more critical for small aerial vehicles due to lack of high precision inertial sensors. In addition, uncertainty of GPS signal in indoor and urban environments calls for more reliance on vision sensing for such small vehicles. With off-line processing does not offer an attractive option in terms of autonomy, these vehicles have been challenging platforms to implement vision processing on-board due to their strict payload capacity and power budget. The strict constraints drive the need for new vision processing architectures for small unmanned aerial vehicles. Recent research has shown encouraging results with FPGA based hardware architectures. This paper reviews the bottle necks involved in implementing vision processing on-board,advocates the potential of hardware based solutions to tackle strict constraints of small unmanned aerial vehicles and finally analyzes feasibility of ASICs, Structured ASICs and FPGAs for use on future systems.","PeriodicalId":318989,"journal":{"name":"2009 NASA/ESA Conference on Adaptive Hardware and Systems","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126979713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. R. Chalamalasetti, Sohan Purohit, M. Margala, W. Vanderbauwhede
This paper presents an architecture and implementation details for MORA, a novel coarse grained reconfigurable processor for accelerating media processing applications. The MORA architecture involves a 2-D array of several such processors, to deliver low cost, high throughput performance in media processing applications. A distinguishing feature of the MORA architecture is the co-design of hardware architecture and low-level programming language throughout the design cycle. The implementation details for the single MORA processor, and benchmark evaluation using a cycle accurate simulator are presented.
{"title":"MORA - An Architecture and Programming Model for a Resource Efficient Coarse Grained Reconfigurable Processor","authors":"S. R. Chalamalasetti, Sohan Purohit, M. Margala, W. Vanderbauwhede","doi":"10.1109/AHS.2009.37","DOIUrl":"https://doi.org/10.1109/AHS.2009.37","url":null,"abstract":"This paper presents an architecture and implementation details for MORA, a novel coarse grained reconfigurable processor for accelerating media processing applications. The MORA architecture involves a 2-D array of several such processors, to deliver low cost, high throughput performance in media processing applications. A distinguishing feature of the MORA architecture is the co-design of hardware architecture and low-level programming language throughout the design cycle. The implementation details for the single MORA processor, and benchmark evaluation using a cycle accurate simulator are presented.","PeriodicalId":318989,"journal":{"name":"2009 NASA/ESA Conference on Adaptive Hardware and Systems","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122638784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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