IEEE/SEMI 1996 Advanced Semiconductor Manufacturing Conference and Workshop. Theme-Innovative Approaches to Growth in the Semiconductor Industry. ASMC 96 Proceedings最新文献
Pub Date : 1996-11-12DOI: 10.1109/ASMC.1996.558006
K. Daigle, R. Powell
In today's highly competitive: marketplace, working better, smarter, and more cost effectively is essential. The scrap created during manufacturing can either sharpen or diminish a company's competitive edge. Customers require that their orders be delivered on time with yield quality that either meets or exceeds specifications. In Hot Process, scrap and hold lots were becoming a very serious problem that affected the manufacturing team's performance, customers orders, and delivery schedule. To alleviate this problem, each project was directed to address its part of this critical defect issue. The Hot Process project with manufacturing production control, acting as an empowered self-directed group, formed a market-driven team for scrap which could help improve production yields and reduce defects. Issues identified by the team included the lack of a unified procedure for documenting scrap, wafer-handling concerns suggested by new and experienced operators, and how best to focus on single wafer scrap and the cause of that scrap, and its correction or prevention. This paper describes the team's plan (or unified assault) to increase yields by reducing defects and how a common accounting procedure was implemented to review existing departmental practices which could result in a common scrap procedure. Also addressed are the several wafer-handling issues which resulted in revised wafer-handling class that more adequately reflects the nature of today's defects and enhances operator understanding of the the underlying costs associated with how scrap affects yield. Finally, this paper discusses the measurement and reporting of our Hot Process scrap team's yield improvements and defect reductions at bimonthly meetings with management.
{"title":"Manufacturing scrap reduction team","authors":"K. Daigle, R. Powell","doi":"10.1109/ASMC.1996.558006","DOIUrl":"https://doi.org/10.1109/ASMC.1996.558006","url":null,"abstract":"In today's highly competitive: marketplace, working better, smarter, and more cost effectively is essential. The scrap created during manufacturing can either sharpen or diminish a company's competitive edge. Customers require that their orders be delivered on time with yield quality that either meets or exceeds specifications. In Hot Process, scrap and hold lots were becoming a very serious problem that affected the manufacturing team's performance, customers orders, and delivery schedule. To alleviate this problem, each project was directed to address its part of this critical defect issue. The Hot Process project with manufacturing production control, acting as an empowered self-directed group, formed a market-driven team for scrap which could help improve production yields and reduce defects. Issues identified by the team included the lack of a unified procedure for documenting scrap, wafer-handling concerns suggested by new and experienced operators, and how best to focus on single wafer scrap and the cause of that scrap, and its correction or prevention. This paper describes the team's plan (or unified assault) to increase yields by reducing defects and how a common accounting procedure was implemented to review existing departmental practices which could result in a common scrap procedure. Also addressed are the several wafer-handling issues which resulted in revised wafer-handling class that more adequately reflects the nature of today's defects and enhances operator understanding of the the underlying costs associated with how scrap affects yield. Finally, this paper discusses the measurement and reporting of our Hot Process scrap team's yield improvements and defect reductions at bimonthly meetings with management.","PeriodicalId":325204,"journal":{"name":"IEEE/SEMI 1996 Advanced Semiconductor Manufacturing Conference and Workshop. Theme-Innovative Approaches to Growth in the Semiconductor Industry. ASMC 96 Proceedings","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127225396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-12DOI: 10.1109/ASMC.1996.557974
B. Pollard, P. Betti, D. Proctor
Silicon nitride, often used to define the device active area, is a critical film with a long history in the semiconductor industry. The film is typically formed in a Low Pressure Chemical Vapor Deposition (LPCVD) reactor. As device geometries shrink below 0.5 /spl mu/m, the need for repeatable nitride particle control is essential to yielding product. Achieving consistent uptime on these LPCVD reactors is equally important to meet increasing productivity requirements. This paper demonstrates how the performance of two horizontal silicon nitride reactors was greatly improved and particle excursions were reduced through a series of process and hardware improvements developed by a team of engineers and technicians. The team started by identifying all known process and equipment failures. Next potential solutions for the failures were developed. The team utilized a systematic approach so that both technical and practical issues were addressed. The potential solutions were ranked and then implemented based on the ones which gave the most return on investment. The most significant technical problem addressed was the effect of the pumpdown delay following door seal on particle performance. Many of the solutions were associated with upgrades that reduced the time it takes for the system to begin pumping down from atmospheric pressure. As a result the number of particle excursions were reduced by a factor of three. Other hardware upgrades were done to reduce intermittent pumpdown and ventup failures. A 40% improvement was seen in the performance of the two nitride systems after the solutions were implemented.
{"title":"A systematic team approach for improving LPCVD silicon nitride reactor performance","authors":"B. Pollard, P. Betti, D. Proctor","doi":"10.1109/ASMC.1996.557974","DOIUrl":"https://doi.org/10.1109/ASMC.1996.557974","url":null,"abstract":"Silicon nitride, often used to define the device active area, is a critical film with a long history in the semiconductor industry. The film is typically formed in a Low Pressure Chemical Vapor Deposition (LPCVD) reactor. As device geometries shrink below 0.5 /spl mu/m, the need for repeatable nitride particle control is essential to yielding product. Achieving consistent uptime on these LPCVD reactors is equally important to meet increasing productivity requirements. This paper demonstrates how the performance of two horizontal silicon nitride reactors was greatly improved and particle excursions were reduced through a series of process and hardware improvements developed by a team of engineers and technicians. The team started by identifying all known process and equipment failures. Next potential solutions for the failures were developed. The team utilized a systematic approach so that both technical and practical issues were addressed. The potential solutions were ranked and then implemented based on the ones which gave the most return on investment. The most significant technical problem addressed was the effect of the pumpdown delay following door seal on particle performance. Many of the solutions were associated with upgrades that reduced the time it takes for the system to begin pumping down from atmospheric pressure. As a result the number of particle excursions were reduced by a factor of three. Other hardware upgrades were done to reduce intermittent pumpdown and ventup failures. A 40% improvement was seen in the performance of the two nitride systems after the solutions were implemented.","PeriodicalId":325204,"journal":{"name":"IEEE/SEMI 1996 Advanced Semiconductor Manufacturing Conference and Workshop. Theme-Innovative Approaches to Growth in the Semiconductor Industry. ASMC 96 Proceedings","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123798340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-12DOI: 10.1109/ASMC.1996.557970
J. Bonal, C. Ortega, L. Rios, S. Aparicio, M. Fernandez, M. Rosendo, A. Sanchez, S. Malvar
The constant increase of the capital needed for a semiconductor facility has brought a huge interest in two methodologies: Theory of Constraints (TOC) and Total Productive Maintenance (TPM) which have been shown to be adequate in optimizing the return on capital equipment. This article shows that both methodologies are convergent. The appropriate use of both together can make it possible to maintain productivity improvement rates in the semiconductor business. The Overall Equipment Efficiency (OEE) measurements are the driver metrics for an effective TPM program. OEE measurements are easy to obtain, nevertheless, the analysis of these parameters requires a large amount of accurate data that are difficult to obtain in a production environment. In addition, it needs the dedication of a considerable amount of effort and human resources to improve in all the organizations (production, maintenance, engineering, etc.). It is widely accepted that bottlenecks should be entered in a TPM program, but for non-bottlenecks, it is not easy to determine which machines should enter the program, their target and their impact on the global fab efficiency. In this study we present a systematic method of approaching this problem.
{"title":"Overall fab efficiency [semiconductor manufacturing]","authors":"J. Bonal, C. Ortega, L. Rios, S. Aparicio, M. Fernandez, M. Rosendo, A. Sanchez, S. Malvar","doi":"10.1109/ASMC.1996.557970","DOIUrl":"https://doi.org/10.1109/ASMC.1996.557970","url":null,"abstract":"The constant increase of the capital needed for a semiconductor facility has brought a huge interest in two methodologies: Theory of Constraints (TOC) and Total Productive Maintenance (TPM) which have been shown to be adequate in optimizing the return on capital equipment. This article shows that both methodologies are convergent. The appropriate use of both together can make it possible to maintain productivity improvement rates in the semiconductor business. The Overall Equipment Efficiency (OEE) measurements are the driver metrics for an effective TPM program. OEE measurements are easy to obtain, nevertheless, the analysis of these parameters requires a large amount of accurate data that are difficult to obtain in a production environment. In addition, it needs the dedication of a considerable amount of effort and human resources to improve in all the organizations (production, maintenance, engineering, etc.). It is widely accepted that bottlenecks should be entered in a TPM program, but for non-bottlenecks, it is not easy to determine which machines should enter the program, their target and their impact on the global fab efficiency. In this study we present a systematic method of approaching this problem.","PeriodicalId":325204,"journal":{"name":"IEEE/SEMI 1996 Advanced Semiconductor Manufacturing Conference and Workshop. Theme-Innovative Approaches to Growth in the Semiconductor Industry. ASMC 96 Proceedings","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117011427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-12DOI: 10.1109/ASMC.1996.558013
M. Broomfield, T. Spooner
As BEOL spacing decreases and aspect ratios increase, conventional dielectric gap filling techniques begin to lose capability. At Digital Semiconductor two different ILD gap fill processes have been evaluated for running in production. At or below 0.5 um spacing an integrated PETEOS/SACVD PETEOS gap fill process showed great variability in providing good gap fill without the creation of voids. In our 0.35 um process an HDP oxide deposition using an ECR deposition system has now replaced the PETEOS/SACVD gap fill process. While providing process simplification in the deposition tool, tool availability, integration, yield and device testing have shown that the HDP process is equally capable while providing robust void free gap fill. The HDP ECR oxide has been integrated with a conventional PECVD TEOS oxide deposition and CMP in a 4 layer metal 0.35 um process. The integration of an HDP oxide with a high throughput PETEOS deposition tool provides manufacturing with a high throughput process. CMP provides global planarization, essential for photo depth of field and integration with tungsten plug formation.
{"title":"HDP dielectric BEOL gapfill: a process for manufacturing","authors":"M. Broomfield, T. Spooner","doi":"10.1109/ASMC.1996.558013","DOIUrl":"https://doi.org/10.1109/ASMC.1996.558013","url":null,"abstract":"As BEOL spacing decreases and aspect ratios increase, conventional dielectric gap filling techniques begin to lose capability. At Digital Semiconductor two different ILD gap fill processes have been evaluated for running in production. At or below 0.5 um spacing an integrated PETEOS/SACVD PETEOS gap fill process showed great variability in providing good gap fill without the creation of voids. In our 0.35 um process an HDP oxide deposition using an ECR deposition system has now replaced the PETEOS/SACVD gap fill process. While providing process simplification in the deposition tool, tool availability, integration, yield and device testing have shown that the HDP process is equally capable while providing robust void free gap fill. The HDP ECR oxide has been integrated with a conventional PECVD TEOS oxide deposition and CMP in a 4 layer metal 0.35 um process. The integration of an HDP oxide with a high throughput PETEOS deposition tool provides manufacturing with a high throughput process. CMP provides global planarization, essential for photo depth of field and integration with tungsten plug formation.","PeriodicalId":325204,"journal":{"name":"IEEE/SEMI 1996 Advanced Semiconductor Manufacturing Conference and Workshop. Theme-Innovative Approaches to Growth in the Semiconductor Industry. ASMC 96 Proceedings","volume":"190 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126802209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-12DOI: 10.1109/ASMC.1996.557964
W. Chou, J. Everton
The simulation model described offers many different opportunities for increasing understanding of a development wafer fab. The results of simulation runs must be analyzed with an understanding of the effect of randomness on the model. Multiple random number runs might be required to confirm a model result. Simulation models can account for dynamic interactions between wafers, tools and operators. The variety of statistics can be used to better understand and interpret the model results. Simulation provides the benefit of experimenting with the fab without buying equipment. In the case of Fujitsu, production volumes were increasing. The model provided information on staffing requirements and new tool acquisitions required to support higher levels of production.
{"title":"Capacity planning for development wafer fab expansion","authors":"W. Chou, J. Everton","doi":"10.1109/ASMC.1996.557964","DOIUrl":"https://doi.org/10.1109/ASMC.1996.557964","url":null,"abstract":"The simulation model described offers many different opportunities for increasing understanding of a development wafer fab. The results of simulation runs must be analyzed with an understanding of the effect of randomness on the model. Multiple random number runs might be required to confirm a model result. Simulation models can account for dynamic interactions between wafers, tools and operators. The variety of statistics can be used to better understand and interpret the model results. Simulation provides the benefit of experimenting with the fab without buying equipment. In the case of Fujitsu, production volumes were increasing. The model provided information on staffing requirements and new tool acquisitions required to support higher levels of production.","PeriodicalId":325204,"journal":{"name":"IEEE/SEMI 1996 Advanced Semiconductor Manufacturing Conference and Workshop. Theme-Innovative Approaches to Growth in the Semiconductor Industry. ASMC 96 Proceedings","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129230100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-12DOI: 10.1109/ASMC.1996.558099
F. Lee, A. Chatterjee, D. Croley
Wafer-level defect distributions and yield patterns are a significant source of information about the performance of a manufacturing line. Computer-based techniques are ideal for pattern analysis because they provide the ability to quickly perform systematic, repetitive analyses on large data sets. The development of algorithms for computer-based spatial pattern analysis are described and initial test results are presented. Integration of automated spatial pattern analysis into the manufacturing process is discussed.
{"title":"Advanced yield enhancement: computer-based spatial pattern analysis. Part 1","authors":"F. Lee, A. Chatterjee, D. Croley","doi":"10.1109/ASMC.1996.558099","DOIUrl":"https://doi.org/10.1109/ASMC.1996.558099","url":null,"abstract":"Wafer-level defect distributions and yield patterns are a significant source of information about the performance of a manufacturing line. Computer-based techniques are ideal for pattern analysis because they provide the ability to quickly perform systematic, repetitive analyses on large data sets. The development of algorithms for computer-based spatial pattern analysis are described and initial test results are presented. Integration of automated spatial pattern analysis into the manufacturing process is discussed.","PeriodicalId":325204,"journal":{"name":"IEEE/SEMI 1996 Advanced Semiconductor Manufacturing Conference and Workshop. Theme-Innovative Approaches to Growth in the Semiconductor Industry. ASMC 96 Proceedings","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121472595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-12DOI: 10.1109/ASMC.1996.557993
D. Scott
Historically, manufacturers have had to choose between using an integrated MES system (often large, costly, monolithic, and insufficiently configurable), or using multiple point solutions (resulting in multiple databases, different user interfaces, different models, and integration nightmares). Today, manufacturers can have both. They can now purchase point solutions that are easily and seamlessly integratable.
{"title":"Comparative advantage through manufacturing execution systems","authors":"D. Scott","doi":"10.1109/ASMC.1996.557993","DOIUrl":"https://doi.org/10.1109/ASMC.1996.557993","url":null,"abstract":"Historically, manufacturers have had to choose between using an integrated MES system (often large, costly, monolithic, and insufficiently configurable), or using multiple point solutions (resulting in multiple databases, different user interfaces, different models, and integration nightmares). Today, manufacturers can have both. They can now purchase point solutions that are easily and seamlessly integratable.","PeriodicalId":325204,"journal":{"name":"IEEE/SEMI 1996 Advanced Semiconductor Manufacturing Conference and Workshop. Theme-Innovative Approaches to Growth in the Semiconductor Industry. ASMC 96 Proceedings","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115898377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-12DOI: 10.1109/ASMC.1996.558090
R. Bunkofske, N. T. Pascoe, J. Colt, M. W. Smit
This paper discusses the building, installation and integration of a data acquisition and analysis system in a semiconductor manufacturing line known as the real time process monitoring system (RTPM). It describes how it has been integrated with the site logistics system, the statistical process control system, and the characterization data base to provide improved process control, increased tool availability, and enhanced yield learning.
{"title":"Real-time process monitoring [semiconductor manufacturing line]","authors":"R. Bunkofske, N. T. Pascoe, J. Colt, M. W. Smit","doi":"10.1109/ASMC.1996.558090","DOIUrl":"https://doi.org/10.1109/ASMC.1996.558090","url":null,"abstract":"This paper discusses the building, installation and integration of a data acquisition and analysis system in a semiconductor manufacturing line known as the real time process monitoring system (RTPM). It describes how it has been integrated with the site logistics system, the statistical process control system, and the characterization data base to provide improved process control, increased tool availability, and enhanced yield learning.","PeriodicalId":325204,"journal":{"name":"IEEE/SEMI 1996 Advanced Semiconductor Manufacturing Conference and Workshop. Theme-Innovative Approaches to Growth in the Semiconductor Industry. ASMC 96 Proceedings","volume":"596 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133910887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-12DOI: 10.1109/ASMC.1996.558030
S. Abraham
A series of process tests were conducted on a high density plasma etcher to improve the etch rate loading. Etch rate loading arises mainly from two different factors which are microloading and aspect ratio dependent etch (ARDE). Microloading can be defined as the etch rate non-uniformities due to pattern density variations. ARDE can be explained as etch nonuniformities between lines with different aspect ratios. Microloading is mainly a flow dependent phenomena while ARDE shows dependence on process chemistries as well. In this study, a new chemistry is introduced for etching the titanium nitride (TiN) ARC layer. With the introduction of this new chemistry, microloading for 0.5 micron geometry is improved by almost 50% compared to the values obtained from the baseline process. The new chemistry provides approximately 5:1 selectivity to the underlying oxide, and gives very high selectivity to the aluminum layer. When using this chemistry, the etch rate of the titanium nitride layer is more than a micron per minute. Details of the improvement obtained in etch rate loading and mechanisms that explain the observed trends are provided in the current paper. Different etch chemistries as well as the new chemistry were tried for the titanium nitride ARC layer etch, and a comparative evaluation of the process performance was done based on the different chemistries. Conventional BCl/sub 3//Cl/sub 2/ chemistry was mainly used for etching the aluminum bulk layer underneath it.
{"title":"A new chemistry for a high-density plasma etcher that improves etch rate loading on the TiN ARC layer when geometries are below 0.5 micron","authors":"S. Abraham","doi":"10.1109/ASMC.1996.558030","DOIUrl":"https://doi.org/10.1109/ASMC.1996.558030","url":null,"abstract":"A series of process tests were conducted on a high density plasma etcher to improve the etch rate loading. Etch rate loading arises mainly from two different factors which are microloading and aspect ratio dependent etch (ARDE). Microloading can be defined as the etch rate non-uniformities due to pattern density variations. ARDE can be explained as etch nonuniformities between lines with different aspect ratios. Microloading is mainly a flow dependent phenomena while ARDE shows dependence on process chemistries as well. In this study, a new chemistry is introduced for etching the titanium nitride (TiN) ARC layer. With the introduction of this new chemistry, microloading for 0.5 micron geometry is improved by almost 50% compared to the values obtained from the baseline process. The new chemistry provides approximately 5:1 selectivity to the underlying oxide, and gives very high selectivity to the aluminum layer. When using this chemistry, the etch rate of the titanium nitride layer is more than a micron per minute. Details of the improvement obtained in etch rate loading and mechanisms that explain the observed trends are provided in the current paper. Different etch chemistries as well as the new chemistry were tried for the titanium nitride ARC layer etch, and a comparative evaluation of the process performance was done based on the different chemistries. Conventional BCl/sub 3//Cl/sub 2/ chemistry was mainly used for etching the aluminum bulk layer underneath it.","PeriodicalId":325204,"journal":{"name":"IEEE/SEMI 1996 Advanced Semiconductor Manufacturing Conference and Workshop. Theme-Innovative Approaches to Growth in the Semiconductor Industry. ASMC 96 Proceedings","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131771256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-12DOI: 10.1109/ASMC.1996.558035
E. E. Chain
The increasing capacity of modern wafer fabrication facilities requires automated metrology methods. Automation provides a significantly improved measurement capability, coupled with increased manufacturing throughput, compared to standard methods. Successful integration of automated metrology into the factory measurement system requires that automated functions, such as pattern recognition, display a high degree of reliability. Data is required on automation, and can be collected on every part measured, along with the collection of measurement data. Reliability data analysis permits rapid identification of automation weaknesses, leading to rapid improvements. This analysis can be applied to such in-line measurements as CD (critical dimension), overlay, particle and film thickness. Results are presented for the CD SEM (Scanning Electron Microscope).
{"title":"Automated metrology for increased throughput and reliability","authors":"E. E. Chain","doi":"10.1109/ASMC.1996.558035","DOIUrl":"https://doi.org/10.1109/ASMC.1996.558035","url":null,"abstract":"The increasing capacity of modern wafer fabrication facilities requires automated metrology methods. Automation provides a significantly improved measurement capability, coupled with increased manufacturing throughput, compared to standard methods. Successful integration of automated metrology into the factory measurement system requires that automated functions, such as pattern recognition, display a high degree of reliability. Data is required on automation, and can be collected on every part measured, along with the collection of measurement data. Reliability data analysis permits rapid identification of automation weaknesses, leading to rapid improvements. This analysis can be applied to such in-line measurements as CD (critical dimension), overlay, particle and film thickness. Results are presented for the CD SEM (Scanning Electron Microscope).","PeriodicalId":325204,"journal":{"name":"IEEE/SEMI 1996 Advanced Semiconductor Manufacturing Conference and Workshop. Theme-Innovative Approaches to Growth in the Semiconductor Industry. ASMC 96 Proceedings","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124123762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
IEEE/SEMI 1996 Advanced Semiconductor Manufacturing Conference and Workshop. Theme-Innovative Approaches to Growth in the Semiconductor Industry. ASMC 96 Proceedings
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