Cryptography is basically securing the data during the communication between different systems. To provide the security of data during communication in cryptography we together require the Algorithm and Key. The confidentiality and integrity of the data during communication depends partially on algorithm and partially on key. Due to human memorizability the size of key in cryptography is limited. 2Dimension graphics image have the property that by visualising or by listening its dimension it is not possible to design exactly the same pattern. In this paper a modified approach is being proposed for increasing the security of the data. For increasing the security we are basically concentrating on the key part of the cryptography we basically uses the 2Dimension graphics image which is designed by the user. 2Dimension Graphics image is composed of pixels in which each pixel have different or same ASCII value. From the large collection of pixel the proposed algorithm will generate any size of key which can be used in encryption as well as in decryption.
{"title":"A Modified Approach of Key Manipulation in Cryptography Using 2D Graphics Image","authors":"Pratik Shrivastava, Retesh Jain, K. Raghuwanshi","doi":"10.1109/ICESC.2014.40","DOIUrl":"https://doi.org/10.1109/ICESC.2014.40","url":null,"abstract":"Cryptography is basically securing the data during the communication between different systems. To provide the security of data during communication in cryptography we together require the Algorithm and Key. The confidentiality and integrity of the data during communication depends partially on algorithm and partially on key. Due to human memorizability the size of key in cryptography is limited. 2Dimension graphics image have the property that by visualising or by listening its dimension it is not possible to design exactly the same pattern. In this paper a modified approach is being proposed for increasing the security of the data. For increasing the security we are basically concentrating on the key part of the cryptography we basically uses the 2Dimension graphics image which is designed by the user. 2Dimension Graphics image is composed of pixels in which each pixel have different or same ASCII value. From the large collection of pixel the proposed algorithm will generate any size of key which can be used in encryption as well as in decryption.","PeriodicalId":335267,"journal":{"name":"2014 International Conference on Electronic Systems, Signal Processing and Computing Technologies","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115845271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Data mining is a knowledge discovery technique, used for exploring the new facts and relationships among data. It enables a user to uncover hidden information among available datasets. Cluster detection is one of the major techniques, which is used for data mining. In the Cluster detection techniques, User performs mining of data by searching for cluster of elements that are similar to each other. Each implementation of the cluster detection techniques adopts a method of comparing the value of individual datasets with those in their centroids. So, in this paper we have enlisted a few of them. Based on certain parameters, we have carried out a comprehensive analysis of various clustering techniques.
{"title":"A Comparative Analysis of Various Cluster Detection Techniques for Data Mining","authors":"Prashant Vats, Manju Mandot, A. Gosain","doi":"10.1109/ICESC.2014.67","DOIUrl":"https://doi.org/10.1109/ICESC.2014.67","url":null,"abstract":"Data mining is a knowledge discovery technique, used for exploring the new facts and relationships among data. It enables a user to uncover hidden information among available datasets. Cluster detection is one of the major techniques, which is used for data mining. In the Cluster detection techniques, User performs mining of data by searching for cluster of elements that are similar to each other. Each implementation of the cluster detection techniques adopts a method of comparing the value of individual datasets with those in their centroids. So, in this paper we have enlisted a few of them. Based on certain parameters, we have carried out a comprehensive analysis of various clustering techniques.","PeriodicalId":335267,"journal":{"name":"2014 International Conference on Electronic Systems, Signal Processing and Computing Technologies","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128260456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As the technology is developing with a huge rate, the functionality of smartphone is also getting higher. But the smartphones have some resource constraints like processing power, battery capacity, limited bandwidth for connecting to the Internet, etc. Therefore, to improve the performance of smartphone in terms of processing power, battery and memory, the technology namely, augmented execution is the best solution in the mobile cloud computing (MCC) scenario. Mobile cloud computing works as the combination of mobile computing and cloud computing. Augmented execution alleviates the problem of resource scarcity of smartphone. To get the benefits from the resource-abundant clouds, massive computation intensive tasks are partitioned and migrated to the cloud side for the execution. After executing the task at the cloud side, the results are sent back to the smartphone. This method is called as the computation offloading. The given survey paper focuses on the partitioning techniques in mobile cloud computing.
{"title":"Augmented Execution in Mobile Cloud Computing: A Survey","authors":"V. Jagtap, Karishma Pawar, Ajeet Ram Pathak","doi":"10.1109/ICESC.2014.46","DOIUrl":"https://doi.org/10.1109/ICESC.2014.46","url":null,"abstract":"As the technology is developing with a huge rate, the functionality of smartphone is also getting higher. But the smartphones have some resource constraints like processing power, battery capacity, limited bandwidth for connecting to the Internet, etc. Therefore, to improve the performance of smartphone in terms of processing power, battery and memory, the technology namely, augmented execution is the best solution in the mobile cloud computing (MCC) scenario. Mobile cloud computing works as the combination of mobile computing and cloud computing. Augmented execution alleviates the problem of resource scarcity of smartphone. To get the benefits from the resource-abundant clouds, massive computation intensive tasks are partitioned and migrated to the cloud side for the execution. After executing the task at the cloud side, the results are sent back to the smartphone. This method is called as the computation offloading. The given survey paper focuses on the partitioning techniques in mobile cloud computing.","PeriodicalId":335267,"journal":{"name":"2014 International Conference on Electronic Systems, Signal Processing and Computing Technologies","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130288916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A file system is used for the organization, storage, retrieval, naming, sharing, and protection of files. Distributed file system has certain degrees of transparency to the user and the system such as access transparency, [2] location transparency, failure transparency, heterogeneity, replication transparency etc. [1][2] NFS (Network File System), RFS (Remote File Sharing), Andrew File System (AFS) are examples of Distributed file system. Distributed file systems are generally used for cloud computing applications based on [4] the MapReduce programming model. A MapReduce program consist of a Map () procedure that performs filtering and a Reduce () procedure that performs a summary operation. However, in a cloud computing environment, sometimes failure is occurs and nodes may be upgraded, replaced, and added in the system. Therefore load imbalanced problem arises. To solve this problem, load rebalancing algorithm is implemented in this paper so that central node should not overloaded. The implementation is done in hadoop distributed file system. As apache hadoop is used, security issues are arises. To solve these security issues and to increase security, [17]Kerberos authentication protocol is implemented to handle multiple nodes. This paper shows real time implementation experiment on cluster.
{"title":"An Approach to Balance the Load with Security for Distributed File System in Cloud","authors":"Vidya N. Chiwande, Animesh R. Tayal","doi":"10.1109/ICESC.2014.51","DOIUrl":"https://doi.org/10.1109/ICESC.2014.51","url":null,"abstract":"A file system is used for the organization, storage, retrieval, naming, sharing, and protection of files. Distributed file system has certain degrees of transparency to the user and the system such as access transparency, [2] location transparency, failure transparency, heterogeneity, replication transparency etc. [1][2] NFS (Network File System), RFS (Remote File Sharing), Andrew File System (AFS) are examples of Distributed file system. Distributed file systems are generally used for cloud computing applications based on [4] the MapReduce programming model. A MapReduce program consist of a Map () procedure that performs filtering and a Reduce () procedure that performs a summary operation. However, in a cloud computing environment, sometimes failure is occurs and nodes may be upgraded, replaced, and added in the system. Therefore load imbalanced problem arises. To solve this problem, load rebalancing algorithm is implemented in this paper so that central node should not overloaded. The implementation is done in hadoop distributed file system. As apache hadoop is used, security issues are arises. To solve these security issues and to increase security, [17]Kerberos authentication protocol is implemented to handle multiple nodes. This paper shows real time implementation experiment on cluster.","PeriodicalId":335267,"journal":{"name":"2014 International Conference on Electronic Systems, Signal Processing and Computing Technologies","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132563260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In applications such as music information and database retrieval systems, classification of musical instruments plays an important role. The proposed work presents automatic classification of Indian Classical instruments based on spectral and MFCC features using well trained back propogation neural network classifier. Musical instruments such as Harmonium, Santo or and Tabla are considered for an experimentation. The spectral features such as amplitude and spectral range along with Mel Frequency Cepstrum Coefficients are considered as features. Being features are not distinguished, classification is done using non parametric classifiers such as neural networks. Being number of cepstrum coefficients are large important coefficients are selected using Principal Component Analysis. It has been observed that using 42 samples for training and 18 for testing, back propogation neural network provides accuracy of 98%. The present work can be extended for more number of Hindustani and Carnitic classical musical Instruments.
{"title":"Classification of Indian Classical Instruments Using Spectral and Principal Component Analysis Based Cepstrum Features","authors":"Sneha Gaikwad, A. Chitre, Y. Dandawate","doi":"10.1109/ICESC.2014.52","DOIUrl":"https://doi.org/10.1109/ICESC.2014.52","url":null,"abstract":"In applications such as music information and database retrieval systems, classification of musical instruments plays an important role. The proposed work presents automatic classification of Indian Classical instruments based on spectral and MFCC features using well trained back propogation neural network classifier. Musical instruments such as Harmonium, Santo or and Tabla are considered for an experimentation. The spectral features such as amplitude and spectral range along with Mel Frequency Cepstrum Coefficients are considered as features. Being features are not distinguished, classification is done using non parametric classifiers such as neural networks. Being number of cepstrum coefficients are large important coefficients are selected using Principal Component Analysis. It has been observed that using 42 samples for training and 18 for testing, back propogation neural network provides accuracy of 98%. The present work can be extended for more number of Hindustani and Carnitic classical musical Instruments.","PeriodicalId":335267,"journal":{"name":"2014 International Conference on Electronic Systems, Signal Processing and Computing Technologies","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132565830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Wireless Sensor Networks represents a new pattern for extracting the data from the environment for many agricultural, industrial and scientific applications. Data gathering protocols are formulated for configuring the network and collecting the information from the desired environment. Sensors have limited battery power and the communication module consumes the maximum power in the sensors. A key challenging issue in case of wireless sensor networks is to decide on a fixed pattern for the purpose of data collection. For this it is very important to schedule the various activities of the sensors which would lead to the reduction in the energy consumption by the network as a whole. In this paper we have focused on two major aspects. One is the construction of data gathering tree and the other is the energy efficient scheduling. Here we have proposed a scheduling strategy which makes use of TDMA and schedules the activities of a subset of a sensors into different groups with successive time slots thereby reducing the state transition and hence the energy consumption. The proposed scheduling algorithm has been simulated in NS-2.32 and the performance has been evaluated on the various performance metrics of Wireless Sensor Networks. The simulation result shows that our proposed scheduling strategy improves the performance metrics like Delivery Ratio and Energy as compared to the traditional method of scheduling.
{"title":"Energy Efficient Scheduling Strategy for Data Collection in Wireless Sensor Networks","authors":"Prerana Shrivastava, S. Pokle","doi":"10.1109/ICESC.2014.35","DOIUrl":"https://doi.org/10.1109/ICESC.2014.35","url":null,"abstract":"Wireless Sensor Networks represents a new pattern for extracting the data from the environment for many agricultural, industrial and scientific applications. Data gathering protocols are formulated for configuring the network and collecting the information from the desired environment. Sensors have limited battery power and the communication module consumes the maximum power in the sensors. A key challenging issue in case of wireless sensor networks is to decide on a fixed pattern for the purpose of data collection. For this it is very important to schedule the various activities of the sensors which would lead to the reduction in the energy consumption by the network as a whole. In this paper we have focused on two major aspects. One is the construction of data gathering tree and the other is the energy efficient scheduling. Here we have proposed a scheduling strategy which makes use of TDMA and schedules the activities of a subset of a sensors into different groups with successive time slots thereby reducing the state transition and hence the energy consumption. The proposed scheduling algorithm has been simulated in NS-2.32 and the performance has been evaluated on the various performance metrics of Wireless Sensor Networks. The simulation result shows that our proposed scheduling strategy improves the performance metrics like Delivery Ratio and Energy as compared to the traditional method of scheduling.","PeriodicalId":335267,"journal":{"name":"2014 International Conference on Electronic Systems, Signal Processing and Computing Technologies","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131697769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Power converters exhibiting higher efficiency, faster response and better control is need of the day. Sophisticated control algorithms are required for the implementation of these converters. This has increased the use of digital controllers in power system and power electronics applications. Selection of a digital controller for power control application is a challenge as there are variety of architectures, specifications, development platforms and design requirements. A right selection is possible only if the application requirements and digital controller capabilities are exactly known. This paper is an attempt to discuss the different aspects of digital controller required for power applications. In initial part of the paper, review of various power system and power electronics applications requiring the digital controller has been taken while the later part of the paper discusses about digital controller specifications to be considered.
{"title":"Selection of Digital Controller for Power System and Power Electronics Applications","authors":"U. Mujumdar, D. R. Tutkane","doi":"10.1109/ICESC.2014.97","DOIUrl":"https://doi.org/10.1109/ICESC.2014.97","url":null,"abstract":"Power converters exhibiting higher efficiency, faster response and better control is need of the day. Sophisticated control algorithms are required for the implementation of these converters. This has increased the use of digital controllers in power system and power electronics applications. Selection of a digital controller for power control application is a challenge as there are variety of architectures, specifications, development platforms and design requirements. A right selection is possible only if the application requirements and digital controller capabilities are exactly known. This paper is an attempt to discuss the different aspects of digital controller required for power applications. In initial part of the paper, review of various power system and power electronics applications requiring the digital controller has been taken while the later part of the paper discusses about digital controller specifications to be considered.","PeriodicalId":335267,"journal":{"name":"2014 International Conference on Electronic Systems, Signal Processing and Computing Technologies","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130871509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Pandey, A. Karmakar, C. Shekhar, S. Gurunarayanan
Emerging embedded system applications require low power, fast and area-efficient implementation of complex arithmetic operations. Modern field-programmable gate array (FPGA) is a suitable candidate for implementing any reasonably complex architecture within minimal design time. Apart from the logic resources, most of the FPGAs contain hard-macro elements. By using a fixed-point data path, the available FPGA macro elements can be used to design an architecture that is much more complex. The realization of the complex arithmetic elements can be simpler by using a logarithmic number system. In this paper, a novel architecture and the FPGA realization of an antilogarithmic computing circuit is proposed. The proposed antilogarithmic circuit uses piecewise linear approximation method. The same architecture works for both the positive and negative binary numbers. A unique barrel-shifter is designed which shifts the input data to the left or right by the required amount. The proposed architecture is implemented in the Xilinx Virtex-5 xc5vfx70t device. The device utilization shows that the architecture utilizes a minimal FPGA resource. We have also performed error analysis of the approximation result. The error analysis shows that error associated with the positive numbers is 0.16% while that for the negative numbers is 0.8%. The error can be further minimized by taking more bits for the fractional bit representation.
{"title":"An FPGA-Based Novel Architecture for the Fixed-Point Binary Antilogarithmic Computation","authors":"J. Pandey, A. Karmakar, C. Shekhar, S. Gurunarayanan","doi":"10.1109/ICESC.2014.13","DOIUrl":"https://doi.org/10.1109/ICESC.2014.13","url":null,"abstract":"Emerging embedded system applications require low power, fast and area-efficient implementation of complex arithmetic operations. Modern field-programmable gate array (FPGA) is a suitable candidate for implementing any reasonably complex architecture within minimal design time. Apart from the logic resources, most of the FPGAs contain hard-macro elements. By using a fixed-point data path, the available FPGA macro elements can be used to design an architecture that is much more complex. The realization of the complex arithmetic elements can be simpler by using a logarithmic number system. In this paper, a novel architecture and the FPGA realization of an antilogarithmic computing circuit is proposed. The proposed antilogarithmic circuit uses piecewise linear approximation method. The same architecture works for both the positive and negative binary numbers. A unique barrel-shifter is designed which shifts the input data to the left or right by the required amount. The proposed architecture is implemented in the Xilinx Virtex-5 xc5vfx70t device. The device utilization shows that the architecture utilizes a minimal FPGA resource. We have also performed error analysis of the approximation result. The error analysis shows that error associated with the positive numbers is 0.16% while that for the negative numbers is 0.8%. The error can be further minimized by taking more bits for the fractional bit representation.","PeriodicalId":335267,"journal":{"name":"2014 International Conference on Electronic Systems, Signal Processing and Computing Technologies","volume":"229 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122580100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper we describe specific application of digital watermarking: Video watermarking for Copyright protection. Literature survey suggests that most video watermarking techniques use static 3D Discrete Cosine Transform technique. In this paper, we show the result of implementation of static 3 D DCT. We observe that this scheme works well on correlated videos. But it does not take care of scene change in the video. Hence we propose dynamic size 3D-DCT technique (by "scene change detection") for embedding binary/ gray scale/ color watermark on a color digital video and compare our results with existing fixed length 3D-DCT technique.
{"title":"Digital Watermarking in Video for Copyright Protection","authors":"Anita Jadhav, Megha M. Kolhekar","doi":"10.1109/ICESC.2014.29","DOIUrl":"https://doi.org/10.1109/ICESC.2014.29","url":null,"abstract":"In this paper we describe specific application of digital watermarking: Video watermarking for Copyright protection. Literature survey suggests that most video watermarking techniques use static 3D Discrete Cosine Transform technique. In this paper, we show the result of implementation of static 3 D DCT. We observe that this scheme works well on correlated videos. But it does not take care of scene change in the video. Hence we propose dynamic size 3D-DCT technique (by \"scene change detection\") for embedding binary/ gray scale/ color watermark on a color digital video and compare our results with existing fixed length 3D-DCT technique.","PeriodicalId":335267,"journal":{"name":"2014 International Conference on Electronic Systems, Signal Processing and Computing Technologies","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123321525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Performance optimization of communication networks with quality of services (QOS) considerations for all active users is highly desirable. The growth of wireless multimedia applications requires high-speed and reliable communication over wireless channels of system. Throughput and fairness are important conflicting performance parameter in resource allocation for non-cooperative and cooperative OFDMA system for downlink transmission. Maximize the system throughput creates problem of unfairness among all user and while maintaining fairness, system throughput will degrade accordingly. In this paper, we proposed algorithm to provide a balanced approach to maintain throughput and fairness in the system and we designed the resources allocation algorithm for cooperative OFDMA system for downlink transmission, that algorithm maintain the fairness among the all user without affecting the throughput of the system. Our proposed subcarrier allocation fills the gap between the fairness-oriented and throughput-oriented algorithms and provides a balanced solution for subcarrier allocation in the system.
{"title":"Strategic Subcarrier Allocation for Cooperative OFDMA Relaying Network","authors":"S. Lande, S. P. Shende, S. Pathak","doi":"10.1109/ICESC.2014.37","DOIUrl":"https://doi.org/10.1109/ICESC.2014.37","url":null,"abstract":"Performance optimization of communication networks with quality of services (QOS) considerations for all active users is highly desirable. The growth of wireless multimedia applications requires high-speed and reliable communication over wireless channels of system. Throughput and fairness are important conflicting performance parameter in resource allocation for non-cooperative and cooperative OFDMA system for downlink transmission. Maximize the system throughput creates problem of unfairness among all user and while maintaining fairness, system throughput will degrade accordingly. In this paper, we proposed algorithm to provide a balanced approach to maintain throughput and fairness in the system and we designed the resources allocation algorithm for cooperative OFDMA system for downlink transmission, that algorithm maintain the fairness among the all user without affecting the throughput of the system. Our proposed subcarrier allocation fills the gap between the fairness-oriented and throughput-oriented algorithms and provides a balanced solution for subcarrier allocation in the system.","PeriodicalId":335267,"journal":{"name":"2014 International Conference on Electronic Systems, Signal Processing and Computing Technologies","volume":"232 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116203334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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