Pub Date : 1995-03-05DOI: 10.1109/APEC.1995.469094
P.F. Kocybik, K. N. Bateson
The paper describes the design and realization of a digital controller for a DC-DC power converter with zero-voltage switching (ZVS). The chosen power converter, usually called the phase-shifted bridge, is valuable because it combines advantages from both conventional PWM and resonant-mode power converters. It is therefore an important topology for investigating the advantages of digital control for DC-DC power converters. The power converter's control equations are nonlinear. The paper explains how the digital technique simplifies the separation of large-signal and small-signal control of the power converter. The loop updates at 25 kHz, and experimental results show the dynamic response achieved.<>
{"title":"Digital control of a ZVS full-bridge DC-DC converter","authors":"P.F. Kocybik, K. N. Bateson","doi":"10.1109/APEC.1995.469094","DOIUrl":"https://doi.org/10.1109/APEC.1995.469094","url":null,"abstract":"The paper describes the design and realization of a digital controller for a DC-DC power converter with zero-voltage switching (ZVS). The chosen power converter, usually called the phase-shifted bridge, is valuable because it combines advantages from both conventional PWM and resonant-mode power converters. It is therefore an important topology for investigating the advantages of digital control for DC-DC power converters. The power converter's control equations are nonlinear. The paper explains how the digital technique simplifies the separation of large-signal and small-signal control of the power converter. The loop updates at 25 kHz, and experimental results show the dynamic response achieved.<<ETX>>","PeriodicalId":335367,"journal":{"name":"Proceedings of 1995 IEEE Applied Power Electronics Conference and Exposition - APEC'95","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115905316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-03-05DOI: 10.1109/APEC.1995.468975
K. Sridhar
A model defines the relationships amongst the parameters which govern the behavior of a system over the operating range of interest. This paper presents magnetic, electrical and electro-mechanical models to support the design of slotless, star-wound, permanent-magnet synchronous motor drives. Modeling assumptions and limitations are discussed. The validity of these models, under the given assumptions, is established by reverse engineering an existing motor and comparing its measured performance with the model predictions, and through comparison with the results of a two-dimensional finite-element analysis program.<>
{"title":"Electromagnetic models for slotless PM synchronous motor drives","authors":"K. Sridhar","doi":"10.1109/APEC.1995.468975","DOIUrl":"https://doi.org/10.1109/APEC.1995.468975","url":null,"abstract":"A model defines the relationships amongst the parameters which govern the behavior of a system over the operating range of interest. This paper presents magnetic, electrical and electro-mechanical models to support the design of slotless, star-wound, permanent-magnet synchronous motor drives. Modeling assumptions and limitations are discussed. The validity of these models, under the given assumptions, is established by reverse engineering an existing motor and comparing its measured performance with the model predictions, and through comparison with the results of a two-dimensional finite-element analysis program.<<ETX>>","PeriodicalId":335367,"journal":{"name":"Proceedings of 1995 IEEE Applied Power Electronics Conference and Exposition - APEC'95","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117260979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-03-05DOI: 10.1109/APEC.1995.469032
K. Siri, I. Batarseh, J. Banda
A zero-voltage switching (ZVS), current-fed, single-ended DC-to-AC power converter with output isolation, symmetrical AC output voltage and transformer volt-second balance is proposed. Using variable switching frequency control and operating its two active complementary switches at 50% duty ratio, the power converter regulates output power via an LCC resonant link circuit. ZVS is achieved by a resonant circuit mainly formed by the switch parasitic capacitance and transformer magnetizing inductance. Continuous input current and near-sinusoidal output voltage and current result in low electromagnetic interference.<>
{"title":"Variable frequency-controlled, zero-voltage switching, current-fed, single-ended DC-to-AC converter with output isolation","authors":"K. Siri, I. Batarseh, J. Banda","doi":"10.1109/APEC.1995.469032","DOIUrl":"https://doi.org/10.1109/APEC.1995.469032","url":null,"abstract":"A zero-voltage switching (ZVS), current-fed, single-ended DC-to-AC power converter with output isolation, symmetrical AC output voltage and transformer volt-second balance is proposed. Using variable switching frequency control and operating its two active complementary switches at 50% duty ratio, the power converter regulates output power via an LCC resonant link circuit. ZVS is achieved by a resonant circuit mainly formed by the switch parasitic capacitance and transformer magnetizing inductance. Continuous input current and near-sinusoidal output voltage and current result in low electromagnetic interference.<<ETX>>","PeriodicalId":335367,"journal":{"name":"Proceedings of 1995 IEEE Applied Power Electronics Conference and Exposition - APEC'95","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125563309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-03-05DOI: 10.1109/APEC.1995.468983
J. Salmon
This paper examines the performance of a unity power factor AC/DC buck-boost rectifier operated with a nonisolated split DC-rail output voltage using one switch and one magnetic core. The rectifier topologies described can supply energy to both DC-rails in both half-cycles of the AC-supply and automatically compensate for a load imbalance between the upper and lower output DC rails. During a half-cycle of the AC supply, the power flow balance between the two DC-rails is affected by the per-unit winding leakage inductance. This paper uses extensive simulation and experimental results to illustrate the operation of the various circuit topologies and to determine the relationship between the half-cycle power flow imbalance to each DC-rail and the winding leakage inductance. This relationship is obtained for balanced and differential loads across the two DC rails and related to the magnitude of the leakage inductance.<>
{"title":"Performance of a 1-phase buck-boost rectifier using two coupled windings and a split DC-rail output voltage","authors":"J. Salmon","doi":"10.1109/APEC.1995.468983","DOIUrl":"https://doi.org/10.1109/APEC.1995.468983","url":null,"abstract":"This paper examines the performance of a unity power factor AC/DC buck-boost rectifier operated with a nonisolated split DC-rail output voltage using one switch and one magnetic core. The rectifier topologies described can supply energy to both DC-rails in both half-cycles of the AC-supply and automatically compensate for a load imbalance between the upper and lower output DC rails. During a half-cycle of the AC supply, the power flow balance between the two DC-rails is affected by the per-unit winding leakage inductance. This paper uses extensive simulation and experimental results to illustrate the operation of the various circuit topologies and to determine the relationship between the half-cycle power flow imbalance to each DC-rail and the winding leakage inductance. This relationship is obtained for balanced and differential loads across the two DC rails and related to the magnitude of the leakage inductance.<<ETX>>","PeriodicalId":335367,"journal":{"name":"Proceedings of 1995 IEEE Applied Power Electronics Conference and Exposition - APEC'95","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128131362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-03-05DOI: 10.1109/APEC.1995.469087
D. Maksimović, Y. Jang, R. Erickson
Novel nonlinear-carrier (NLC) controllers are proposed for high-power-factor boost rectifiers. In the NLC controllers, the switch duty ratio is determined by comparing a signal derived from the main switch current with a periodic, nonlinear carrier waveform. As a result, the average input current follows the input line voltage. The technique is suitable for boost power converters operating in the continuous conduction mode. Input voltage sensing, the error amplifier in the current-shaping loop, and the multiplier/divider circuitry in the voltage feedback loop are eliminated. The current-shaping is based on switch (as opposed to inductor) current sensing. The NLC controllers offer comparable or improved performance over existing schemes, and are well-suited for simple integrated-circuit implementation. Experimental verification on a 240 W rectifier is described.<>
{"title":"Nonlinear-carrier control for high power factor boost rectifiers","authors":"D. Maksimović, Y. Jang, R. Erickson","doi":"10.1109/APEC.1995.469087","DOIUrl":"https://doi.org/10.1109/APEC.1995.469087","url":null,"abstract":"Novel nonlinear-carrier (NLC) controllers are proposed for high-power-factor boost rectifiers. In the NLC controllers, the switch duty ratio is determined by comparing a signal derived from the main switch current with a periodic, nonlinear carrier waveform. As a result, the average input current follows the input line voltage. The technique is suitable for boost power converters operating in the continuous conduction mode. Input voltage sensing, the error amplifier in the current-shaping loop, and the multiplier/divider circuitry in the voltage feedback loop are eliminated. The current-shaping is based on switch (as opposed to inductor) current sensing. The NLC controllers offer comparable or improved performance over existing schemes, and are well-suited for simple integrated-circuit implementation. Experimental verification on a 240 W rectifier is described.<<ETX>>","PeriodicalId":335367,"journal":{"name":"Proceedings of 1995 IEEE Applied Power Electronics Conference and Exposition - APEC'95","volume":"392 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133544611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-03-05DOI: 10.1109/APEC.1995.469098
Jung-hui Cheng, A. Witulski
A new method for steady state design of current-programmed-mode (CPM) DC/DC converters is presented. The method uses a set of equations derived based on the relationships between line voltage, load current, control current and the stabilizing artificial ramp. The set of normalized equations are verified by a fast large-signal simulation and experimental measurement. These equations are plotted on the converter DC output plane (a graph of output current versus output voltage) in which characteristic curves related to different artificial ramps and boundaries of different operating modes are indicated. A general design procedure is presented for a CPM converter with both input voltage and output resistive load varied. By this means, the design time can be significantly reduced and systematic design trade-offs can be made to ensure correct converter operation over the desired range of line and load variation.<>
{"title":"Steady-state and large-signal design of current-programmed DC-to-DC converters","authors":"Jung-hui Cheng, A. Witulski","doi":"10.1109/APEC.1995.469098","DOIUrl":"https://doi.org/10.1109/APEC.1995.469098","url":null,"abstract":"A new method for steady state design of current-programmed-mode (CPM) DC/DC converters is presented. The method uses a set of equations derived based on the relationships between line voltage, load current, control current and the stabilizing artificial ramp. The set of normalized equations are verified by a fast large-signal simulation and experimental measurement. These equations are plotted on the converter DC output plane (a graph of output current versus output voltage) in which characteristic curves related to different artificial ramps and boundaries of different operating modes are indicated. A general design procedure is presented for a CPM converter with both input voltage and output resistive load varied. By this means, the design time can be significantly reduced and systematic design trade-offs can be made to ensure correct converter operation over the desired range of line and load variation.<<ETX>>","PeriodicalId":335367,"journal":{"name":"Proceedings of 1995 IEEE Applied Power Electronics Conference and Exposition - APEC'95","volume":"8 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132611164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-03-05DOI: 10.1109/APEC.1995.469038
E. Mehl, I. Barbi
A new method to improve the power factor of three-phase rectifiers is introduced in this paper. The main features of the proposed circuit are low cost, small size, high efficiency and simplicity. The power factor improvement is achieved with three bidirectional active switches rated at a small fraction of the total processed power, and gated at the line frequency. Principle of operation and design procedure, with practical examples are also presented. The theoretical analysis was validated with experimental results from a laboratory prototype rated at 6.4 kW and connected to the 220 V, 60 Hz AC system. The same circuit was also used in another prototype rated at 12 kW, with similar results.<>
{"title":"An improved high power factor and low cost three-phase rectifier","authors":"E. Mehl, I. Barbi","doi":"10.1109/APEC.1995.469038","DOIUrl":"https://doi.org/10.1109/APEC.1995.469038","url":null,"abstract":"A new method to improve the power factor of three-phase rectifiers is introduced in this paper. The main features of the proposed circuit are low cost, small size, high efficiency and simplicity. The power factor improvement is achieved with three bidirectional active switches rated at a small fraction of the total processed power, and gated at the line frequency. Principle of operation and design procedure, with practical examples are also presented. The theoretical analysis was validated with experimental results from a laboratory prototype rated at 6.4 kW and connected to the 220 V, 60 Hz AC system. The same circuit was also used in another prototype rated at 12 kW, with similar results.<<ETX>>","PeriodicalId":335367,"journal":{"name":"Proceedings of 1995 IEEE Applied Power Electronics Conference and Exposition - APEC'95","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134230566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-03-05DOI: 10.1109/APEC.1995.469060
G. Kamath, N. Mohan, V. Albertson
This paper presents the hardware results of a new active filter topology with reduced VA rating for 3-phase, 4-wire loads. The scheme consists of a single-phase inverter connected between the zig-zag transformer neutral and the utility neutral in addition to a three-phase inverter connected to the delta winding of the zig-zag transformer. Compared to other reported schemes, the inverter VA rating in this scheme is reduced by a factor of six. This reduction in the inverter VA rating is mainly due to the zero-sequence current inverter having a low VA rating. The equations for this active filter are derived. The simulation results are verified by means of experimental results from a proof-of-concept prototype.<>
{"title":"Hardware implementation of a novel, reduced rating active filter for 3-phase, 4-wire loads","authors":"G. Kamath, N. Mohan, V. Albertson","doi":"10.1109/APEC.1995.469060","DOIUrl":"https://doi.org/10.1109/APEC.1995.469060","url":null,"abstract":"This paper presents the hardware results of a new active filter topology with reduced VA rating for 3-phase, 4-wire loads. The scheme consists of a single-phase inverter connected between the zig-zag transformer neutral and the utility neutral in addition to a three-phase inverter connected to the delta winding of the zig-zag transformer. Compared to other reported schemes, the inverter VA rating in this scheme is reduced by a factor of six. This reduction in the inverter VA rating is mainly due to the zero-sequence current inverter having a low VA rating. The equations for this active filter are derived. The simulation results are verified by means of experimental results from a proof-of-concept prototype.<<ETX>>","PeriodicalId":335367,"journal":{"name":"Proceedings of 1995 IEEE Applied Power Electronics Conference and Exposition - APEC'95","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133022684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-03-05DOI: 10.1109/APEC.1995.468980
M. Bilgiç, V. Ozbulur, A. Sabanoviç
This paper presents a simple technique to minimize torque ripple of a switched reluctance motor. The technique is based on the control of the sum of the square of the phase currents by using only two current sensors and analog multipliers. The simulation results and a proposed circuit are given. The advantages and its limitations of the proposed circuit are explained.<>
{"title":"Torque ripple minimization of a switched reluctance motor","authors":"M. Bilgiç, V. Ozbulur, A. Sabanoviç","doi":"10.1109/APEC.1995.468980","DOIUrl":"https://doi.org/10.1109/APEC.1995.468980","url":null,"abstract":"This paper presents a simple technique to minimize torque ripple of a switched reluctance motor. The technique is based on the control of the sum of the square of the phase currents by using only two current sensors and analog multipliers. The simulation results and a proposed circuit are given. The advantages and its limitations of the proposed circuit are explained.<<ETX>>","PeriodicalId":335367,"journal":{"name":"Proceedings of 1995 IEEE Applied Power Electronics Conference and Exposition - APEC'95","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121839960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-03-05DOI: 10.1109/APEC.1995.469010
A. Hava, T. Lipo, W. L. Erdman
This paper examines the interface issues which occur when pulse width modulated (PWM) voltage source power converters (VSCs) are connected to the utility. In particular, it investigates the line current total harmonic distortion (THD) characteristics of various current regulated PWM (CRPWM) techniques with constraints on the power converter average switching frequency (power converter efficiency) and passive filter size (filter cost). Various CRPWM methods with proper filter and controller structures have been studied and evaluated by means of computer simulations for the utility interface with a variable speed wind turbine generating system. Dynamic performance has been evaluated as well as the steady state light load, full load, leading, lagging and unity power factor operating conditions.<>
{"title":"Utility interface issues for line connected PWM voltage source converters: a comparative study","authors":"A. Hava, T. Lipo, W. L. Erdman","doi":"10.1109/APEC.1995.469010","DOIUrl":"https://doi.org/10.1109/APEC.1995.469010","url":null,"abstract":"This paper examines the interface issues which occur when pulse width modulated (PWM) voltage source power converters (VSCs) are connected to the utility. In particular, it investigates the line current total harmonic distortion (THD) characteristics of various current regulated PWM (CRPWM) techniques with constraints on the power converter average switching frequency (power converter efficiency) and passive filter size (filter cost). Various CRPWM methods with proper filter and controller structures have been studied and evaluated by means of computer simulations for the utility interface with a variable speed wind turbine generating system. Dynamic performance has been evaluated as well as the steady state light load, full load, leading, lagging and unity power factor operating conditions.<<ETX>>","PeriodicalId":335367,"journal":{"name":"Proceedings of 1995 IEEE Applied Power Electronics Conference and Exposition - APEC'95","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114035163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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