Pub Date : 2016-04-01DOI: 10.1109/RTAS.2016.7461353
Ankit Agrawal, G. Fohler, Jan Nowotsch, S. Uhrig, M. Paulitsch
In this work, we present an initial step towards enabling TT scheduling on a real COTS multicore platform P4080. It takes into account inter-core interferences in the on-chip network and the memory sub-system. We propose an approach comprising a runtime mechanism and an offline phase. For the runtime mechanism, we propose two servers running on each core-processing time server and memory access server implemented using built-in hardware monitors. Jointly, the two servers on each core, enforce slot-level offline computed server budget reservations, thereby limiting the maximum inter-core interferences introduced and experienced by each task considering different inter-core interference latencies. In the offline phase, we propose a procedure that can be used by any offline scheduler to compute the bound on variability in execution time of each task while allowing different slot-level memory access server budget reservations. We also did a preliminary bare-metal implementation of our proposed runtime mechanism on a real COTS multicore platform P4080. Overall, our proposed method facilitates integration of COTS multicore platforms in TT systems, while maintaining features of TT architecture like slot-level determinism, clock synchronization, etc.
{"title":"Poster Abstract: Slot-Level Time-Triggered Scheduling on COTS Multicore Platform with Resource Contentions","authors":"Ankit Agrawal, G. Fohler, Jan Nowotsch, S. Uhrig, M. Paulitsch","doi":"10.1109/RTAS.2016.7461353","DOIUrl":"https://doi.org/10.1109/RTAS.2016.7461353","url":null,"abstract":"In this work, we present an initial step towards enabling TT scheduling on a real COTS multicore platform P4080. It takes into account inter-core interferences in the on-chip network and the memory sub-system. We propose an approach comprising a runtime mechanism and an offline phase. For the runtime mechanism, we propose two servers running on each core-processing time server and memory access server implemented using built-in hardware monitors. Jointly, the two servers on each core, enforce slot-level offline computed server budget reservations, thereby limiting the maximum inter-core interferences introduced and experienced by each task considering different inter-core interference latencies. In the offline phase, we propose a procedure that can be used by any offline scheduler to compute the bound on variability in execution time of each task while allowing different slot-level memory access server budget reservations. We also did a preliminary bare-metal implementation of our proposed runtime mechanism on a real COTS multicore platform P4080. Overall, our proposed method facilitates integration of COTS multicore platforms in TT systems, while maintaining features of TT architecture like slot-level determinism, clock synchronization, etc.","PeriodicalId":338179,"journal":{"name":"2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124538208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-01DOI: 10.1109/RTAS.2016.7461356
Harrison Kurunathan, Ricardo Severino, A. Koubâa, E. Tovar
Wireless Sensor Networks have been enabling an ever increasing span of applications and usages in the industrial, domestic and commercial domains. Recent advancements in information and communication technologies have been fueling the increasing pervasiveness and ubiquity of this infrastructures, making them an obvious candidate to support the future Internet of Things. Among the prospective applications, however, there are those which present strict requirements in terms of timeliness and reliability, specially in the industrial domain. To address these, the IEEE 802.15.4 standard functionalities were recently enhanced by the IEEE 802.15.4e amendment. Ideas which are prominent in the industrial communication field such as frequency hopping, dedicated and shared timeslots and multichannel communication have been implemented in 802.15.4e. In this line, proposed MAC behaviors such as the Deterministic and Synchronous Multi-channel Extension (DSME) and Time Synchronous Channel Hopping (TSCH), are gaining a lot of attention. Nevertheless, to efficiently address the network demands in terms of latency, resources, and reliability, it is mandatory to carry out a thorough network planning. To achieve this, modeling the fundamental performance limits of such networks is of paramount importance to understand their behavior under the worst-case conditions and to make the appropriate design choices. Network Calculus is an established tool which can accurately compute the worst case bounds of a network. In this paper we provide an insight towards DSME and TSCH by modeling, using Network Calculus formalism, the delay bounds of these MAC behaviors. As a continuation of this work the end-to-end delay bounds will be derived for the rest of the MAC behaviors of IEEE 802.15.4e. Scheduling algorithms will be developed, analyzed and validated as a future work.
{"title":"Poster Abstract: Towards Worst-Case Bounds Analysis of the IEEE 802.15.4e","authors":"Harrison Kurunathan, Ricardo Severino, A. Koubâa, E. Tovar","doi":"10.1109/RTAS.2016.7461356","DOIUrl":"https://doi.org/10.1109/RTAS.2016.7461356","url":null,"abstract":"Wireless Sensor Networks have been enabling an ever increasing span of applications and usages in the industrial, domestic and commercial domains. Recent advancements in information and communication technologies have been fueling the increasing pervasiveness and ubiquity of this infrastructures, making them an obvious candidate to support the future Internet of Things. Among the prospective applications, however, there are those which present strict requirements in terms of timeliness and reliability, specially in the industrial domain. To address these, the IEEE 802.15.4 standard functionalities were recently enhanced by the IEEE 802.15.4e amendment. Ideas which are prominent in the industrial communication field such as frequency hopping, dedicated and shared timeslots and multichannel communication have been implemented in 802.15.4e. In this line, proposed MAC behaviors such as the Deterministic and Synchronous Multi-channel Extension (DSME) and Time Synchronous Channel Hopping (TSCH), are gaining a lot of attention. Nevertheless, to efficiently address the network demands in terms of latency, resources, and reliability, it is mandatory to carry out a thorough network planning. To achieve this, modeling the fundamental performance limits of such networks is of paramount importance to understand their behavior under the worst-case conditions and to make the appropriate design choices. Network Calculus is an established tool which can accurately compute the worst case bounds of a network. In this paper we provide an insight towards DSME and TSCH by modeling, using Network Calculus formalism, the delay bounds of these MAC behaviors. As a continuation of this work the end-to-end delay bounds will be derived for the rest of the MAC behaviors of IEEE 802.15.4e. Scheduling algorithms will be developed, analyzed and validated as a future work.","PeriodicalId":338179,"journal":{"name":"2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131589628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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