Pub Date : 2016-04-11DOI: 10.1109/RTAS.2016.7461331
N. Shivaraman, Sriram Vasudevan, A. Easwaran
Summary form only given. With the increasing complexity of real-time embedded applications and the availability of Commercial-Off-The-Shelf (COTS) multi-cores, time-predictable execution on these platforms has become a necessity. However, there are several challenges to achieving this predictability, primarily arising due to hardware resources shared between the cores (memory controllers, caches and shared interconnect). In this demo, we present a novel System-on-Chip (SoC) architecture based on COTS multi-cores that address some of these challenges. Specifically, we develop an architecture that enables COTS multi-cores to predictably access external memory. This SoC is designed using hybrid hardware platforms comprising a COTS multi-core and closely coupled Field Programmable Gate Array (FPGA), e.g., Xilinx Zynq ZC706. In our design, the COTS multi-core (ARM Cortex-A9 dual-core) is integrated using a high-speed interconnect with an arbiter module and the Memory Interface Generator (MIG) Xilinx memory controller on the FPGA. Through experiments we show that the proposed architecture has a precisely predictable worst-case memory access latency when compared to a COTS-only design.
{"title":"Demo Abstract: Predictable SoC Architecture Based on COTS Multi-Core","authors":"N. Shivaraman, Sriram Vasudevan, A. Easwaran","doi":"10.1109/RTAS.2016.7461331","DOIUrl":"https://doi.org/10.1109/RTAS.2016.7461331","url":null,"abstract":"Summary form only given. With the increasing complexity of real-time embedded applications and the availability of Commercial-Off-The-Shelf (COTS) multi-cores, time-predictable execution on these platforms has become a necessity. However, there are several challenges to achieving this predictability, primarily arising due to hardware resources shared between the cores (memory controllers, caches and shared interconnect). In this demo, we present a novel System-on-Chip (SoC) architecture based on COTS multi-cores that address some of these challenges. Specifically, we develop an architecture that enables COTS multi-cores to predictably access external memory. This SoC is designed using hybrid hardware platforms comprising a COTS multi-core and closely coupled Field Programmable Gate Array (FPGA), e.g., Xilinx Zynq ZC706. In our design, the COTS multi-core (ARM Cortex-A9 dual-core) is integrated using a high-speed interconnect with an arbiter module and the Memory Interface Generator (MIG) Xilinx memory controller on the FPGA. Through experiments we show that the proposed architecture has a precisely predictable worst-case memory access latency when compared to a COTS-only design.","PeriodicalId":338179,"journal":{"name":"2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115371149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-11DOI: 10.1109/RTAS.2016.7461354
Hela Guesmi, Belgacem Ben Hedia, M. Jan, S. Bliudze, S. Bensalem
Developing embedded real-time systems based on the TT paradigm is a challenging task due to the increasing complexity of such systems and the necessity to manage, already in the programming model, the fine-grained temporal constraints and the low-level communication primitives imposed by the temporal firewall abstraction. In embedded systems, high-level component-based design approaches have been proposed in order to allow specification and design of complex real-time systems. However, their final implementations mostly rely on the generation of code for generic execution platforms. On the other hand, a variety of Real-Time Operating System (RTOS), in particular when based on the Time-Triggered (TT) paradigm, guarantee the temporal and behavioural determinism of the executed software. However, these TT-based RTOS do not provide high-level design frameworks enabling the scalable design of complex safety-critical real-time systems. The goal of our work is to couple a high-level component-based design approach based on the RT-BIP (Real-Time Behaviour-Interaction-Priority) framework with a safety-oriented real-time execution platform, implementing the TT approach. Thus, we combine their complementary advantages, by deriving correct-by-construction TT implementations from high-level componentised models. To this end, we propose an automatic transformation process from RT-BIP models into applications for the target platform based on the TT execution model. The process consists in a two-step transformation. The first step transforms a generic RT-BIP model into a restricted one, which lends itself well to an implementation based on TT communication primitives. This step was presented in previous work. The second step, which is the subject of this paper, transforms the resulting model into the TT implementation provided by the PharOS RTOS. We identify the key difficulties in defining this transformation, propose solutions to address these difficulties and study how this transformation can be proven to be semantics-preserving. This transformation is already partially implemented.
{"title":"Poster Abstract: Towards Correct Transformation: From High-Level Models to Time-Triggered Implementations","authors":"Hela Guesmi, Belgacem Ben Hedia, M. Jan, S. Bliudze, S. Bensalem","doi":"10.1109/RTAS.2016.7461354","DOIUrl":"https://doi.org/10.1109/RTAS.2016.7461354","url":null,"abstract":"Developing embedded real-time systems based on the TT paradigm is a challenging task due to the increasing complexity of such systems and the necessity to manage, already in the programming model, the fine-grained temporal constraints and the low-level communication primitives imposed by the temporal firewall abstraction. In embedded systems, high-level component-based design approaches have been proposed in order to allow specification and design of complex real-time systems. However, their final implementations mostly rely on the generation of code for generic execution platforms. On the other hand, a variety of Real-Time Operating System (RTOS), in particular when based on the Time-Triggered (TT) paradigm, guarantee the temporal and behavioural determinism of the executed software. However, these TT-based RTOS do not provide high-level design frameworks enabling the scalable design of complex safety-critical real-time systems. The goal of our work is to couple a high-level component-based design approach based on the RT-BIP (Real-Time Behaviour-Interaction-Priority) framework with a safety-oriented real-time execution platform, implementing the TT approach. Thus, we combine their complementary advantages, by deriving correct-by-construction TT implementations from high-level componentised models. To this end, we propose an automatic transformation process from RT-BIP models into applications for the target platform based on the TT execution model. The process consists in a two-step transformation. The first step transforms a generic RT-BIP model into a restricted one, which lends itself well to an implementation based on TT communication primitives. This step was presented in previous work. The second step, which is the subject of this paper, transforms the resulting model into the TT implementation provided by the PharOS RTOS. We identify the key difficulties in defining this transformation, propose solutions to address these difficulties and study how this transformation can be proven to be semantics-preserving. This transformation is already partially implemented.","PeriodicalId":338179,"journal":{"name":"2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121080616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-11DOI: 10.1109/RTAS.2016.7461348
Laure Abdallah, M. Jan, Jérôme Ermont, C. Fraboul
Many-core architectures are more promising hardware to design real-time systems than multi-core systems as they should enable an easier mastered integration of an higher number of applications, potentially of different level of criticalities. However, the worst-case behavior of the Network-on-Chip (NoC) for both inter-core and core-to-Input/Output (I/O) communications of critical applications must be established. We use the term core-to-I/O for both core communications from or to I/O interfaces. The mapping over the NoC of both critical and non-critical applications has an impact on the network contention these critical communications exhibit. So far, all existing mapping strategies have focused on inter-core communications. However, we claim that many-cores in embedded real-time systems will be integrated within backbone ethernet networks, as they mostly provide ethernet controllers as I/O interfaces. In this work, we first show that ethernet packets can be dropped due to an internal congestion in the NoC, if these core-to-I/O communications are not taken into account while mapping applications. To this end, we rely on a case study from the avionic domain. It is made of a critical Full Authority Digital Engine (FADEC) application and a non-critical Health Monitoring (HM) application of the engine, used for recognizing incipient failure conditions. Based on this analysis, we introduce our approach to map critical and non critical real-time applications over many-cores that reduces the WCTT of core-to-I/O communications. We show for two variants of our case study that our algorithm successfully find a mapping that avoids ethernet packets, whose payload are making the core-to-I/O communications, to be dropped. This demonstrates the benefits of our proposal compared to a state of the art mapping strategy that fails to do so.
{"title":"Poster Abstract: I/O Contention Aware Mapping of Multi-Criticalities Real-Time Applications over Many-Core Architectures","authors":"Laure Abdallah, M. Jan, Jérôme Ermont, C. Fraboul","doi":"10.1109/RTAS.2016.7461348","DOIUrl":"https://doi.org/10.1109/RTAS.2016.7461348","url":null,"abstract":"Many-core architectures are more promising hardware to design real-time systems than multi-core systems as they should enable an easier mastered integration of an higher number of applications, potentially of different level of criticalities. However, the worst-case behavior of the Network-on-Chip (NoC) for both inter-core and core-to-Input/Output (I/O) communications of critical applications must be established. We use the term core-to-I/O for both core communications from or to I/O interfaces. The mapping over the NoC of both critical and non-critical applications has an impact on the network contention these critical communications exhibit. So far, all existing mapping strategies have focused on inter-core communications. However, we claim that many-cores in embedded real-time systems will be integrated within backbone ethernet networks, as they mostly provide ethernet controllers as I/O interfaces. In this work, we first show that ethernet packets can be dropped due to an internal congestion in the NoC, if these core-to-I/O communications are not taken into account while mapping applications. To this end, we rely on a case study from the avionic domain. It is made of a critical Full Authority Digital Engine (FADEC) application and a non-critical Health Monitoring (HM) application of the engine, used for recognizing incipient failure conditions. Based on this analysis, we introduce our approach to map critical and non critical real-time applications over many-cores that reduces the WCTT of core-to-I/O communications. We show for two variants of our case study that our algorithm successfully find a mapping that avoids ethernet packets, whose payload are making the core-to-I/O communications, to be dropped. This demonstrates the benefits of our proposal compared to a state of the art mapping strategy that fails to do so.","PeriodicalId":338179,"journal":{"name":"2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117193401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-11DOI: 10.1109/RTAS.2016.7461338
David Trilla, J. Jalle, Mikel Fernández, J. Abella, F. Cazorla
This paper presents a modelling approach for the timing behavior of real-time embedded systems (RTES) in early design phases. The model focuses on multicore processors - accepted as the next computing platform for RTES - and in particular it predicts the contention tasks suffer in the access to multicore on-chip shared resources. The model presents the key properties of not requiring the application's source code or binary and having high-accuracy and low overhead. The former is of paramount importance in those common scenarios in which several software suppliers work in parallel implementing different applications for a system integrator, subject to different intellectual property (IP) constraints. Our model helps reducing the risk of exceeding the assigned budgets for each application in late design stages and its associated costs.
{"title":"Improving Early Design Stage Timing Modeling in Multicore Based Real-Time Systems","authors":"David Trilla, J. Jalle, Mikel Fernández, J. Abella, F. Cazorla","doi":"10.1109/RTAS.2016.7461338","DOIUrl":"https://doi.org/10.1109/RTAS.2016.7461338","url":null,"abstract":"This paper presents a modelling approach for the timing behavior of real-time embedded systems (RTES) in early design phases. The model focuses on multicore processors - accepted as the next computing platform for RTES - and in particular it predicts the contention tasks suffer in the access to multicore on-chip shared resources. The model presents the key properties of not requiring the application's source code or binary and having high-accuracy and low overhead. The former is of paramount importance in those common scenarios in which several software suppliers work in parallel implementing different applications for a system integrator, subject to different intellectual property (IP) constraints. Our model helps reducing the risk of exceeding the assigned budgets for each application in late design stages and its associated costs.","PeriodicalId":338179,"journal":{"name":"2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131495496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The increasing complexity of embedded applications in modern cars has increased the need of computational power. To meet this requirement the European automotive standard AUTOSAR has introduced the use of multi-core platforms in it version 4.x. In the industry, the applications are often designed and validated by high level models such as Matlab/Simulink before being implemented on AUTOSAR. However, passing from a Simulink synchronous model to a multi-core AUTOSAR implementation is not trivial. In this paper, we present an approach to model formally the synchronous semantic of any multi-periodic Simulink system by Synchronous Dataflow Graph. Our model is constructed on a formal equivalence between the data dependencies imposed by the communication mechanisms in Simulink and the precedence constraints of a synchronous dataflow graph. The resulting graph is equivalent in size to the Simulink description and allows multi/many-core accurate implementation analysis.
{"title":"Modeling Multi-Periodic Simulink Systems by Synchronous Dataflow Graphs","authors":"Enagnon Cédric Klikpo, Jad Khatib, Alix Munier Kordon","doi":"10.1109/RTAS.2016.7461343","DOIUrl":"https://doi.org/10.1109/RTAS.2016.7461343","url":null,"abstract":"The increasing complexity of embedded applications in modern cars has increased the need of computational power. To meet this requirement the European automotive standard AUTOSAR has introduced the use of multi-core platforms in it version 4.x. In the industry, the applications are often designed and validated by high level models such as Matlab/Simulink before being implemented on AUTOSAR. However, passing from a Simulink synchronous model to a multi-core AUTOSAR implementation is not trivial. In this paper, we present an approach to model formally the synchronous semantic of any multi-periodic Simulink system by Synchronous Dataflow Graph. Our model is constructed on a formal equivalence between the data dependencies imposed by the communication mechanisms in Simulink and the precedence constraints of a synchronous dataflow graph. The resulting graph is equivalent in size to the Simulink description and allows multi/many-core accurate implementation analysis.","PeriodicalId":338179,"journal":{"name":"2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122958856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-11DOI: 10.1109/RTAS.2016.7461334
R. Henia, L. Rioux, Nicolas Sordon
Summary form only given. Usually, the industrial practices rely on the subjective judgment of experienced software architects and developers to predict how design decisions may impact the system timing behavior. This is however risky since eventual timing errors are only detected after implementation and integration, when the software execution can be tested on system level, under realistic conditions. At this stage, timing errors may be very costly and time consuming to correct. Therefore, to overcome this problem we need an efficient, reliable and automated timing estimation method applicable already at early design stages and continuing throughout the whole development cycle. Scheduling analysis appears to be the adequate candidate for this purpose. However, its use in the industry is conditioned by a seamless integration in the software development process. This is not always an easy task due to the semantic mismatches that usually exist between the design and the scheduling analysis models. At Thales Research & Technology, we have developed a timing framework called TEMPO that solves the semantic issues through appropriate model transformation rules, thus allowing the integration of scheduling analysis in the development process of real-time embedded software. In this demonstration paper, we present the basic building blocks and functionalities of the TEMPO framework and describe the main visible stages in the model transformations involved.
{"title":"Demo Abstract: TEMPO: Integrating Scheduling Analysis in the Industrial Design Practices","authors":"R. Henia, L. Rioux, Nicolas Sordon","doi":"10.1109/RTAS.2016.7461334","DOIUrl":"https://doi.org/10.1109/RTAS.2016.7461334","url":null,"abstract":"Summary form only given. Usually, the industrial practices rely on the subjective judgment of experienced software architects and developers to predict how design decisions may impact the system timing behavior. This is however risky since eventual timing errors are only detected after implementation and integration, when the software execution can be tested on system level, under realistic conditions. At this stage, timing errors may be very costly and time consuming to correct. Therefore, to overcome this problem we need an efficient, reliable and automated timing estimation method applicable already at early design stages and continuing throughout the whole development cycle. Scheduling analysis appears to be the adequate candidate for this purpose. However, its use in the industry is conditioned by a seamless integration in the software development process. This is not always an easy task due to the semantic mismatches that usually exist between the design and the scheduling analysis models. At Thales Research & Technology, we have developed a timing framework called TEMPO that solves the semantic issues through appropriate model transformation rules, thus allowing the integration of scheduling analysis in the development process of real-time embedded software. In this demonstration paper, we present the basic building blocks and functionalities of the TEMPO framework and describe the main visible stages in the model transformations involved.","PeriodicalId":338179,"journal":{"name":"2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122173301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-11DOI: 10.1109/RTAS.2016.7461355
J. Hennig, H. V. Hasseln, H. Mohammad, S. Resmerita, Stefan Lukesch, A. Naderlinger
Summary form only given. The growing demand for computing power in automotive applications can only be satisfied by embedded multi-core processors. Significant parts of such applications include OEM-owned legacy software, which has been developed for single-core platforms. While the OEM is faced with the issues of parallelizing the software and specifying the requirements to the ECU supplier, the latter has to deal with implementing the required parallelization within the integrated system. The Logical Execution Time (LET) paradigm addresses these concerns in a clear conceptual framework. We present here initial steps for applying the LET model in this respect. This work deals with the parallelization of a legacy electric powertrain coordinator software, by exploiting its existent inherent parallelism. The application software remains unchanged, as adaptations are only made to the middleware. The LET programming model is employed to ensure that the parallelized software has a correct functional and temporal behavior, while giving room for optimizing the parallelization. The Timing Definition Language (TDL) and associated tools are employed to specify LET-based requirements, and to generate system components that ensure LET behavior. While the runtime overhead of TDL components is still under evaluation, it is shown that the required buffer overhead can be kept small by a suitable choosing of LET values. The work describes two conceptual ways for integrating TDL components in AUTOSAR, by using either a complex device driver, or OS schedule tables. Next steps include a prototypical realization of the presented concepts, which will be done in a cooperation between OEM and suppliers. As evidence is gathered on the LET programming discipline's role as a facilitator of interaction between OEM and suppliers, we plan to further pursue LET standardization efforts in AUTOSAR.
{"title":"Poster Abstract: Towards Parallelizing Legacy Embedded Control Software Using the LET Programming Paradigm","authors":"J. Hennig, H. V. Hasseln, H. Mohammad, S. Resmerita, Stefan Lukesch, A. Naderlinger","doi":"10.1109/RTAS.2016.7461355","DOIUrl":"https://doi.org/10.1109/RTAS.2016.7461355","url":null,"abstract":"Summary form only given. The growing demand for computing power in automotive applications can only be satisfied by embedded multi-core processors. Significant parts of such applications include OEM-owned legacy software, which has been developed for single-core platforms. While the OEM is faced with the issues of parallelizing the software and specifying the requirements to the ECU supplier, the latter has to deal with implementing the required parallelization within the integrated system. The Logical Execution Time (LET) paradigm addresses these concerns in a clear conceptual framework. We present here initial steps for applying the LET model in this respect. This work deals with the parallelization of a legacy electric powertrain coordinator software, by exploiting its existent inherent parallelism. The application software remains unchanged, as adaptations are only made to the middleware. The LET programming model is employed to ensure that the parallelized software has a correct functional and temporal behavior, while giving room for optimizing the parallelization. The Timing Definition Language (TDL) and associated tools are employed to specify LET-based requirements, and to generate system components that ensure LET behavior. While the runtime overhead of TDL components is still under evaluation, it is shown that the required buffer overhead can be kept small by a suitable choosing of LET values. The work describes two conceptual ways for integrating TDL components in AUTOSAR, by using either a complex device driver, or OS schedule tables. Next steps include a prototypical realization of the presented concepts, which will be done in a cooperation between OEM and suppliers. As evidence is gathered on the LET programming discipline's role as a facilitator of interaction between OEM and suppliers, we plan to further pursue LET standardization efforts in AUTOSAR.","PeriodicalId":338179,"journal":{"name":"2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132250850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-11DOI: 10.1109/RTAS.2016.7461346
S. M. Sundharam, S. Altmeyer, N. Navet
Summary form only given. Scheduling is crucial in real-time applications. For any real-time system, the desired scheduling policy can be selected based on the scheduling problem itself and the underlying system constraints. This work targets a novel optimization framework which automates the selection and configuration of the scheduling policy. The framework selects the best suited scheduling configuration for a partially specified task set and the given constraints. Our aim is to develop this framework such that the system designer only focuses on the high-level timing behavior of the system, where the implementation choices of the low level timing behavior are taken care of by the framework. The framework fits in the early design phases as a device to automate system synthesis and hide away from the designer the complexity of the underlying runtime environments. In the framework, the system synthesis step involving both analysis and optimization then generates a scheduling solution which at run-time is enforced by the execution environment. This work is a contribution towards a more automated design process building on the wide set of techniques and results developed within the real-time system community.
{"title":"Poster Abstract: An Optimizing Framework for Real-Time Scheduling","authors":"S. M. Sundharam, S. Altmeyer, N. Navet","doi":"10.1109/RTAS.2016.7461346","DOIUrl":"https://doi.org/10.1109/RTAS.2016.7461346","url":null,"abstract":"Summary form only given. Scheduling is crucial in real-time applications. For any real-time system, the desired scheduling policy can be selected based on the scheduling problem itself and the underlying system constraints. This work targets a novel optimization framework which automates the selection and configuration of the scheduling policy. The framework selects the best suited scheduling configuration for a partially specified task set and the given constraints. Our aim is to develop this framework such that the system designer only focuses on the high-level timing behavior of the system, where the implementation choices of the low level timing behavior are taken care of by the framework. The framework fits in the early design phases as a device to automate system synthesis and hide away from the designer the complexity of the underlying runtime environments. In the framework, the system synthesis step involving both analysis and optimization then generates a scheduling solution which at run-time is enforced by the execution environment. This work is a contribution towards a more automated design process building on the wide set of techniques and results developed within the real-time system community.","PeriodicalId":338179,"journal":{"name":"2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121586852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-01DOI: 10.1109/RTAS.2016.7461351
C. CarlosA.Rincon, A. Cheng
Summary form only given. The purpose of this paper is to analyze the performance of the Highest Entropy First (HEF) scheduling algorithm for real-time tasks. The contributions of this paper are: · Generate multiple task sets by implementing the programs from the Seoul National University (SNU) real-time benchmark in Wind River Workbench 3.3 to calculate the WCET and generating the periods by using a linear programming solution aiming to maximize the utilization of the system based on a predefined hyper-period. We implemented the SNU programs (sqrt.c, fibcall.c, crc.c, minver.c and select.c) on a server with an Intel i7-3770 processor running at 3.4 GHz, with 16 GB of RAM and 2 TB hard drive using Wind River Workbench 3.3 to calculate the worst case execution time (WCET). We run each program 100 times to average the results. We created 4 task sets with 2, 3, 4, and 5 tasks respectively. For each task set we used 100 ms as the hyper-period to calculate the periods of the tasks. We implemented a system with implicit deadlines. · Measure the performance of HEF algorithm to schedule real-time tasks using as metrics the number of context switches and deadline-miss ratio. The results from the preliminary performance evaluation show that the number of context switches is directly proportional to the number of tasks in the task set. For the deadline-miss ratio, HEF was able to schedule all the task sets without missing any deadline. Further analysis must be made to confirm that the deadline-miss ratio depends on the utilization of the system (U ≤ 1 = no deadline misses). The HEF algorithm has some similarities with the earliest deadline first algorithm (EDF), therefore we propose as future work to compare the performance of HEF against EDF using the task sets generated by the methodology proposed in this paper.
只提供摘要形式。本文的目的是分析最高熵优先(HEF)调度算法对实时任务的性能。本文的贡献是:·通过在风河工作台3.3中实现来自首尔国立大学(SNU)实时基准的程序来生成多个任务集，以计算WCET，并通过使用线性规划解决方案生成周期，旨在基于预定义的超周期最大化系统利用率。我们在一台运行频率为3.4 GHz、内存为16gb、硬盘为2tb的Intel i7-3770服务器上实现了SNU程序(sqrt.c、fibcall.c、crc.c、minver.c和select.c)，使用Wind River Workbench 3.3计算最坏情况执行时间(WCET)。我们将每个程序运行100次来计算结果的平均值。我们创建了4个任务集，分别包含2、3、4和5个任务。对于每个任务集，我们使用100毫秒作为超周期来计算任务的周期。我们执行了一个带有隐式截止日期的系统。·衡量HEF算法调度实时任务的性能，使用上下文切换次数和截止日期错过率作为度量标准。初步的性能评估结果表明，上下文切换的次数与任务集中的任务数量成正比。对于截止日期-错过比率，HEF能够调度所有任务集而不会错过任何截止日期。必须进一步分析，以确认截止日期-错过比率取决于系统的利用率(U≤1 =没有截止日期错过)。HEF算法与最早截止日期优先算法(EDF)有一些相似之处，因此我们建议在未来的工作中使用本文提出的方法生成的任务集来比较HEF和EDF的性能。
{"title":"Poster Abstract: Preliminary Performance Evaluation of HEF Scheduling Algorithm","authors":"C. CarlosA.Rincon, A. Cheng","doi":"10.1109/RTAS.2016.7461351","DOIUrl":"https://doi.org/10.1109/RTAS.2016.7461351","url":null,"abstract":"Summary form only given. The purpose of this paper is to analyze the performance of the Highest Entropy First (HEF) scheduling algorithm for real-time tasks. The contributions of this paper are: · Generate multiple task sets by implementing the programs from the Seoul National University (SNU) real-time benchmark in Wind River Workbench 3.3 to calculate the WCET and generating the periods by using a linear programming solution aiming to maximize the utilization of the system based on a predefined hyper-period. We implemented the SNU programs (sqrt.c, fibcall.c, crc.c, minver.c and select.c) on a server with an Intel i7-3770 processor running at 3.4 GHz, with 16 GB of RAM and 2 TB hard drive using Wind River Workbench 3.3 to calculate the worst case execution time (WCET). We run each program 100 times to average the results. We created 4 task sets with 2, 3, 4, and 5 tasks respectively. For each task set we used 100 ms as the hyper-period to calculate the periods of the tasks. We implemented a system with implicit deadlines. · Measure the performance of HEF algorithm to schedule real-time tasks using as metrics the number of context switches and deadline-miss ratio. The results from the preliminary performance evaluation show that the number of context switches is directly proportional to the number of tasks in the task set. For the deadline-miss ratio, HEF was able to schedule all the task sets without missing any deadline. Further analysis must be made to confirm that the deadline-miss ratio depends on the utilization of the system (U ≤ 1 = no deadline misses). The HEF algorithm has some similarities with the earliest deadline first algorithm (EDF), therefore we propose as future work to compare the performance of HEF against EDF using the task sets generated by the methodology proposed in this paper.","PeriodicalId":338179,"journal":{"name":"2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)","volume":"210 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122426051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-01DOI: 10.1109/RTAS.2016.7461336
S. Narayana, Pengcheng Huang, G. Giannopoulou, L. Thiele, R. V. Prasad
In this paper we study a general energy minimization problem for mixed-criticality systems on multi-cores, considering different system operation modes, and static & dynamic energy consumption. While making global scheduling decisions, trade-offs in energy consumption between different modes and also between static and dynamic energy consumption are required. Thus, such a problem is challenging. To this end, we first develop an optimal solution analytically for unicore and a corresponding low-complexity heuristic. Leveraging this, we further propose energy-aware mapping techniques and explore energy savings for multi-cores. To the best of our knowledge, we are the first to investigate mixed-criticality energy minimization in such a general setting. The effectiveness of our approaches in energy reduction is demonstrated through both extensive simulations and a realistic industrial application.
{"title":"Exploring Energy Saving for Mixed-Criticality Systems on Multi-Cores","authors":"S. Narayana, Pengcheng Huang, G. Giannopoulou, L. Thiele, R. V. Prasad","doi":"10.1109/RTAS.2016.7461336","DOIUrl":"https://doi.org/10.1109/RTAS.2016.7461336","url":null,"abstract":"In this paper we study a general energy minimization problem for mixed-criticality systems on multi-cores, considering different system operation modes, and static & dynamic energy consumption. While making global scheduling decisions, trade-offs in energy consumption between different modes and also between static and dynamic energy consumption are required. Thus, such a problem is challenging. To this end, we first develop an optimal solution analytically for unicore and a corresponding low-complexity heuristic. Leveraging this, we further propose energy-aware mapping techniques and explore energy savings for multi-cores. To the best of our knowledge, we are the first to investigate mixed-criticality energy minimization in such a general setting. The effectiveness of our approaches in energy reduction is demonstrated through both extensive simulations and a realistic industrial application.","PeriodicalId":338179,"journal":{"name":"2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115096418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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