Pub Date : 2017-07-01DOI: 10.1109/ISSCS.2017.8034946
A. Korotkov, V. Loboda, A. Feldhoff, D. Groeneveld
Thermoelectric generators (TEG) have been widely used as autonomous energy sources for a wide spectrum of applications that require output power from several mW to several W. The paper below presents simulation results compared to the experiments for the two mass production TEG types. TEGs have been simulated based on the finite element method (FEM) within ANSYS Workbench software platform, which allowed TEG workload mode and output power calculations within the operating temperature gap. The simulation results demonstrate appropriate compliance with the experimental measurements.
{"title":"Simulation of thermoelectric generators and its results experimental verification","authors":"A. Korotkov, V. Loboda, A. Feldhoff, D. Groeneveld","doi":"10.1109/ISSCS.2017.8034946","DOIUrl":"https://doi.org/10.1109/ISSCS.2017.8034946","url":null,"abstract":"Thermoelectric generators (TEG) have been widely used as autonomous energy sources for a wide spectrum of applications that require output power from several mW to several W. The paper below presents simulation results compared to the experiments for the two mass production TEG types. TEGs have been simulated based on the finite element method (FEM) within ANSYS Workbench software platform, which allowed TEG workload mode and output power calculations within the operating temperature gap. The simulation results demonstrate appropriate compliance with the experimental measurements.","PeriodicalId":338255,"journal":{"name":"2017 International Symposium on Signals, Circuits and Systems (ISSCS)","volume":"40 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120811417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-01DOI: 10.1109/ISSCS.2017.8034920
A. Sirbu, I. Alecsandrescu
The paper proposes a new clustering approach based on genetic algorithms (GA) and devoted to improving energy efficiency in ad-hoc wireless sensor networks (WSN). A special designed MATLAB framework operates as test bench to evaluate different implementations. The solutions of the optimization algorithms provide the number of clusters along with the cluster structures. Real-time implementations of such algorithms justify the necessity to minimize their execution time. We have devised custom genetic operators in order to improve the GA convergence. The process of fine tuning of the GA parameters proved to be also extremely important. Intensive simulation studies have confirmed the validity and efficiency of the proposed solutions. Using our approach, we have improved the speed of convergence for the GA up to 50%, as compared with existing approaches, while reducing considerably the minimum communication distance in the ad-hoc WSN.
{"title":"Enhanced genetic algorithm for energy efficient dynamic ad hoc wireless sensor networks","authors":"A. Sirbu, I. Alecsandrescu","doi":"10.1109/ISSCS.2017.8034920","DOIUrl":"https://doi.org/10.1109/ISSCS.2017.8034920","url":null,"abstract":"The paper proposes a new clustering approach based on genetic algorithms (GA) and devoted to improving energy efficiency in ad-hoc wireless sensor networks (WSN). A special designed MATLAB framework operates as test bench to evaluate different implementations. The solutions of the optimization algorithms provide the number of clusters along with the cluster structures. Real-time implementations of such algorithms justify the necessity to minimize their execution time. We have devised custom genetic operators in order to improve the GA convergence. The process of fine tuning of the GA parameters proved to be also extremely important. Intensive simulation studies have confirmed the validity and efficiency of the proposed solutions. Using our approach, we have improved the speed of convergence for the GA up to 50%, as compared with existing approaches, while reducing considerably the minimum communication distance in the ad-hoc WSN.","PeriodicalId":338255,"journal":{"name":"2017 International Symposium on Signals, Circuits and Systems (ISSCS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121433426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-01DOI: 10.1109/ISSCS.2017.8034911
Celal Avci, E. O. Gunes, B. Yarman
In this work, a novel “Broadband-Wide Phase Range” and compact digital phase shifter topology is proposed based on the modified symmetrical lattice structures. The generic topology is suitable for MMIC implementation. The concept proof is exhibited on silicon substrate utilizing the 0.18um TSMC CMOS process. It is shown that proposed architecture results in feasible 45°, 90° and 180° phase shifting cells over combined C and X bands with less than 3 dB loss.
{"title":"A novel Broadband-Wide Phase Range digital phase shifter topology","authors":"Celal Avci, E. O. Gunes, B. Yarman","doi":"10.1109/ISSCS.2017.8034911","DOIUrl":"https://doi.org/10.1109/ISSCS.2017.8034911","url":null,"abstract":"In this work, a novel “Broadband-Wide Phase Range” and compact digital phase shifter topology is proposed based on the modified symmetrical lattice structures. The generic topology is suitable for MMIC implementation. The concept proof is exhibited on silicon substrate utilizing the 0.18um TSMC CMOS process. It is shown that proposed architecture results in feasible 45°, 90° and 180° phase shifting cells over combined C and X bands with less than 3 dB loss.","PeriodicalId":338255,"journal":{"name":"2017 International Symposium on Signals, Circuits and Systems (ISSCS)","volume":"717 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121997536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-01DOI: 10.1109/ISSCS.2017.8034877
V. A. Nita, R. Dobre, S. Ciochină, C. Paleologu
The convergence analysis of the affine projection algorithm (APA) was intensively studied, however, it is far to be a trivial task. In this context, a set of assumptions have to be considered, in order to allow a tractable analytical approach. As a consequence, notable differences occur between the simulation results and the analytical model. In this paper, the convergence of APA is studied and a refined approximation is proposed, named “the third level of approximation.” The results show a near perfect matching between the theoretical model and simulation results, in terms of the asymptotic behavior and convergence speed of the studied algorithm.
{"title":"Improved convergence model of the affine projection algorithm for system identification","authors":"V. A. Nita, R. Dobre, S. Ciochină, C. Paleologu","doi":"10.1109/ISSCS.2017.8034877","DOIUrl":"https://doi.org/10.1109/ISSCS.2017.8034877","url":null,"abstract":"The convergence analysis of the affine projection algorithm (APA) was intensively studied, however, it is far to be a trivial task. In this context, a set of assumptions have to be considered, in order to allow a tractable analytical approach. As a consequence, notable differences occur between the simulation results and the analytical model. In this paper, the convergence of APA is studied and a refined approximation is proposed, named “the third level of approximation.” The results show a near perfect matching between the theoretical model and simulation results, in terms of the asymptotic behavior and convergence speed of the studied algorithm.","PeriodicalId":338255,"journal":{"name":"2017 International Symposium on Signals, Circuits and Systems (ISSCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125597416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-01DOI: 10.1109/ISSCS.2017.8034889
D. Chiper, A. Cracan
Using a new input restructuring sequence and an appropriate reordering of the elements involved, a new VLSI algorithm that uses short length pseudo-cycle convolution structures for the VLSI implementation of discrete sine transform is presented. It uses a new parallel decomposition of discrete sine transform (DST) that leads to a high throughput VLSI implementation with a low hardware cost. The proposed algorithm is efficiently mapped onto two linear systolic arrays that have a modular and regular structure with a a low I/O cost and local and regular interconnections. Thus, an efficient VLSI implementation with high performances can be obtained.
{"title":"A novel algorithm and architecture for a high-throughput VLSI implementation of DST using short pseudo-cycle convolutions","authors":"D. Chiper, A. Cracan","doi":"10.1109/ISSCS.2017.8034889","DOIUrl":"https://doi.org/10.1109/ISSCS.2017.8034889","url":null,"abstract":"Using a new input restructuring sequence and an appropriate reordering of the elements involved, a new VLSI algorithm that uses short length pseudo-cycle convolution structures for the VLSI implementation of discrete sine transform is presented. It uses a new parallel decomposition of discrete sine transform (DST) that leads to a high throughput VLSI implementation with a low hardware cost. The proposed algorithm is efficiently mapped onto two linear systolic arrays that have a modular and regular structure with a a low I/O cost and local and regular interconnections. Thus, an efficient VLSI implementation with high performances can be obtained.","PeriodicalId":338255,"journal":{"name":"2017 International Symposium on Signals, Circuits and Systems (ISSCS)","volume":"288 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124154446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-01DOI: 10.1109/ISSCS.2017.8034916
R. Arsinte, Teodor Sumalan, E. Lupu
The paper presents a cheaper alternative to the traditional way to implement experiments in Embedded DSP research or teaching laboratory. In this approach, in the test bench, the classical instruments (signal generator, oscilloscope, spectrum analyzer) are replaced by the computer itself. Simple signal generation and acquisition applications make possible to generate and visualize the signals in DSP, voice and audio experiments. The built in and added components of the PC (desktop or laptop) are less expensive than the traditional test bench. The results are comparable with expensive implementations. The proposed structure is important in environments where the correct understanding of the phenomena and quick evaluation are more important than the relative accuracy of the results. In addition, the possibility to integrate quickly the results in computer environments, complex networks and online is a key advantage in connected educational experiments.
{"title":"On the use of Virtual Instrumentation concepts in the test of Embedded signal processing applications","authors":"R. Arsinte, Teodor Sumalan, E. Lupu","doi":"10.1109/ISSCS.2017.8034916","DOIUrl":"https://doi.org/10.1109/ISSCS.2017.8034916","url":null,"abstract":"The paper presents a cheaper alternative to the traditional way to implement experiments in Embedded DSP research or teaching laboratory. In this approach, in the test bench, the classical instruments (signal generator, oscilloscope, spectrum analyzer) are replaced by the computer itself. Simple signal generation and acquisition applications make possible to generate and visualize the signals in DSP, voice and audio experiments. The built in and added components of the PC (desktop or laptop) are less expensive than the traditional test bench. The results are comparable with expensive implementations. The proposed structure is important in environments where the correct understanding of the phenomena and quick evaluation are more important than the relative accuracy of the results. In addition, the possibility to integrate quickly the results in computer environments, complex networks and online is a key advantage in connected educational experiments.","PeriodicalId":338255,"journal":{"name":"2017 International Symposium on Signals, Circuits and Systems (ISSCS)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126957318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-01DOI: 10.1109/ISSCS.2017.8034939
Michael Ebli, M. Pfost
Gallium nitride high electron mobility transistors (GaN-HEMTs) have low capacitances and can achieve low switching losses in applications where hard turn-on is required. Low switching losses imply a fast switching; consequently, fast voltage and current transients occur. However, these transients can be limited by package and layout parasitics even for highly optimized systems. Furthermore, a fast switching requires a fast charging of the input capacitance, hence a high gate current. In this paper, the switching speed limitations of GaN-HEMTs due to the common source inductance and the gate driver supply voltage are discussed. The turn-on behavior of a GaN-HEMT is simulated and the impact of the parasitics and the gate driver supply voltage on the switching losses is described in detail. Furthermore, measurements are performed with an optimized layout for a drain-source voltage of 500V and a drain-source current up to 60 A.
{"title":"An analysis of the switching behavior of GaN-HEMTs","authors":"Michael Ebli, M. Pfost","doi":"10.1109/ISSCS.2017.8034939","DOIUrl":"https://doi.org/10.1109/ISSCS.2017.8034939","url":null,"abstract":"Gallium nitride high electron mobility transistors (GaN-HEMTs) have low capacitances and can achieve low switching losses in applications where hard turn-on is required. Low switching losses imply a fast switching; consequently, fast voltage and current transients occur. However, these transients can be limited by package and layout parasitics even for highly optimized systems. Furthermore, a fast switching requires a fast charging of the input capacitance, hence a high gate current. In this paper, the switching speed limitations of GaN-HEMTs due to the common source inductance and the gate driver supply voltage are discussed. The turn-on behavior of a GaN-HEMT is simulated and the impact of the parasitics and the gate driver supply voltage on the switching losses is described in detail. Furthermore, measurements are performed with an optimized layout for a drain-source voltage of 500V and a drain-source current up to 60 A.","PeriodicalId":338255,"journal":{"name":"2017 International Symposium on Signals, Circuits and Systems (ISSCS)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121658230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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