Pub Date : 1988-05-25DOI: 10.1109/ARRAYS.1988.18105
K.R. Liu, K. Yao
This approach provides a systematic way to design a recursive computational architecture instead of a bit-slice architecture. Since the relationship is much stronger at the bit level than at the work level and most relations can be described as shift-and-operate computations, these kinds of relations can be formulated as recursive equations, from which the systolic array can be built without deriving the dependence graph of the bit-level computation. Some design examples for bit-recursive systolic array presented: multiplier, inner product and convolution correlation.<>
{"title":"A systematic approach to bit recursive systolic array design","authors":"K.R. Liu, K. Yao","doi":"10.1109/ARRAYS.1988.18105","DOIUrl":"https://doi.org/10.1109/ARRAYS.1988.18105","url":null,"abstract":"This approach provides a systematic way to design a recursive computational architecture instead of a bit-slice architecture. Since the relationship is much stronger at the bit level than at the work level and most relations can be described as shift-and-operate computations, these kinds of relations can be formulated as recursive equations, from which the systolic array can be built without deriving the dependence graph of the bit-level computation. Some design examples for bit-recursive systolic array presented: multiplier, inner product and convolution correlation.<<ETX>>","PeriodicalId":339807,"journal":{"name":"[1988] Proceedings. International Conference on Systolic Arrays","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123553402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-05-25DOI: 10.1109/ARRAYS.1988.18086
D. Sciuto, F. Lombardi
Different sets of testability conditions for two-dimensional bilateral arrays are presented. Conditions are established with respect to the dependency of the testing process on the signal flow. Each set of testability conditions establishes the controllability and observability of a test vector. These conditions are proved to be applicable under different processing models related to the three inputs of each cell in the array. Complexity issues, such as number of test vectors and time units, are discussed.<>
{"title":"New conditions for testability of two-dimensional bilateral arrays","authors":"D. Sciuto, F. Lombardi","doi":"10.1109/ARRAYS.1988.18086","DOIUrl":"https://doi.org/10.1109/ARRAYS.1988.18086","url":null,"abstract":"Different sets of testability conditions for two-dimensional bilateral arrays are presented. Conditions are established with respect to the dependency of the testing process on the signal flow. Each set of testability conditions establishes the controllability and observability of a test vector. These conditions are proved to be applicable under different processing models related to the three inputs of each cell in the array. Complexity issues, such as number of test vectors and time units, are discussed.<<ETX>>","PeriodicalId":339807,"journal":{"name":"[1988] Proceedings. International Conference on Systolic Arrays","volume":"12 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120837415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-05-25DOI: 10.1109/ARRAYS.1988.18063
K. Wen, J. Wang, J. Lee, M. Lin
Efficient VLSI array processor architectures for maximum-likelihood decoding (MLD) have been developed to meet the high throughput and data processing requirements of modern communication systems. Both 1-D and 2-D MLD processors with large constraint length (>8) have been derived. Radix-4p processing elements and delay commutating switching processors for MLD have been concatenated to construct a pipeline MLD processor. The pipeline length can be adapted to meet the time/area constraints for various applications. A 2-D MLD array processor is also presented. Processing data are modulized, data transmission are embedded into processing elements, and a fixed-size 2-D MLD array is derived to meet high-data-throughput requirements.<>
{"title":"Implementation of array structured maximum likelihood decoders","authors":"K. Wen, J. Wang, J. Lee, M. Lin","doi":"10.1109/ARRAYS.1988.18063","DOIUrl":"https://doi.org/10.1109/ARRAYS.1988.18063","url":null,"abstract":"Efficient VLSI array processor architectures for maximum-likelihood decoding (MLD) have been developed to meet the high throughput and data processing requirements of modern communication systems. Both 1-D and 2-D MLD processors with large constraint length (>8) have been derived. Radix-4p processing elements and delay commutating switching processors for MLD have been concatenated to construct a pipeline MLD processor. The pipeline length can be adapted to meet the time/area constraints for various applications. A 2-D MLD array processor is also presented. Processing data are modulized, data transmission are embedded into processing elements, and a fixed-size 2-D MLD array is derived to meet high-data-throughput requirements.<<ETX>>","PeriodicalId":339807,"journal":{"name":"[1988] Proceedings. International Conference on Systolic Arrays","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125034062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-05-25DOI: 10.1109/ARRAYS.1988.18038
T. V. Vo, J. Litva
A pipelined architecture for implementing a 2-D digital adaptive beamformer is described. The architecture relies heavily on a triangular systolic structure as a means of solving recursive least-squares problems based on the QRD algorithm due to J.G. McWhirter (1983). A manifold of triangular systolic arrays, which in the limit takes the form of a cosmic cube, is used. With the proper time skew format for the data flow, it is shown that the cosmic cube beamformer can concurrently and simultaneously process the data from the rows and columns of array antennas with a speed comparable to the 1-D case. Data memory requirements are modest. It is felt that the beamformer has promise for real-time beamforming with planar array antennas.<>
{"title":"Systolic array for 2-D adaptive beamforming","authors":"T. V. Vo, J. Litva","doi":"10.1109/ARRAYS.1988.18038","DOIUrl":"https://doi.org/10.1109/ARRAYS.1988.18038","url":null,"abstract":"A pipelined architecture for implementing a 2-D digital adaptive beamformer is described. The architecture relies heavily on a triangular systolic structure as a means of solving recursive least-squares problems based on the QRD algorithm due to J.G. McWhirter (1983). A manifold of triangular systolic arrays, which in the limit takes the form of a cosmic cube, is used. With the proper time skew format for the data flow, it is shown that the cosmic cube beamformer can concurrently and simultaneously process the data from the rows and columns of array antennas with a speed comparable to the 1-D case. Data memory requirements are modest. It is felt that the beamformer has promise for real-time beamforming with planar array antennas.<<ETX>>","PeriodicalId":339807,"journal":{"name":"[1988] Proceedings. International Conference on Systolic Arrays","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129473967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-05-25DOI: 10.1109/ARRAYS.1988.18095
J. Eldon
The TMC3211 CMOS-integrated circuit integer divider, which offers a low-power, high-speed, cost-effective solution to the division problem, is presented. Operating on 32-bit dividends and 16-bit divisors and returning 32-bit quotients at 25 million operations per second, the TMC3211 is implemented as a one-dimensional systolic array of 16 identical two-block arithmetic cells, each of which accepts the next two bits of the dividend and generates the next two bits of the quotient, while passing its remainder and the original divisor to the next cell in the series.<>
{"title":"A systolic integrated circuit integer divider","authors":"J. Eldon","doi":"10.1109/ARRAYS.1988.18095","DOIUrl":"https://doi.org/10.1109/ARRAYS.1988.18095","url":null,"abstract":"The TMC3211 CMOS-integrated circuit integer divider, which offers a low-power, high-speed, cost-effective solution to the division problem, is presented. Operating on 32-bit dividends and 16-bit divisors and returning 32-bit quotients at 25 million operations per second, the TMC3211 is implemented as a one-dimensional systolic array of 16 identical two-block arithmetic cells, each of which accepts the next two bits of the dividend and generates the next two bits of the quotient, while passing its remainder and the original divisor to the next cell in the series.<<ETX>>","PeriodicalId":339807,"journal":{"name":"[1988] Proceedings. International Conference on Systolic Arrays","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122178510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-05-25DOI: 10.1109/ARRAYS.1988.18073
M. Payer
The author exemplifies a conceptual framework, namely, the theory of finite-state machines, for the VLSI design process. He starts from a functional description of the system to be realized and achieves a (semi)systolic array in a formal way. The resulting designs are correct by their mere construction.<>
{"title":"Formal derivation of systolic arrays-a case study","authors":"M. Payer","doi":"10.1109/ARRAYS.1988.18073","DOIUrl":"https://doi.org/10.1109/ARRAYS.1988.18073","url":null,"abstract":"The author exemplifies a conceptual framework, namely, the theory of finite-state machines, for the VLSI design process. He starts from a functional description of the system to be realized and achieves a (semi)systolic array in a formal way. The resulting designs are correct by their mere construction.<<ETX>>","PeriodicalId":339807,"journal":{"name":"[1988] Proceedings. International Conference on Systolic Arrays","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132767399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-05-25DOI: 10.1109/ARRAYS.1988.18104
M. Yan, J. McCanny, H. A. Kaouri
The use of bit-level systolic arrays in the design of a vector quantized transformed subband coding system for speech signals is described. It is shown how the major components of this system can be decomposed into a small number of highly regular building blocks that interface directly to one another. These include circuits for the computation of the discrete cosine transform, the inverse discrete cosine transform, and vector quantization codebook search.<>
{"title":"Systolic array system for vector quantization using transformed sub-band coding","authors":"M. Yan, J. McCanny, H. A. Kaouri","doi":"10.1109/ARRAYS.1988.18104","DOIUrl":"https://doi.org/10.1109/ARRAYS.1988.18104","url":null,"abstract":"The use of bit-level systolic arrays in the design of a vector quantized transformed subband coding system for speech signals is described. It is shown how the major components of this system can be decomposed into a small number of highly regular building blocks that interface directly to one another. These include circuits for the computation of the discrete cosine transform, the inverse discrete cosine transform, and vector quantization codebook search.<<ETX>>","PeriodicalId":339807,"journal":{"name":"[1988] Proceedings. International Conference on Systolic Arrays","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131812547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-05-25DOI: 10.1109/ARRAYS.1988.18080
Y. Wong, J. Delosme
A major difficulty with the automatic synthesis of systolic arrays is that many algorithms process data dependences that are not directly realizable in a systolic fashion. The authors consider one particular class of such data dependences, called data sharing or broadcast, in recurrence algorithms. They present a data routing scheme called propagation and show that all broadcasts can be systematically transformed into propagations.<>
{"title":"Broadcast removal in systolic algorithms","authors":"Y. Wong, J. Delosme","doi":"10.1109/ARRAYS.1988.18080","DOIUrl":"https://doi.org/10.1109/ARRAYS.1988.18080","url":null,"abstract":"A major difficulty with the automatic synthesis of systolic arrays is that many algorithms process data dependences that are not directly realizable in a systolic fashion. The authors consider one particular class of such data dependences, called data sharing or broadcast, in recurrence algorithms. They present a data routing scheme called propagation and show that all broadcasts can be systematically transformed into propagations.<<ETX>>","PeriodicalId":339807,"journal":{"name":"[1988] Proceedings. International Conference on Systolic Arrays","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133846347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-05-25DOI: 10.1109/ARRAYS.1988.18066
U. Schwiegelshohn
An algorithm is presented for sorting n/sup 2/ elements on a two-dimensional systolic processor array. It is proved that this algorithm requires O(nlog n) steps in the worst case. The state of the whole processor array recurs every eight steps, so no global control is necessary. An easy realization of this array on a VLSI circuit is thus possible, and the structure of an elementary processor cell is given. The sorting algorithm is well suited to solve problems of data transfer in locally connected parallel processors with distributed energy.<>
{"title":"A shortperiodic two-dimensional systolic sorting algorithm","authors":"U. Schwiegelshohn","doi":"10.1109/ARRAYS.1988.18066","DOIUrl":"https://doi.org/10.1109/ARRAYS.1988.18066","url":null,"abstract":"An algorithm is presented for sorting n/sup 2/ elements on a two-dimensional systolic processor array. It is proved that this algorithm requires O(nlog n) steps in the worst case. The state of the whole processor array recurs every eight steps, so no global control is necessary. An easy realization of this array on a VLSI circuit is thus possible, and the structure of an elementary processor cell is given. The sorting algorithm is well suited to solve problems of data transfer in locally connected parallel processors with distributed energy.<<ETX>>","PeriodicalId":339807,"journal":{"name":"[1988] Proceedings. International Conference on Systolic Arrays","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116907332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-05-25DOI: 10.1109/ARRAYS.1988.18047
M.-J. Chen, K. Yao
The use of square-root-free linear systolic array structure to perform the QR decomposition needed in the solution of least-squares (LS) problems is proposed. A form of the Kalman filter algorithm is applied to perform the recursive LS estimation. Compared with the conventional triangular systolic array structure for LS estimation, the linear array has the advantage of requiring less area and being simpler for VLSI implementation.<>
{"title":"Linear systolic array for least-squares estimation","authors":"M.-J. Chen, K. Yao","doi":"10.1109/ARRAYS.1988.18047","DOIUrl":"https://doi.org/10.1109/ARRAYS.1988.18047","url":null,"abstract":"The use of square-root-free linear systolic array structure to perform the QR decomposition needed in the solution of least-squares (LS) problems is proposed. A form of the Kalman filter algorithm is applied to perform the recursive LS estimation. Compared with the conventional triangular systolic array structure for LS estimation, the linear array has the advantage of requiring less area and being simpler for VLSI implementation.<<ETX>>","PeriodicalId":339807,"journal":{"name":"[1988] Proceedings. International Conference on Systolic Arrays","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114861990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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